oups

2026-03-05 10:24:10 +00:00 · 2021-06-21 03:15:39 -04:00
parent b2e4a450e1
commit 5cdec193d2
1 changed files with 0 additions and 1 deletions
--- a/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
+++ b/sbus-to-ztex-gateware-migen/sbus_to_fpga_fsm.py
@@ -856,7 +856,6 @@ class SBusFPGABus(Module):
        self.submodules.wishbone_slave_buffering_fsm = wishbone_slave_buffering_fsm = FSM(reset_state="Reset")
        self.sync += led4.eq(self.master_read_buffer_start)
        wishbone_slave_buffering_fsm.act("Reset",
-                                         led1.eq(0),
                                         led2.eq(0),
                                         led3.eq(0),
                                         NextState("Idle")