github.com/rdolbeau.SBusFPGA
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Fix support for USB, I2C in updated Litex & submodules

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This commit is contained in:
Romain Dolbeau
2022-11-18 09:54:29 +01:00
parent 260f513e2c
commit 9d6e3c075e
3 changed files with 4 additions and 3 deletions
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1
sbus-to-ztex-gateware-migen/deps/gateware Submodule

Submodule sbus-to-ztex-gateware-migen/deps/gateware added at 5812818ae2

4
sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
View File

@@ -165,7 +165,7 @@ class _CRG(Module):
if (usb):
self.submodules.usb_pll = usb_pll = S7MMCM(speedgrade=platform.speedgrade)
#usb_pll.register_clkin(clk48, 48e6)
usb_pll.register_clkin(self.clk48_bufg, 48e6)
usb_pll.register_clkin(self.clk48_bufg, usb_clk_freq)
usb_pll.create_clkout(self.cd_usb, usb_clk_freq, margin = 0)
platform.add_platform_command("create_generated_clock -name usbclk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
num_clk = num_clk + 1
@@ -203,7 +203,7 @@ class SBusFPGA(SoCCore):
# Add USB Host
def add_usb_host_custom(self, name="usb_host", pads=None, usb_clk_freq=48e6, single_dvma_master=False):
from litex.soc.cores.usb_ohci import USBOHCI
self.submodules.usb_host = USBOHCI(platform=self.platform, pads=pads, usb_clk_freq=usb_clk_freq, dma_data_width=32)
self.submodules.usb_host = USBOHCI(platform=self.platform, pads=pads, usb_clk_freq=int(usb_clk_freq), dma_data_width=32)
usb_host_region_size = 0x10000
usb_host_region = SoCRegion(origin=self.mem_map.get(name, None), size=usb_host_region_size, cached=False)
self.bus.add_slave("usb_host_ctrl", self.usb_host.wb_ctrl, region=usb_host_region)

2
sbus-to-ztex-gateware-migen/sdram_init.py
View File

@@ -28,7 +28,7 @@ sdram_dfii_pi0_baddress = sdram_dfii_base + 0x010
# /!\ keep up to date with csr /!\
ddrphy_base = 0x00041000
ddrphy_rst = ddrphy_base + 0x000
ddrphy_dly_sel = ddrphy_base + 0x010
ddrphy_dly_sel = ddrphy_base + 0x004
ddrphy_rdly_dq_rst = ddrphy_base + 0x014
ddrphy_rdly_dq_inc = ddrphy_base + 0x018
ddrphy_rdly_dq_bitslip_rst = ddrphy_base + 0x01c