github.com/rdolbeau.SBusFPGA
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rename blit to blit_cg6

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This commit is contained in:
Romain Dolbeau 2022-07-23 12:51:43 +02:00
parent a90021072c
commit b2377276b2
4 changed files with 8 additions and 8 deletions
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6
sbus-to-ztex-gateware-migen/blit.c → sbus-to-ztex-gateware-migen/blit_cg6.c
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@ -1,7 +1,7 @@
/*
~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -S blit.c -march=rv32ib -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles
~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -o blit -march=rv32ib -mabi=ilp32 -T blit.lds -nostartfiles blit.s
~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-objcopy -O binary -j .text blit blit.raw
~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -S blit_cg6.c -march=rv32ib -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles
~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -Os -o blit -march=rv32ib -mabi=ilp32 -T blit_cg6.lds -nostartfiles blit_cg6.s
~/LITEX/riscv64-unknown-elf-gcc-10.1.0-2020.08.2-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-objcopy -O binary -j .text blit blit_cg6.raw
*/
#ifndef HRES

0
sbus-to-ztex-gateware-migen/blit.lds → sbus-to-ztex-gateware-migen/blit_cg6.lds
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8
sbus-to-ztex-gateware-migen/blit.sh → sbus-to-ztex-gateware-migen/blit_cg6.sh
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@ -23,8 +23,8 @@ ARCH=rv32i_zba_zbb_zbt
PARAM="-DHRES=${HRES} -DVRES=${VRES} -DBASE_FB=${BASE_FB}"
if test "x$1" != "xASM"; then
$GCC $OPT -S -o blit.s $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.c
$GCC $OPT -S -o blit_cg6.s $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit_cg6.c
fi
$GCC $OPT -c -o blit.o $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit.s &&
$GCCLINK $OPT -o blit $PARAM -march=$ARCH -mabi=ilp32 -T blit.lds -nostartfiles blit.o &&
$OBJCOPY -O binary -j .text -j .rodata blit blit.raw
$GCC $OPT -c -o blit_cg6.o $PARAM -march=$ARCH -mabi=ilp32 -mstrict-align -fno-builtin-memset -nostdlib -ffreestanding -nostartfiles blit_cg6.s &&
$GCCLINK $OPT -o blit_cg6 $PARAM -march=$ARCH -mabi=ilp32 -T blit_cg6.lds -nostartfiles blit_cg6.o &&
$OBJCOPY -O binary -j .text -j .rodata blit_cg6 blit_cg6.raw

2
sbus-to-ztex-gateware-migen/sbus_to_fpga_soc.py
View File

@ -543,7 +543,7 @@ class SBusFPGA(SoCCore):
self.bus.add_slave("cg6_alt", self.cg6.bus3, SoCRegion(origin=self.mem_map.get("cg6_alt", None), size=0x2000, cached=False))
self.bus.add_master(name="cg6_accel_r5_i", master=self.cg6_accel.ibus)
self.bus.add_master(name="cg6_accel_r5_d", master=self.cg6_accel.dbus)
cg6_rom_file = "blit.raw"
cg6_rom_file = "blit_cg6.raw"
cg6_rom_data = soc_core.get_mem_data(cg6_rom_file, "little")
cg6_rom_len = 4*len(cg6_rom_data);
rounded_cg6_rom_len = 2**log2_int(cg6_rom_len, False)