add preliminary support for PROM-in-flash-NOR using a custom PMod
This commit is contained in:
Romain Dolbeau
parent
a60b731d72
commit
c4717d4bd6
@ -1 +1 @@
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Subproject commit c708a834691efb34bbcc7d4c0022dd2f59aa7e4d
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Subproject commit 1697001fb4f7d929005db86bd44a5339f750cf15
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@ -24,6 +24,8 @@ for V in "V1_2"; do
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#echo "rom = ["
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#cat /tmp/${PFX}.txt_hexa
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#echo "]"
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hexdump -v -e '1/4 "%08x"' -e '"\n"' ${PFX}.fc | xxd -r -p > ${PFX}_flash_little.fc
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fi
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done
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@ -25,21 +25,27 @@ ADDR_PHYS_LOW = 0
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ADDR_PFX_HIGH = ADDR_PHYS_HIGH
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ADDR_PFX_LOW = 16 ## 64 KiB per prefix
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ADDR_PFX_LENGTH = 12 #(1 + ADDR_PFX_HIGH - ADDR_PFX_LOW)
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ROM_ADDR_PFX = Signal(12, reset = 0x000) # read only
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WISHBONE_CSR_ADDR_PFX = Signal(12, reset = 0x004)
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USBOHCI_ADDR_PFX = Signal(12, reset = 0x008)
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SRAM_ADDR_PFX = Signal(12, reset = 0x009) # unmapped ; LE
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ENGINE_ADDR_PFXA = Signal(12, reset = 0x00a)
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ENGINE_ADDR_PFXB = Signal(12, reset = 0x00b)
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JARETH_ADDR_PFXA = Signal(12, reset = 0x00c)
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JARETH_ADDR_PFXB = Signal(12, reset = 0x00d)
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CG6_BT_ADDR_PFX = Signal(12, reset = 0x020)
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CG6_ALT_ADDR_PFX = Signal(12, reset = 0x028)
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CG6_FHC_ADDR_PFX = Signal(12, reset = 0x030)
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CG3_BT_ADDR_PFX = Signal(12, reset = 0x040)
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FBC_ROM_ADDR_PFX = Signal(12, reset = 0x041)
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#FBC_RAM_ADDR_PFX = Signal(12, reset = 0x042)
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CG6_FBC_ADDR_PFX = Signal(12, reset = 0x070)
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ROM_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x000) # read only
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WISHBONE_CSR_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x004) # 0x00040000
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USBOHCI_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x008)
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SRAM_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x009) # unmapped ; LE
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ENGINE_ADDR_PFXA = Signal(ADDR_PFX_LENGTH, reset = 0x00a)
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ENGINE_ADDR_PFXB = Signal(ADDR_PFX_LENGTH, reset = 0x00b)
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JARETH_ADDR_PFXA = Signal(ADDR_PFX_LENGTH, reset = 0x00c)
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JARETH_ADDR_PFXB = Signal(ADDR_PFX_LENGTH, reset = 0x00d)
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CG6_BT_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x020)
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CG6_ALT_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x028)
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CG6_FHC_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x030)
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CG3_BT_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x040)
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FBC_ROM_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x041) # read only
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#FBC_RAM_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x042) #
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CG6_FBC_ADDR_PFX = Signal(ADDR_PFX_LENGTH, reset = 0x070)
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ADDR_LONG_PFX_HIGH = ADDR_PHYS_HIGH
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ADDR_LONG_PFX_LOW = 26 ## 64 MiB per prefix
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ADDR_LONG_PFX_LENGTH = 2 #(1 + ADDR_LONG_PFX_HIGH - ADDR_LONG_PFX_LOW)
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SPIFLASH_ADDR_LONG_PFX = Signal(ADDR_LONG_PFX_LENGTH, reset = 0x1) # 0x04000000
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wishbone_default_timeout = 120 ##
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sbus_default_timeout = 50 ## must be below 255/2 (two waits)
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@ -541,6 +547,7 @@ class SBusFPGABus(Module):
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_ALT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_LONG_PFX_LOW:ADDR_LONG_PFX_LOW+ADDR_LONG_PFX_LENGTH] == SPIFLASH_ADDR_LONG_PFX) |
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
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NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
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NextValue(SBUS_3V3_ERRs_o, 1),
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@ -598,6 +605,7 @@ class SBusFPGABus(Module):
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_LONG_PFX_LOW:ADDR_LONG_PFX_LOW+ADDR_LONG_PFX_LENGTH] == SPIFLASH_ADDR_LONG_PFX) |
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
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NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
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NextValue(SBUS_3V3_ERRs_o, 1),
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@ -663,6 +671,7 @@ class SBusFPGABus(Module):
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FHC_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG3_BT_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_LONG_PFX_LOW:ADDR_LONG_PFX_LOW+ADDR_LONG_PFX_LENGTH] == SPIFLASH_ADDR_LONG_PFX) |
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(SBUS_3V3_PA_i[ADDR_BIGPFX_LOW:ADDR_BIGPFX_LOW+ADDR_BIGPFX_LENGTH] == CG3_PIXELS_ADDR_BIGPFX)),
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NextValue(SBUS_3V3_ACKs_o, ACK_IDLE), # need to wait for data, don't ACK yet
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NextValue(SBUS_3V3_ERRs_o, 1),
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@ -732,7 +741,6 @@ class SBusFPGABus(Module):
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#NextValue(sbus_master_error_virtual, Cat(SBUS_3V3_PA_i, SBUS_3V3_SIZ_i, Signal(1, reset=0))),
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NextState("Slave_Error")
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).Elif(((SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == WISHBONE_CSR_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == FBC_ROM_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == CG6_FBC_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == USBOHCI_ADDR_PFX) |
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(SBUS_3V3_PA_i[ADDR_PFX_LOW:ADDR_PFX_LOW+ADDR_PFX_LENGTH] == SRAM_ADDR_PFX) |
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@ -212,7 +212,7 @@ class SBusFPGA(SoCCore):
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#if self.irq.enabled:
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#self.irq.add(name, use_loc_if_exists=True)
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def __init__(self, variant, version, sys_clk_freq, trng, stat, usb, sdram, engine, i2c, bw2, cg3, cg6, goblin, cg3_res, sdcard, jareth, **kwargs):
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def __init__(self, variant, version, sys_clk_freq, trng, stat, usb, sdram, engine, i2c, bw2, cg3, cg6, goblin, cg3_res, sdcard, jareth, flash, **kwargs):
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framebuffer = (bw2 or cg3 or cg6 or goblin)
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print(f"Building SBusFPGA for board version {version}")
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@ -229,6 +229,14 @@ class SBusFPGA(SoCCore):
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if (framebuffer and (version == "V1.2")):
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platform.add_extension(ztex213_sbus._vga_pmod_io_v1_2)
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if (i2c and (version == "V1.0")):
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platform.add_extension(ztex213_sbus._tempi2c_pmod_io_v1_0)
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if (i2c and (version == "V1.2")):
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platform.add_extension(ztex213_sbus._tempi2c_pmod_io_v1_2)
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if (flash and (version == "V1.2")):
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platform.add_extension(ztex213_sbus._flashtemp_pmod_io_v1_2)
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if (framebuffer):
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hres = int(cg3_res.split("@")[0].split("x")[0])
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@ -265,6 +273,8 @@ class SBusFPGA(SoCCore):
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bus_interconnect = "crossbar",
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**kwargs)
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###### self.cpu.endianness = "big" # some devices use that, such as Flash & SD # should try to figure out eveything that breaks when I do that...
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# *** This mem-map is also exposed in the FSM (matched prefixes) ***
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# and in the PROM (to tell NetBSD where everything is)
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# Currently it is a straight mapping between the two:
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@ -278,6 +288,7 @@ class SBusFPGA(SoCCore):
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# differently.
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self.wb_mem_map = wb_mem_map = {
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"prom": 0x00000000, # 256 Kib ought to be enough for anybody (we're using < 8 Kib now...)
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"spiflash": 0x00000000, # FIXME currently the flash is in 0 as well, limited to 256 KiB
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"csr" : 0x00040000,
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"usb_host": 0x00080000, # OHCI registers are here, not in CSR
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#"usb_shared_mem": 0x00090000, # unused ATM
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@ -295,6 +306,7 @@ class SBusFPGA(SoCCore):
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#"cg6_tec": 0x00701000, # required for compatibility
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"cg3_pixels": 0x00800000, # required for compatibility, 1/2/4/8 MiB for now (up to 0x00FFFFFF inclusive) (bw2, cg3 and cg6 idem)
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"goblin_pixels": 0x01000000, # base address for 16 MiB Goblin Framebuffer
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# "spiflash": 0x04000000, # base address for up to 64 MiB Flash
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"main_ram": 0x80000000, # not directly reachable from SBus mapping (only 0x0 - 0x10000000 is accessible),
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"video_framebuffer":0x80000000 + 0x10000000 - cg3_fb_size, # Updated later
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"dvma_bridge": 0xf0000000, # required to match DVMA virtual addresses
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@ -348,24 +360,36 @@ class SBusFPGA(SoCCore):
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#self.comb += pad_SBUS_DATA_OE_LED_2.eq(SBUS_DATA_OE_LED_2_o)
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#self.comb += SBUS_DATA_OE_LED_o.eq(~SBUS_3V3_INT1s_o)
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prom_file = "prom_{}.fc".format(version.replace(".", "_"))
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#prom_file = "SUNW,501-2325.bin" # real TGX
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#prom_file = "SUNW,501-1415.bin" # real cg3
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#prom_file = "SUNW,501-2253.bin" # real TGX+
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prom_data = soc_core.get_mem_data(filename_or_regions=prom_file, endianness="big")
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# prom = Array(prom_data)
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#print("\n****************************************\n")
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#for i in range(len(prom)):
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# print(hex(prom[i]))
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#print("\n****************************************\n")
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prom_len = 4*len(prom_data);
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rounded_prom_len = 2**log2_int(prom_len, False)
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print(f"ROM is {prom_len} bytes, using {rounded_prom_len}")
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assert(rounded_prom_len <= 2**16)
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self.add_ram("prom", origin=self.mem_map["prom"], size=rounded_prom_len, contents=prom_data, mode="r")
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#getattr(self,"prom").mem.init = prom_data
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#getattr(self,"prom").mem.depth = 2**15
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# PROM
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# in the bitstream if no Flash available
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if (not flash):
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prom_file = "prom_{}.fc".format(version.replace(".", "_"))
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#prom_file = "SUNW,501-2325.bin" # real TGX
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#prom_file = "SUNW,501-1415.bin" # real cg3
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#prom_file = "SUNW,501-2253.bin" # real TGX+
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prom_data = soc_core.get_mem_data(filename_or_regions=prom_file, endianness="big")
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# prom = Array(prom_data)
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#print("\n****************************************\n")
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#for i in range(len(prom)):
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# print(hex(prom[i]))
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#print("\n****************************************\n")
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prom_len = 4*len(prom_data);
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rounded_prom_len = 2**log2_int(prom_len, False)
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print(f"ROM is {prom_len} bytes, using {rounded_prom_len}")
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assert(rounded_prom_len <= 2**16)
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self.add_ram("prom", origin=self.mem_map["prom"], size=rounded_prom_len, contents=prom_data, mode="r")
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# SPI Flash
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if (flash):
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from litespi.modules.generated_modules import W25Q128JV
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="4x",
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clk_freq = sys_clk_freq/4, # Fixme; PHY freq ?
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module=W25Q128JV(Codes.READ_1_1_4),
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region_size = 0x00040000,
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with_mmap=True, with_master=False)
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# DDR3
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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@ -596,7 +620,7 @@ def main():
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parser.add_argument("--sdram", action="store_true", help="expose the sdram to the host [all]")
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parser.add_argument("--usb", action="store_true", help="add a USB OHCI controller [V1.2]")
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parser.add_argument("--engine", action="store_true", help="add a Engine crypto core [all]")
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parser.add_argument("--i2c", action="store_true", help="add an I2C bus [V1.2+custom temp. pmod]")
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parser.add_argument("--i2c", action="store_true", help="add an I2C bus [V1.2+TEMPI2C or FLASHTEMP pmod]")
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parser.add_argument("--bw2", action="store_true", help="add a BW2 framebuffer [V1.2+VGA_RGB222 pmod]")
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parser.add_argument("--cg3", action="store_true", help="add a CG3 framebuffer [V1.2+VGA_RGB222 pmod]")
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parser.add_argument("--cg3-res", default="1152x900@76Hz", help="Specify the CG3/CG6 resolution")
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@ -604,6 +628,7 @@ def main():
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parser.add_argument("--goblin", action="store_true", help="add a Goblin framebuffer [V1.2+VGA_RGB222 pmod]")
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parser.add_argument("--sdcard", action="store_true", help="add a sdcard controller [all]")
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parser.add_argument("--jareth", action="store_true", help="add a Jareth vector core [all]")
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parser.add_argument("--flash", action="store_true", help="add a Flash device [V1.2+FLASHTEMP pmod]")
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builder_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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@ -612,11 +637,15 @@ def main():
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print(" ***** WARNING ***** : not enabling the SDRAM still adds a controller, but doesn't add the DMA engines\n")
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if (args.usb and (args.version == "V1.0")):
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print(" ***** WARNING ***** : USB on V1.0 is an ugly hack \n");
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if (args.i2c):
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print(" ***** WARNING ***** : I2C on V1.x is for testing the core \n");
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if (args.i2c and (args.version == "V1.0")):
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print(" ***** WARNING ***** : I2C on V1.0 is for testing the core \n");
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if ((args.bw2 or args.cg3 or args.cg6 or args.goblin) and (args.version == "V1.0")):
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print(" ***** ERROR ***** : VGA not supported on V1.0\n")
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assert(False)
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if (args.flash and (args.version == "V1.0")):
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print(" ***** ERROR ***** : Flash not supported on V1.0\n");
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assert(False)
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fbcount = 0
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if (args.bw2):
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fbcount = fbcount + 1
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@ -648,7 +677,8 @@ def main():
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goblin=args.goblin,
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cg3_res=args.cg3_res,
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sdcard=args.sdcard,
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jareth=args.jareth)
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jareth=args.jareth,
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flash=args.flash)
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#soc.add_uart(name="uart", baudrate=115200, fifo_depth=16)
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version_for_filename = args.version.replace(".", "_")
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@ -115,16 +115,16 @@
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: dphy_rst_wr ( value -- )
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ddrphy-virt h# 0000 + l!
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;
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: dphy_half_sys8x_taps_wr ( value -- )
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: dphy_dly_sel_wr ( value -- )
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ddrphy-virt h# 0004 + l!
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;
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: dphy_wlevel_en_wr ( value -- )
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: dphy_half_sys8x_taps_wr ( value -- )
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ddrphy-virt h# 0008 + l!
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;
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: dphy_wlevel_strobe_wr ( value -- )
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: dphy_wlevel_en_wr ( value -- )
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ddrphy-virt h# 000c + l!
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;
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: dphy_dly_sel_wr ( value -- )
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: dphy_wlevel_strobe_wr ( value -- )
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ddrphy-virt h# 0010 + l!
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;
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: dphy_rdly_dq_rst_wr ( value -- )
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@ -151,6 +151,8 @@
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: dphy_wrphase_wr ( value -- )
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ddrphy-virt h# 0030 + l!
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;
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: sdr_dfii_control_wr ( value -- )
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sdram-virt h# 0000 + l!
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;
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@ -183,7 +183,8 @@ _usb_io_v1_0 = [
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_connectors_v1_0 = [
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]
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_connectors_v1_2 = [
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("P1", "T8 P3 T1 R1 U6 P4 U4 T3"), # swapped line?
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("P1", "T8 P3 T1 R1 U6 P4 U4 T3"), # swapped line? & columns?
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# PMOD- 11 9 7 5 12 10 8 6
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]
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# I2C ----------------------------------------------------------------------------------------------
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@ -213,6 +214,17 @@ def tempi2c_pmod_io(pmod):
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]
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_tempi2c_pmod_io_v1_2 = tempi2c_pmod_io("P1")
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def flashtemp_pmod_io(pmod):
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return [
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("spiflash4x", 0,
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Subsignal("cs_n", Pins(f"{pmod}:2")),
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Subsignal("clk", Pins(f"{pmod}:5")),
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Subsignal("dq", Pins(f"{pmod}:4 {pmod}:1 {pmod}:0 {pmod}:6")),
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IOStandard("LVCMOS33")
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),
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]
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_flashtemp_pmod_io_v1_2 = flashtemp_pmod_io("P1")
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# VGA ----------------------------------------------------------------------------------------------
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def vga_rgb222_pmod_io(pmod):
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@ -284,6 +296,10 @@ class Platform(XilinxPlatform):
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"V1.0" : _i2c_v1_0,
|
||||
"V1.2" : _tempi2c_pmod_io_v1_2,
|
||||
}[version]
|
||||
flashrom = {
|
||||
"V1.0": None,
|
||||
"V1.2": _flashtemp_pmod_io_v1_2,
|
||||
}
|
||||
self.avail_irqs = {
|
||||
"V1.0" : { 1 }, # don't add 7 here, too risky
|
||||
"V1.2" : { 1, 2, 3, 4, 5, 6 },
|
||||
@ -297,7 +313,6 @@ class Platform(XilinxPlatform):
|
||||
XilinxPlatform.__init__(self, device, _io, connectors, toolchain="vivado")
|
||||
self.add_extension(sbus_io)
|
||||
self.add_extension(sbus_sbus)
|
||||
self.add_extension(i2c)
|
||||
|
||||
self.toolchain.opt_directive = "Explore"
|
||||
#self.toolchain.vivado_place_directive = "Explore"
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user