more V1.0 to V1.2 update stuff
This commit is contained in:
Romain Dolbeau
parent
34ed2b130a
commit
fa2c511766
@ -12,3 +12,4 @@ h# 80000000 constant sbusfpga_regionaddr_main_ram
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h# fc000000 constant sbusfpga_regionaddr_usb_fake_dma
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h# a0000 constant sbusfpga_regionaddr_curve25519engine
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h# 40000 constant sbusfpga_regionaddr_csr
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h# 1 constant sbusfpga_irq_usb_host
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@ -49,7 +49,8 @@ my-address sbusfpga_regionaddr_usb_host_ctrl + my-space h# 1000 reg
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h# 7c xdrint " slave-burst-sizes" attribute
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h# 7c xdrint " burst-sizes" attribute
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1 xdrint " interrupts" attribute
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\ USB has an interrupt
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sbusfpga_irq_usb_host xdrint " interrupts" attribute
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headers
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-1 instance value regs-virt
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@ -124,12 +124,15 @@ def get_csr_header(regions, constants, csr_base=None, with_access_functions=True
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return r
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def get_csr_forth_header(csr_regions, mem_regions, constants, csr_base=None):
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def get_csr_forth_header(csr_regions, mem_regions, device_irq_map, constants, csr_base=None):
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r = "\\ auto-generated base regions for CSRs in the PROM\n"
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for name, region in csr_regions.items():
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_csraddr_{}".format(name) + "\n"
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for name, region in mem_regions.items():
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r += "h# " + hex(region.origin).replace("0x", "") + " constant " + "sbusfpga_regionaddr_{}".format(name) + "\n"
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for device, irq in device_irq_map.items():
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if ((irq < 7) and (irq > 0)):
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r += "h# " + hex(irq).replace("0x", "") + " constant " + "sbusfpga_irq_{}".format(device) + "\n"
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return r
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@ -27,16 +27,22 @@ from engine import Engine;
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from migen.genlib.cdc import BusSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer;
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# betrusted-io/gateware
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from gateware import i2c;
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import sbus_to_fpga_export;
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import cg3;
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, usb=True):
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def __init__(self, platform, sys_clk_freq, usb=False, sdram=False):
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self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by SBus (via pll), SoC/Wishbone main clock
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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if (sdram):
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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self.clock_domains.cd_idelay = ClockDomain()
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## self.clock_domains.cd_sys = ClockDomain() # 16.67-25 MHz SBus, reset'ed by SBus, native SBus & SYS clock domain
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self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset, we don't want the delay after a warm reset)
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self.clock_domains.cd_sbus = ClockDomain() # 16.67-25 MHz SBus, reset'ed by SBus, native SBus clock domain
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@ -71,26 +77,37 @@ class _CRG(Module):
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self.curve25519_on = Signal()
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num_adv = 1
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num_clk = 0
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self.submodules.pll = pll = S7MMCM(speedgrade=-1)
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#pll.register_clkin(clk48, 48e6)
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pll.register_clkin(self.clk48_bufg, 48e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq, gated_replicas={self.cd_clk100_gated : pll.locked & self.curve25519_on})
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platform.add_platform_command("create_generated_clock -name sysclk [get_pins {{MMCME2_ADV/CLKOUT0}}]")
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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platform.add_platform_command("create_generated_clock -name sys4xclk [get_pins {{MMCME2_ADV/CLKOUT1}}]")
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{MMCME2_ADV/CLKOUT2}}]")
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platform.add_platform_command("create_generated_clock -name sysclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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if (sdram):
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pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
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platform.add_platform_command("create_generated_clock -name sys4xclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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self.comb += pll.reset.eq(~rst_sbus) # | ~por_done
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platform.add_false_path_constraints(self.cd_native.clk, self.cd_sbus.clk)
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platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_native.clk)
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#platform.add_false_path_constraints(self.cd_sys.clk, self.cd_sbus.clk)
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#platform.add_false_path_constraints(self.cd_sbus.clk, self.cd_sys.clk)
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##platform.add_false_path_constraints(self.cd_native.clk, self.cd_sys.clk)
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pll.create_clkout(self.cd_clk50, sys_clk_freq/2, ce=pll.locked & self.curve25519_on)
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platform.add_platform_command("create_generated_clock -name clk50 [get_pins {{MMCME2_ADV/CLKOUT3}}]")
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platform.add_platform_command("create_generated_clock -name clk50 [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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pll.create_clkout(self.cd_clk200, sys_clk_freq*2, ce=pll.locked & self.curve25519_on)
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platform.add_platform_command("create_generated_clock -name clk200 [get_pins {{MMCME2_ADV/CLKOUT4}}]")
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platform.add_platform_command("create_generated_clock -name clk200 [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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num_adv = num_adv + 1
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num_clk = 0
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#self.submodules.curve25519_pll = curve25519_pll = S7MMCM(speedgrade=-1)
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#curve25519_clk_freq = 90e6
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@ -127,21 +144,28 @@ class _CRG(Module):
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#usb_pll.register_clkin(clk48, 48e6)
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usb_pll.register_clkin(self.clk48_bufg, 48e6)
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usb_pll.create_clkout(self.cd_usb, 48e6, margin = 0)
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platform.add_platform_command("create_generated_clock -name usbclk [get_pins {{MMCME2_ADV_2/CLKOUT0}}]")
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platform.add_platform_command("create_generated_clock -name usbclk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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num_clk = num_clk + 1
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self.comb += usb_pll.reset.eq(~rst_sbus) # | ~por_done
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platform.add_false_path_constraints(self.cd_sys.clk, self.cd_usb.clk)
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self.submodules.pll_idelay = pll_idelay = S7MMCM(speedgrade=-1)
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#pll_idelay.register_clkin(clk48, 48e6)
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pll_idelay.register_clkin(self.clk48_bufg, 48e6)
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pll_idelay.create_clkout(self.cd_idelay, 200e6, margin = 0)
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platform.add_platform_command("create_generated_clock -name idelayclk [get_pins {{MMCME2_ADV_3/CLKOUT0}}]")
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self.comb += pll_idelay.reset.eq(~rst_sbus) # | ~por_done
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num_adv = num_adv + 1
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num_clk = 0
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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if (sdram):
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self.submodules.pll_idelay = pll_idelay = S7MMCM(speedgrade=-1)
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#pll_idelay.register_clkin(clk48, 48e6)
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pll_idelay.register_clkin(self.clk48_bufg, 48e6)
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pll_idelay.create_clkout(self.cd_idelay, 200e6, margin = 0)
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platform.add_platform_command("create_generated_clock -name idelayclk [get_pins {{{{MMCME2_ADV_{}/CLKOUT{}}}}}]".format(num_adv, num_clk))
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num_clk = num_clk + 1
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self.comb += pll_idelay.reset.eq(~rst_sbus) # | ~por_done
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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num_adv = num_adv + 1
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num_clk = 0
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class SBusFPGA(SoCCore):
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def __init__(self, version, usb, **kwargs):
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def __init__(self, version, usb, sdram, **kwargs):
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print(f"Building SBusFPGA for board version {version}")
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kwargs["cpu_type"] = "None"
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@ -195,7 +219,7 @@ class SBusFPGA(SoCCore):
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"usb_fake_dma": 0xfc000000,
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}
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self.mem_map.update(wb_mem_map)
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self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, usb=usb)
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self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, usb=usb, sdram=sdram)
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self.platform.add_period_constraint(self.platform.lookup_request("SBUS_3V3_CLK", loose=True), 1e9/25e6) # SBus max
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if (version == "V1.0"):
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@ -207,9 +231,10 @@ class SBusFPGA(SoCCore):
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if (usb):
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self.add_usb_host(pads=platform.request("usb"), usb_clk_freq=48e6)
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if (version == "V1.0"):
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pad_usb_interrupt = platform.request("SBUS_3V3_INT1s") ## only one usable
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elif (version == "V1.2"):
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pad_usb_interrupt = platform.request("SBUS_3V3_INT3s") ## can be 1-6, beware others
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print(" ***** WARNING ***** USB on SBusFPGA V1.0 is an ugly hack\n");
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pad_usb_interrupt = platform.get_irq(irq_req=5, device="usb_host", next_down=True, next_up=True)
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if (pad_usb_interrupt is None):
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print(" ***** ERROR ***** USB requires an interrupt")
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sig_usb_interrupt = Signal(reset=1)
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# the 74LVC2G07 takes care of the Z state: 1 -> Z on the bus, 0 -> 0 on the bus (asserted interrupt)
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self.comb += pad_usb_interrupt.eq(sig_usb_interrupt)
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@ -235,15 +260,16 @@ class SBusFPGA(SoCCore):
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#getattr(self,"prom").mem.init = prom_data
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#getattr(self,"prom").mem.depth = 2**14
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 0,
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)
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if (sdram):
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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memtype = "DDR3",
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_sdram("sdram",
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phy = self.ddrphy,
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module = MT41J128M16(sys_clk_freq, "1:4"),
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l2_cache_size = 0,
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)
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# don't enable anything on the SBus side for 20 seconds after power up
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# this avoids FPGA initialization messing with the cold boot process
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# requires us to reset the SPARCstation afterward so the FPGA board
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@ -265,26 +291,30 @@ class SBusFPGA(SoCCore):
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# burst_size=16 should work on Ultra systems, but then they probably should go for 64-bits ET as well...
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# Older systems are probably limited to burst_size=4, (it should always be available)
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burst_size=8
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self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=(32+burst_size*32), depth=burst_size))
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+burst_size*32), depth=burst_size))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+32), depth=burst_size))
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if (sdram):
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self.submodules.tosbus_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=(32+burst_size*32), depth=burst_size))
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self.submodules.fromsbus_fifo = ClockDomainsRenamer({"write": "sbus", "read": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+burst_size*32), depth=burst_size))
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self.submodules.fromsbus_req_fifo = ClockDomainsRenamer({"read": "sbus", "write": "sys"})(AsyncFIFOBuffered(width=((30-log2_int(burst_size))+32), depth=burst_size))
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self.submodules.dram_dma_writer = LiteDRAMDMAWriter(port=self.sdram.crossbar.get_port(mode="write", data_width=burst_size*32),
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fifo_depth=4,
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fifo_buffered=True)
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self.submodules.dram_dma_reader = LiteDRAMDMAReader(port=self.sdram.crossbar.get_port(mode="read", data_width=burst_size*32),
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fifo_depth=4,
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fifo_buffered=True)
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self.submodules.dram_dma_writer = LiteDRAMDMAWriter(port=self.sdram.crossbar.get_port(mode="write", data_width=burst_size*32),
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fifo_depth=4,
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fifo_buffered=True)
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self.submodules.dram_dma_reader = LiteDRAMDMAReader(port=self.sdram.crossbar.get_port(mode="read", data_width=burst_size*32),
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fifo_depth=4,
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fifo_buffered=True)
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self.submodules.exchange_with_mem = ExchangeWithMem(soc=self,
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tosbus_fifo=self.tosbus_fifo,
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fromsbus_fifo=self.fromsbus_fifo,
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fromsbus_req_fifo=self.fromsbus_req_fifo,
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dram_dma_writer=self.dram_dma_writer,
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dram_dma_reader=self.dram_dma_reader,
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burst_size=burst_size,
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do_checksum = True)
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self.submodules.exchange_with_mem = ExchangeWithMem(soc=self,
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tosbus_fifo=self.tosbus_fifo,
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fromsbus_fifo=self.fromsbus_fifo,
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fromsbus_req_fifo=self.fromsbus_req_fifo,
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dram_dma_writer=self.dram_dma_writer,
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dram_dma_reader=self.dram_dma_reader,
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burst_size=burst_size,
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do_checksum = True)
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else:
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self.submodules.tosbus_fifo = None
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self.submodules.fromsbus_fifo = None
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self.submodules.fromsbus_req_fifo = None
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_sbus_bus = SBusFPGABus(platform=self.platform,
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hold_reset=hold_reset,
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@ -323,18 +353,31 @@ class SBusFPGA(SoCCore):
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#self.comb += self.curve25519_on_sync.i.eq(self.curve25519engine.power.fields.on)
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#self.comb += self.crg.curve25519_on.eq(self.curve25519_on_sync.o)
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self.comb += self.crg.curve25519_on.eq(self.curve25519engine.power.fields.on)
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#self.submodules.i2c = i2c.RTLI2C(platform, pads=platform.request("i2c"))
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print("IRQ to Device map:\n")
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print(platform.irq_device_map)
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print("Device to IRQ map:\n")
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print(platform.device_irq_map)
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def main():
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parser = argparse.ArgumentParser(description="SbusFPGA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--version", default="V1.0", help="SBusFPGA board version (default V1.0)")
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parser.add_argument("--sdram", action="store_true", help="add a SDRAM controller (mandatory)")
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parser.add_argument("--usb", action="store_true", help="add a USB OHCI controller")
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builder_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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if (args.sdram == False):
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print(" ***** ERROR ***** : disabling the SDRAM doesn't actually work (too integrated in the SBus FSM...)")
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assert(False)
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soc = SBusFPGA(**soc_core_argdict(args),
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version=args.version,
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sdram=args.sdram,
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usb=args.usb)
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#soc.add_uart(name="uart", baudrate=115200, fifo_depth=16)
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@ -364,6 +407,7 @@ def main():
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csr_forth_contents = sbus_to_fpga_export.get_csr_forth_header(
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csr_regions = soc.csr_regions,
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mem_regions = soc.mem_regions,
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device_irq_map = soc.platform.device_irq_map,
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constants = soc.constants,
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csr_base = soc.mem_regions['csr'].origin)
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write_to_file(os.path.join("prom_csr.fth"), csr_forth_contents)
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@ -185,12 +185,52 @@ _connectors_v1_2 = [
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("P1", "T8 U6 P3 P4 T1 U4 R1 T3"),
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]
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# I2C ----------------------------------------------------------------------------------------------
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# reusing the UART pins !!!
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_i2c_v1_0 = [
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("i2c", 0,
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Subsignal("scl", Pins("V9")),
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Subsignal("sda", Pins("U9")),
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IOStandard("LVCMOS33"))
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]
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# reusing the UART pins !!!
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_i2c_v1_2 = [
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("i2c", 0,
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Subsignal("scl", Pins("V9")),
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Subsignal("sda", Pins("U9")),
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IOStandard("LVCMOS33"))
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]
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk48"
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default_clk_period = 1e9/48e6
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def get_irq(self, device, irq_req, next_down=True, next_up=False):
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irq = irq_req
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if (irq in self.avail_irqs):
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self.avail_irqs.remove(irq)
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self.irq_device_map[irq] = device
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self.device_irq_map[device] = irq
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return self.request("SBUS_3V3_INT{}s".format(irq))
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if (next_down):
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for irq in range(irq_req, 0, -1):
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if (irq in self.avail_irqs):
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self.avail_irqs.remove(irq)
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self.irq_device_map[irq] = device
|
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self.device_irq_map[device] = irq
|
||||
return self.request("SBUS_3V3_INT{}s".format(irq))
|
||||
if (next_up):
|
||||
for irq in range(irq_req, 7, 1):
|
||||
if (irq in self.avail_irqs):
|
||||
self.avail_irqs.remove(irq)
|
||||
self.irq_device_map[irq] = device
|
||||
self.device_irq_map[device] = irq
|
||||
return self.request("SBUS_3V3_INT{}s".format(irq))
|
||||
return None
|
||||
|
||||
def __init__(self, variant="ztex2.13a", version="V1.0"):
|
||||
device = {
|
||||
"ztex2.13a": "xc7a35tcsg324-1",
|
||||
@ -211,10 +251,21 @@ class Platform(XilinxPlatform):
|
||||
"V1.0" : _connectors_v1_0,
|
||||
"V1.2" : _connectors_v1_2,
|
||||
}[version]
|
||||
i2c = {
|
||||
"V1.0" : _i2c_v1_0,
|
||||
"V1.2" : _i2c_v1_2,
|
||||
}[version]
|
||||
self.avail_irqs = {
|
||||
"V1.0" : { 1 }, # don't add 7 here, too risky
|
||||
"V1.2" : { 1, 2, 3, 4, 5, 6 },
|
||||
}[version]
|
||||
self.irq_device_map = dict()
|
||||
self.device_irq_map = dict()
|
||||
|
||||
XilinxPlatform.__init__(self, device, _io, connectors, toolchain="vivado")
|
||||
self.add_extension(sbus_io)
|
||||
self.add_extension(sbus_sbus)
|
||||
self.add_extension(i2c)
|
||||
|
||||
self.toolchain.bitstream_commands = \
|
||||
["set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR No [current_design]",
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user