Romain Dolbeau 10447bb7ec master mode: 1 cycle delay between receiving ACK and reading data...

2020-12-18 07:13:34 -05:00

..

.cvsignore

Add the sbus-to-zex gateware

2020-12-13 14:58:52 +01:00

led8.vhd

Add the sbus-to-zex gateware

2020-12-13 14:58:52 +01:00

Makefile

Add the sbus-to-zex gateware

2020-12-13 14:58:52 +01:00

mastrovito_v2_multiplier.vhd

Add the sbus-to-zex gateware

2020-12-13 14:58:52 +01:00

rom.vhd

change ROM 'LEDs show that the board has been probed'

2020-12-16 05:03:14 -05:00

sbus_fsm_TB.vhd.cpp

Improve reset (?), add IOBUF on some signals that are INOUT when including 'master' mode (but not yet Extended Transfer for which 'master' is a pretty much a prerequisite)

2020-12-16 09:10:18 -05:00

sbus_fsm.vhd

master mode: 1 cycle delay between receiving ACK and reading data...

2020-12-18 07:13:34 -05:00

sbus-to-ztex-timings.xdc

Add the sbus-to-zex gateware

2020-12-13 14:58:52 +01:00

sbus-to-ztex.xdc

Add the sbus-to-zex gateware

2020-12-13 14:58:52 +01:00

UART_TX.vhd

Add the sbus-to-zex gateware

2020-12-13 14:58:52 +01:00