Romain Dolbeau
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10447bb7ec
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master mode: 1 cycle delay between receiving ACK and reading data...
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2020-12-18 07:13:34 -05:00 |
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Romain Dolbeau
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7cbd2d68a6
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ultra-preliminary support for a bus master DMA)
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2020-12-17 07:18:13 -05:00 |
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Romain Dolbeau
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1bec4569ec
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add some extra registers for potential DMA
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2020-12-16 09:37:54 -05:00 |
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Romain Dolbeau
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eb473454ce
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Improve reset (?), add IOBUF on some signals that are INOUT when including 'master' mode (but not yet Extended Transfer for which 'master' is a pretty much a prerequisite)
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2020-12-16 09:10:18 -05:00 |
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Romain Dolbeau
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d1e36d05da
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more comments
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2020-12-16 05:22:50 -05:00 |
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Romain Dolbeau
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d696ae0209
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signal comment
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2020-12-16 05:17:30 -05:00 |
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Romain Dolbeau
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04284d7f6f
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change ROM 'LEDs show that the board has been probed'
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2020-12-16 05:03:14 -05:00 |
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Romain Dolbeau
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0d2fce0146
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disable COUNTER25 heartbeat, remove superfluous state in the FSM (detecting ACK is handled by a variable instead)
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2020-12-15 06:23:14 -05:00 |
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Romain Dolbeau
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e105dcb274
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Add the sbus-to-zex gateware
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2020-12-13 14:58:52 +01:00 |
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