github.com/rdolbeau.VintageBusFPGA_Common
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more oups python....

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This commit is contained in:
Romain Dolbeau 2023-11-18 15:53:10 +01:00
parent a3b1143bef
commit 92ff9831fe
1 changed files with 2 additions and 2 deletions
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4
sdram_init.py
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@ -96,10 +96,10 @@ class DDR3Addr(WishboneMaster):
r += [_WRITE_CMD, self.ddrphy_rdly_dq_bitslip_rst, 1]
for i in range(bitslip):
r += [_WRITE_CMD, self.ddrphy_rdly_dq_bitslip, 1]
r += [_WRITE_CMD, self.ddrphy_rdly_dq_rst, 1]
r += [_WRITE_CMD, self.ddrphy_rdly_dq_rst, 1]
for i in range(delay):
r += [_WRITE_CMD, self.ddrphy_rdly_dq_inc, 1]
r += [_WRITE_CMD, self.ddrphy_dly_sel, 0 ]
r += [_WRITE_CMD, self.ddrphy_dly_sel, 0 ]
return r
def startfb(self):