github.com/rdolbeau.VintageBusFPGA_Common
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This commit is contained in:
Romain Dolbeau
2023-11-18 15:48:24 +01:00
parent 4da55815b0
commit a3b1143bef
1 changed files with 6 additions and 6 deletions
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12
sdram_init.py
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@@ -94,12 +94,12 @@ class DDR3Addr(WishboneMaster):
for module in range(2):
r += [_WRITE_CMD, self.ddrphy_dly_sel, 1<<module ]
r += [_WRITE_CMD, self.ddrphy_rdly_dq_bitslip_rst, 1]
for i in range(bitslip):
r += [_WRITE_CMD, self.ddrphy_rdly_dq_bitslip, 1]
r += [_WRITE_CMD, self.ddrphy_rdly_dq_rst, 1]
for i in range(delay):
r += [_WRITE_CMD, self.ddrphy_rdly_dq_inc, 1]
r += [_WRITE_CMD, self.ddrphy_dly_sel, 0 ]
for i in range(bitslip):
r += [_WRITE_CMD, self.ddrphy_rdly_dq_bitslip, 1]
r += [_WRITE_CMD, self.ddrphy_rdly_dq_rst, 1]
for i in range(delay):
r += [_WRITE_CMD, self.ddrphy_rdly_dq_inc, 1]
r += [_WRITE_CMD, self.ddrphy_dly_sel, 0 ]
return r
def startfb(self):