github.com/rdolbeau.VintageBusFPGA_Common
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common sdram_init

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This commit is contained in:
Romain Dolbeau
2023-11-18 11:54:56 +01:00
parent 9266948658
commit ad54db78be
1 changed files with 2 additions and 2 deletions
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4
sdram_init.py
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@@ -131,7 +131,7 @@ class DDR3Addr(WishboneMaster):
class DDR3Init(DDR3Addr):
def __init__(self, sys_clk_freq, bitslip, delay, sdram_dfii_base, ddrphy_base):
DDR3Addr.__init__(self, sdram_dfii_base = None, ddrphy_base = None)
DDR3Addr.__init__(self, sdram_dfii_base = sdram_dfii_base, ddrphy_base = ddrphy_base)
WishboneMaster.__init__(self,
ddr3_init_instructions(sys_clk_freq) +
ddr3_config_instructions(bitslip, delay) +
@@ -139,7 +139,7 @@ class DDR3Init(DDR3Addr):
class DDR3FBInit(DDR3Addr):
def __init__(self, sys_clk_freq, bitslip, delay, sdram_dfii_base, ddrphy_base):
DDR3Addr.__init__(self, sdram_dfii_base = None, ddrphy_base = None)
DDR3Addr.__init__(self, sdram_dfii_base = sdram_dfii_base, ddrphy_base = ddrphy_base)
WishboneMaster.__init__(self,
ddr3_init_instructions(sys_clk_freq) +
ddr3_config_instructions(bitslip, delay) +