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https://github.com/rdolbeau/VintageBusFPGA_Common.git
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first draft at audio-in-hdmi
This commit is contained in:
Romain Dolbeau
188
goblin_alt_audio.py
Normal file
188
goblin_alt_audio.py
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@@ -0,0 +1,188 @@
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from migen import *
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from migen.genlib.fifo import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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class GoblinAudio(Module, AutoCSR):
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def __init__(self, soc, audio_clk_freq):
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self.hdmiext_audio_clk = hdmiext_audio_clk = Signal() # should be audio_clk_freq/44.1 kHz clock
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self.hdmiext_audio_word_0 = hdmiext_audio_word_0 = Signal(16) # channel 0 of stereo audio (L-PCM)
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self.hdmiext_audio_word_1 = hdmiext_audio_word_1 = Signal(16) # channel 1 of stereo audio (L-PCM)
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self.irq = Signal() # active LOW
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self.busmaster = busmaster = wishbone.Interface()
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# # #
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self.irqctrl = CSRStorage(write_from_dev=True, fields = [CSRField("irq_enable", 1, description = "Enable interrupt"),
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CSRField("irq_clear", 1, description = "Clear interrupt"),
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CSRField("reserved", 30, description = "Reserved"),
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])
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self.irqstatus = CSRStatus(fields = [ CSRField("irq", 1, description = "There's a pending interrupt"),
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CSRField("reserved", 31, description = "Reserved")
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])
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self.ctrl = CSRStorage(write_from_dev=True, fields = [CSRField("buffer_num", 1, description = "Buffer to use"),
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CSRField("reserved0", 7, description = "Reserved"),
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CSRField("play", 1, description = "Play (start with specified buffer and keel looping over all buffers)"),
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CSRField("reserved1", 7, description = "Reserved"),
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CSRField("autostop", 1, description = "Autostop when currently playing buffer is empty"),
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CSRField("reserved2", 7, description = "Reserved"),
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CSRField("reserved3", 8, description = "Reserved"),
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])
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self.bufstatus = CSRStatus(fields = [CSRField("buffer_num", 1, description = "Buffer in use"),
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CSRField("reserved0", 7, description = "Reserved"),
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CSRField("play", 1, description = "Playing"),
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CSRField("reserved1", 7, description = "Reserved"),
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CSRField("buffer_left", 16, description = "samples left"),
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])
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self.buf0_addr = CSRStorage(32, description = "Wishbone base address for audio buffer 0")
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self.buf0_size = CSRStorage(fields = [CSRField("size", 16, description = "Number of samples in audio buffer 0"),
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CSRField("reserved", 16, description = "Reserved"),
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])
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self.buf1_addr = CSRStorage(32, description = "Wishbone base address for audio buffer 1")
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self.buf1_size = CSRStorage(fields = [CSRField("size", 16, description = "Number of samples in audio buffer 1"),
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CSRField("reserved", 16, description = "Reserved"),
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])
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# handle IRQ
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self.sync += If(self.irqctrl.fields.irq_clear, ## auto-reset irq_clear
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self.irqctrl.we.eq(1),
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self.irqctrl.dat_w.eq(self.irqctrl.storage & 0xFFFFFFFD)).Else(
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self.irqctrl.we.eq(0),
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)
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temp_irq = Signal() # long internal irq (can be masked)
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set_irq = Signal() # short transient irq (1 cycle ping from FSM)
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self.sync += temp_irq.eq(set_irq | # transient irq signal
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(temp_irq & ~self.irqctrl.fields.irq_clear)) # keep irq until cleared
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self.comb += self.irq.eq(~(temp_irq & self.irqctrl.fields.irq_enable)) # only notify irq to the host if not disabled # self.irq active low
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self.comb += self.irqstatus.fields.irq.eq(~self.irq) # self.irq active low
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# basic 44.1 KHz clock based on system clock
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audio_max = int((soc.sys_clk_freq / audio_clk_freq) + 0.5)
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audio_max_bits = log2_int(audio_max, False)
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audio_counter = Signal(audio_max_bits)
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self.sync += [
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If((audio_counter == (audio_max - 1)),
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hdmiext_audio_clk.eq(1),
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audio_counter.eq(0),
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).Else(
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hdmiext_audio_clk.eq(0),
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audio_counter.eq(audio_counter + 1),
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),
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]
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next_adr = Signal(30) # wishbone!
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sample_cnt = Signal(16)
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cur_buf = Signal(1)
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next_buf = Signal(1)
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self.comb += [
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self.bufstatus.fields.buffer_num.eq(cur_buf),
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self.bufstatus.fields.buffer_left.eq(sample_cnt),
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]
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need_data = Signal()
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# self-reset need_data, whenever we consume a sample in hdmi (audio_clk) we request more
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self.sync += [
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If(~need_data & hdmiext_audio_clk,
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need_data.eq(1),
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)
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]
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# autostop
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self.sync += [
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If((sample_cnt == 0) & self.ctrl.fields.autostop & hdmiext_audio_clk, # we just consumed the last sample in autostop mode
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self.ctrl.we.eq(1),
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self.ctrl.dat_w.eq(self.ctrl.storage & 0xFFFFFEFF), # reset 'play'
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).Else(
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self.ctrl.we.eq(0),
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),
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]
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self.submodules.play_fsm = play_fsm = FSM(reset_state="Reset")
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play_fsm.act("Reset",
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NextState("Silent")
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)
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play_fsm.act("Silent",
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NextValue(hdmiext_audio_word_0, 0),
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NextValue(hdmiext_audio_word_1, 0),
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If(self.ctrl.fields.play,
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NextValue(cur_buf, self.ctrl.fields.buffer_num),
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NextValue(next_buf, self.ctrl.fields.buffer_num + 1),
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NextValue(need_data, 1),
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Case(self.ctrl.fields.buffer_num, {
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0x0: [
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NextValue(next_adr, self.buf0_addr.storage[2:32]),
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NextValue(sample_cnt, self.buf0_size.fields.size),
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],
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0x1: [
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NextValue(next_adr, self.buf1_addr.storage[2:32]),
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NextValue(sample_cnt, self.buf1_size.fields.size),
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],
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}),
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NextState("Play"),
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)
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)
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play_fsm.act("Play",
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If(~self.ctrl.fields.play,
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NextValue(hdmiext_audio_word_0, 0),
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NextValue(hdmiext_audio_word_1, 0),
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NextState("Silent"),
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).Elif((sample_cnt == 0), # ran out of sample in this buffer
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set_irq.eq(self.irqctrl.fields.irq_enable), # transient notify to the host we emptied a buffer # only raised when enabled
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If(~self.ctrl.fields.autostop,
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NextValue(cur_buf, next_buf),
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NextValue(next_buf, next_buf + 1),
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Case(next_buf, {
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0x0: [
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NextValue(next_adr, self.buf0_addr.storage[2:32]),
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NextValue(sample_cnt, self.buf0_size.fields.size),
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],
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0x1: [
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NextValue(next_adr, self.buf1_addr.storage[2:32]),
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NextValue(sample_cnt, self.buf1_size.fields.size),
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],
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}),
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)
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# stay in "Play"
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)
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)
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led0 = soc.platform.request("user_led", 0)
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self.comb += [
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self.bufstatus.fields.play.eq(play_fsm.ongoing("Play")),
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led0.eq(play_fsm.ongoing("Play")),
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]
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# auto-reload
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self.submodules.req_fsm = req_fsm = FSM(reset_state="Reset")
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req_fsm.act("Reset",
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NextState("Idle")
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)
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req_fsm.act("Idle",
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If(need_data & self.ctrl.fields.play & play_fsm.ongoing("Play") & (sample_cnt != 0),
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NextValue(busmaster.cyc, 1),
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NextValue(busmaster.stb, 1),
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NextValue(busmaster.sel, 2**len(busmaster.sel)-1),
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NextValue(busmaster.we, 0),
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NextValue(busmaster.adr, next_adr),
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NextState("WaitForAck")
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)
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)
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req_fsm.act("WaitForAck",
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If(busmaster.ack,
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NextValue(busmaster.cyc, 0),
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NextValue(busmaster.stb, 0),
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NextValue(hdmiext_audio_word_0, Cat(busmaster.dat_r[ 8:16], busmaster.dat_r[ 0: 8])), # fixme: endianess
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NextValue(hdmiext_audio_word_1, Cat(busmaster.dat_r[24:32], busmaster.dat_r[16:24])), # fixme: endianess
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NextValue(next_adr, next_adr + 1), # fixme
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NextValue(sample_cnt, sample_cnt - 1),
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NextValue(need_data, 0), # this will self-reset to 1 above after the next audio_clk cycle, i.e. when hdmi consume the data
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NextState("Idle"),
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)
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)
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@@ -15,6 +15,8 @@ from litex.soc.cores.video import *
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from VintageBusFPGA_Common.fb_video import *
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from VintageBusFPGA_Common.fb_dma import LiteDRAMFBDMAReader
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from VintageBusFPGA_Common.goblin_alt_audio import GoblinAudio
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from math import ceil
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cmap_layout = [
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@@ -674,6 +676,13 @@ class GoblinAlt(Module, AutoCSR):
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hdmiext_rgb = Signal(24) # three colors at 8 bits each, fixme
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hdmiext_audio_word_0 = Signal(16) # channel 0 of stereo audio, fixme
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hdmiext_audio_word_1 = Signal(16) # channel 1 of stereo audio, fixme
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self.submodules.goblin_audio = GoblinAudio(soc, 44.1e3)
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self.comb += [
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hdmiext_audio_clk.eq(self.goblin_audio.hdmiext_audio_clk),
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hdmiext_audio_word_0.eq(self.goblin_audio.hdmiext_audio_word_0),
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hdmiext_audio_word_1.eq(self.goblin_audio.hdmiext_audio_word_1),
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]
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## OUTPUTS from the HDMI module
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hdmiext_tmds = Signal(3) # high-speed colors to the TMDS bits
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@@ -693,8 +702,8 @@ class GoblinAlt(Module, AutoCSR):
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hdmiext_rgb[ 0: 8].eq(vfb.source.b),
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hdmiext_rgb[ 8:16].eq(vfb.source.g),
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hdmiext_rgb[16:24].eq(vfb.source.r),
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hdmiext_audio_word_0.eq(0), # fixme: implement
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hdmiext_audio_word_1.eq(0), # fixme: implement
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## hdmiext_audio_word_0.eq(0), # fixme: implement
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## hdmiext_audio_word_1.eq(0), # fixme: implement
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# use VTG enable to generate reset, to we have the same relationship to the DMA
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hdmiext_reset.eq(~vtg_enable),
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]
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@@ -757,19 +766,19 @@ class GoblinAlt(Module, AutoCSR):
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vfb.inframe.eq(hinframe & vinframe),
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]
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# basic 44.1 KHz clock based on the HDMI clock
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audio_max = int((vtg.video_timings["pix_clk"] / 44100.0) + 0.5)
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audio_max_bits = log2_int(audio_max, False)
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audio_counter = Signal(audio_max_bits)
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hdmi_sync += [
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If(audio_counter == (audio_max - 1),
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hdmiext_audio_clk.eq(1),
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audio_counter.eq(0),
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).Else(
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hdmiext_audio_clk.eq(0),
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audio_counter.eq(audio_counter + 1),
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),
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]
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### basic 44.1 KHz clock based on the HDMI clock
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##audio_max = int((vtg.video_timings["pix_clk"] / 44100.0) + 0.5)
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##audio_max_bits = log2_int(audio_max, False)
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##audio_counter = Signal(audio_max_bits)
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##hdmi_sync += [
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## If(audio_counter == (audio_max - 1),
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## hdmiext_audio_clk.eq(1),
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## audio_counter.eq(0),
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## ).Else(
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## hdmiext_audio_clk.eq(0),
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## audio_counter.eq(audio_counter + 1),
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## ),
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##]
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self.specials += Instance("hdmi",
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p_VIDEO_ID_CODE = 16, # CEA-861-D, "4.15 1920x1080p @ 59.94/60Hz (Format 16)", FIXME
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