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3b2: Fix for clock drift when idling
When the 3B2 simulator was set to allow idling, there was significant clock drift related to the primary timer unit. It turns out that the simulator was using `AIO_SET_INTERRUPT_LATENCY` and `sim_rtcn_tick_ack` incorrectly. They are not needed with the structure of system timers in the 3B2 architecture.
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@ -388,7 +388,6 @@ static t_stat tod_svc(UNIT *uptr)
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sim_activate_after(uptr, 1000000/CLK_TPS);
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tmr_poll = t;
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tmxr_poll = t;
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AIO_SET_INTERRUPT_LATENCY(tmr_poll * CLK_TPS);
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return SCPE_OK;
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}
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@ -345,8 +345,6 @@ uint32 timer_read(uint32 pa, size_t size)
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of also clearing pending interrupts */
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CSRBIT(CSRCLK, FALSE);
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CPU_CLR_INT(INT_CLOCK);
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/* Acknowledge a clock tick */
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sim_rtcn_tick_ack(1, TMR_CLK);
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retval = 0;
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break;
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default:
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