Problem reported in https://github.com/open-simh/simh/issues/409
There are key differences between the MicroVAX I and MicroVAX II.
Specifically, the MicroVAX I is a machine with direct Qbus memory and
no QBA (Qbus Adapter) which is part of all later MicroVAXen and
corresponds to the UBA (Unibus Adapter) on systems with Unibuxes.
Among possibly other things, these Adapters primarily provide the
translation between the CPU's system memory and addresses on the
respective bus (Qbus or Unibus). These Adapters provide a set of
mapping registers which map the respective bus addresses to desired
locations in CPU memory which allows for "Scatter/Gather" memory
transfers. The MicroVAX I, having its memory directly on the Qbus,
has no CPU specific way to implement "Scatter/Gather" for I/O device
for memory transfers very much needed in systems with virtual memory.
On this system, the Scatter/Gather functionality is provided directly
within the MSCP controller which is simulated by the pdp11_rq.c
module.
On Qbus MicroVAXen with Qbus Adapters, the boot rom initializes all
the Qbus mapping registers such that Qbus addresses map directly to
CPU RAM addresses. This simplifies boot code which don't turn on
Virtual Memory (and thus the need for Scatter/Gather) until later stages
of the operating system boot. The Ultrix boot we're dealing with plays
games with the mapping registers somewhat early in the boot, and
requests a transfer of 0x2000 bytes (words maybe) to an address of
0x010000c8. Note that this would be the address from the point of
view of the controller on the Qbus. This value is actually beyond the
end of the 22bit Qbus address space (0x003fffff). The controller
therefore previously returned a non-existent memory error.
It would seem that instructions performing this I/O request are ones
which were loaded by an earlier read and thus the bug really should
be there, but since this code actually worked on real hardware,
accomodating that behavior belongs in the simulator. Meanwhile,
when this transfer has happened, the QBA Mapping registers have
been changed from their initial values that mapped 1-1 Qbus addresses
to RAM. The proper approach is therefore merely to ignore any bits
in the transfer address beyond the 22bits of the Qbus address space.
Interesting that all other operating systems (or boot code) never
presented a buffer address beyond the maximum 22bit Qbus address.
- Add new CP and CR devices
- COC: Zero delay from SIO to INIT state Detect and UEN on 0xFF order
- COC: Moved SIO int pending test to devices
- DK: Zero delay from SIO to INIT state
- DP: Added case points for RDEES, dp_aio_status
- DP: Zero delay from SIO to INIT state
- defs: Added chaining modifier flag
- defs: Fixed DVT_NODEV definition
- defs: Added chan_chk_dvi definition
- io: Added chaining modifier flag
- LP: Zero delay from SIO to INIT state
- LP: Added INIT test for illegal command
- LP: Moved SIO interrupt test to devices
- MT: Zero delay from SIO to INIT state
- PT: Zero delay from SIO to INIT state
- PT: Moved SIO interrupt test to devices
- RAD: Zero delay from SIO to INIT state
- RAD: Fixed nx unit test
- RAD: Fixed write protect test
- TT: Zero delay from SIO to INIT state
- TT: Moved SIO int pending test to devices
PDP11: RP11: Interrupt on IE+RESET+GO
Recent analysis of the 2.9BSD kernel revealed that RP11 was
expected to interrupt on control RESET function if IE bit was
also set. Documentation was not very clear of the fact, saying
in one place that RESET+GO does not interrupt (which is not
contradictory with the above because it does not mention IE).
In other place, however, it says that IE always causes interrupt
when DONE is asserted. Thus, since RESET does assert DONE, an
interrupt should be posted if IE is set. The autoconfig binary
from 2.9BSD uses this feature of RP11 to check the presence
of the controller.
Formerly RESET was always clearing RPCS with DONE unconditionally,
and that reset IE as well. This patch makes sure that the IE bit
is preserved, and if set, it posts an interrupt when RESET asserts
DONE.
PDP11: RP11: Make sure to advance DA after every I/O
It looks like disk controllers, which automatically update
disk address (DA) after completion of I/O, are expected to do
so even if there was no data transfer because of I/O errors.
I was studying RSX-11's Error Logger documentation and
examples are clearly offsetting disk addresses backwards
by one when I/O errors are reported by the controller.
Since once the controller has found the DA-specified sector,
the I/O begins regardless of the condition of the sector (bad
or good data) or ability to transfer the contents between the
disk and the memory. If an error occurs (NXM, for instance)
the operation would stop (with the error reported) at the end
of the sector. So if, for example, the bus address register
had a bad address from the get-go, no data would be able to
transfer at all, yet DA should still be updated with DA + 1
once the controller asserts the DONE bit.
This patch makes sure that DA is always advanced when I/O has
actually been commenced.
PDP11: RP11: Remove duplicate checks (now only done in svc routine)
PDP11: RP11: Implement delayed CS_DONE for "initiation" commands (SEEK/HOME)
Running earlier XXDP tests revealed that a technique of concurrent command
initiation and continued housekeeping for the command completion was used in
the old code.
For example, code could initiate a SEEK command for a drive, and knowing that
CS_DONE (and thus, an interrupt) is coming in about 16us, it would then go
ahead and clear a flag, which registers that the interrupt has occurred
(expected to be set to 1 by the ISR). If CS_DONE is set by the implementation
at the function initiation immediately, that would mean that the interrupt
could be triggered before the next instruction, and the flag would be set by
the ISR right away. The main code, however, would proceed with the the flag
clear as the following instruction, thus, never detecting the interrupt down
the road.
Since this technique was in existence, it is better to introduce a delay for
setting CS_DONE in the "fast" initiation commands like SEEK and HOME, to
accommodate the software that was relying on it.
So far, however, no issues were encountered in testing (except one), where
this delay mattered, but it's hard to tell if it would not be needed at all.
All I/O commands always delay CS_DONE already because they were never supposed
to be immediate.
Since the time for CS_DONE in initiation commands was documented at 16us, the
introduced delay is set to 10 instructions, which usually took more than that
to execute. But the interrupt flag clear case would be covered, as well as
the counted waits, which used some 25+-iteration tight loops for "drive ready",
before flagging a time-out (so the delay cannot be longer, either).
It also looks like more modern code never used any such tricks, so for it, it
should not matter if CS_DONE was slightly delayed or not.
PDP11: RP11: Major update after XXDP
Having run the device code thru XXDP and some other OS's and scenarios
rigorously, a bunch of discrepancies were found, which need to be addressed
by this rather extensive patch.
1. Each unit must implement its own "drive status" register, to be able to
track per-drive errors / conditions correctly;
2. Fixed INT_SET() / INT_CLR() in RPCS write function (wrong order of the "if"
conditions);
3. Some behavior was implemented not exactly how it was expected from the real
hardware, such as:
a. Post-I/O register values in RPDA and RPCA (including the corner case of
pack overflow);
b. I/O stacking, which wasn't mentioned in any available documentation, but
only XXDP listings;
c. RESET/IDLE function must be accepted for a "busy" controller;
d. HOME function must always execute, even when "device ready" is not set
(e.g. when SEEK error detected);
e. SEEK incomplete should not respond with "device ready" (however, the
condition can be cleared by HOME, d.);
f. WLOA-induced write-lock violation wasn't reflected in "device status".
4. Some timing was off so that the device worked "too fast" -- this was fixed
(except for the pathological cases when the races are in the actual test
code, and cannot be logically fixed);
5. WLOA setup command bug was fixed;
6. Added more code comments found per the above peculiarities.
This fixes the H flag handling for the 8080 CPU and corrects the parity
flag computation for the Z80 CPU for INI, OUTI, IND, OUTD, INIR, OTIR,
INDR and OTDR instructions. It is based on Thomas Eberhardt's work.
Removed previously added DEPOSIT ALL 0 in precalibrate routine.
That DEPOSIT was added to explicitly restore memory to 0's at simulator
startup, but the several second cost of executing that slowed down
startup of any simulator which had precalibration support. Anyone who
explicitly cares to have zeroed memory on startup should include such a
command in their own simulator configuration.
- Fix printf() warnings (format should be long, not int)
- Signed/unsigned mismatch, size_t for array indexing
- Comment out the unused trim() function.
In sim_instr(), the effective address is computed; for the case of TAG
(index register addressing), the contents of the specified index register
is added to the effective address, but the result is not masked to 16
bits as per the hardware functionality.
Adding a a 16 bit mask operation fixes the issue.
Allow: n execute n instructions/cycles per second
nK execute n thousand instructions/cycles per second
nM execute n million instructions/cycles per second
n% occupy x percent of the host CPU capacity
n/t sleep for t milliseconds after executing x
instructions/cycles
n{K|M}/t sleep for t milliseconds after executing x
thousand or million instructions/cycles
Adds the following devices to AltairZ80:
TUART0: Cromemco FDC controller TUART console port at I/O address 0x00.
TUART1: Cromemco TU-ART port A at I/O address 0x20.
TUART2: Cromemco TU-ART port B at I/I address 0x50.
These devices are fully TMXR capable.
This PR makes the following changes to the JAIR devices:
Refactors the service routines into STAT, TX and RX units (thanks @markpizz)
Adds a 128-byte input ring buffer
Corrects a null pointer exception
Adds overrun status bit implementation
Replaces a tab with spaces
