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add ibd_ibtst; tbench code for ibd_ibtst and sdreg

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- ibd_ibtst: added, an ibus tester device
- pdp11_sys70: instantiate ibd_ibtst (when sys_conf_ibtst = true)
- Rw11Cpu,RtclRw11Cpu: add ibmon setup and HasIbtst()
- tcl/ibd_ibtst/util.tcl: added, tcl support for ibd_ibtst
- tbench/w11a/test_w11a_sdreg.tcl: added, tbench for sdreg
- tools/tbench/w11a_ibtst/: added tbench for ibd_ibtst
This commit is contained in:
wfjm 2019-03-01 09:05:29 +01:00
parent 8d323848b3
commit 1206e5d938
20 changed files with 1030 additions and 31 deletions
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6
doc/CHANGELOG.md
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@ -26,14 +26,20 @@ The full set of tests is only run for tagged releases.
### New features
- new components
- fifo_simple_dram: simple fifo with CE/WE interface, dram based
- ibd_ibtst: ibus tester device
- simclkv: test bench clock generator with variable period
- new verification codes
- tbench/w11a_ibtst/*: tbench for ibd_ibtst
- test_w11a_sdreg.tcl: tbench for sdreg
### Changes
- tools changes
- Rw11Cpu,RtclRw11Cpu: add ibmon setup and HasIbtst()
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- firmware changes
- rbd_tester: use now fifo_simple_dram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
- pdp11_sys70: instantiate ibd_ibtst (when sys_conf_ibtst = true)
### Bug Fixes

8
rtl/ibus/ibd_ibtst.vbom Normal file
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@ -0,0 +1,8 @@
# libs
../vlib/slvtypes.vhd
../vlib/memlib/memlib.vhd
iblib.vhd
# components
../vlib/memlib/fifo_simple_dram.vbom
# design
ibd_ibtst.vhd

405
rtl/ibus/ibd_ibtst.vhd Normal file
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@ -0,0 +1,405 @@
-- $Id: ibd_ibtst.vhd 1112 2019-02-17 11:10:04Z mueller $
--
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibd_ibtst - syn
-- Description: ibus dev(rem): ibus tester
--
-- Dependencies: memlib/fifo_simple_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-16 1112 1.0 Initial version
-- 2019-02-09 1110 0.1 First draft
------------------------------------------------------------------------------
--
-- ibus registers:
--
-- Addr Bits IB RB IR Name Function
-- 00 cntl Control register
-- 15 -- 0W 00 fclr fifo clear
-- 7 -- RW 00 datto ibus timeout for bad loc data access
-- 6 -- RW 00 nobyt disallow byte writes to data (loc+rem)
-- 5 -- RW 00 dlyw enable loc write delay for fifo/data
-- 4 -- RW 00 dlyr enable loc read delay for fifo/data
-- 3 -- RW 11 remw enable rem write for fifo/data
-- 2 -- RW 11 remr enable rem read for fifo/data
-- 1 -- RW 00 locw enable loc write for fifo/data
-- 0 -- RW 00 locr enable loc read for fifo/data
-- 01 -- R- stat Status register (moni last data/fifo)
-- 15:12 -- R- fsize fifo size
-- 6 -- R- racc remote access seen
-- 5 -- R- cacc console access seen
-- 4 -- R- be1 byte enable high seen
-- 3 -- R- be0 byte enable low seen
-- 2 -- R- rmw read-modify-write seen
-- 1 -- R- we write enable seen
-- 0 -- R- re read enable seen
-- 10 rw rw 00 data data register (byte/word writable)
-- 11 rw rw fifo fifo interface register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_ibtst is -- ibus dev(rem): ibus tester
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16))); -- base address
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end ibd_ibtst;
architecture syn of ibd_ibtst is
constant ibaddr_cntl : slv2 := "00"; -- cntl address offset
constant ibaddr_stat : slv2 := "01"; -- stat address offset
constant ibaddr_data : slv2 := "10"; -- bdat address offset
constant ibaddr_fifo : slv2 := "11"; -- wdat address offset
constant cntl_ibf_fclr : integer := 15;
constant cntl_ibf_datto : integer := 7;
constant cntl_ibf_nobyt : integer := 6;
constant cntl_ibf_dlyw : integer := 5;
constant cntl_ibf_dlyr : integer := 4;
constant cntl_ibf_remw : integer := 3;
constant cntl_ibf_remr : integer := 2;
constant cntl_ibf_locw : integer := 1;
constant cntl_ibf_locr : integer := 0;
subtype stat_ibf_fsize is integer range 15 downto 12;
constant stat_ibf_racc : integer := 6;
constant stat_ibf_cacc : integer := 5;
constant stat_ibf_be1 : integer := 4;
constant stat_ibf_be0 : integer := 3;
constant stat_ibf_rmw : integer := 2;
constant stat_ibf_we : integer := 1;
constant stat_ibf_re : integer := 0;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
datto : slbit; -- cntl: ibus timeout for bad loc data
nobyt : slbit; -- cntl: disallow byte writes to data
dlyw : slbit; -- cntl: enable loc write delay
dlyr : slbit; -- cntl: enable loc read delay
remw : slbit; -- cntl: enable rem write
remr : slbit; -- cntl: enable rem read
locw : slbit; -- cntl: enable loc write
locr : slbit; -- cntl: enable loc read
racc : slbit; -- stat: racc seen
cacc : slbit; -- stat: cacc seen
be1 : slbit; -- stat: be1 seen
be0 : slbit; -- stat: be0 seen
rmw : slbit; -- stat: rmw seen
we : slbit; -- stat: we seen
re : slbit; -- stat: re seen
data : slv16; -- data register
dcnt : slv3; -- delay counter
req_1 : slbit; -- (re or we) of last cycle
rwm_1 : slbit; -- (re or we or rmw) of last cycle
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'0','0','0','0', -- datto,nobyt,dlyw,dlyr
'1','1','0','0', -- remw,remr,locw,locr
'0','0','0','0', -- racc,cacc,be1,be0
'0','0','0', -- rmw,we,re
(others=>'0'), -- data
(others=>'0'), -- dcnt
'0','0' -- req_1,rwm_1
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal FIFO_CE : slbit := '0';
signal FIFO_WE : slbit := '0';
signal FIFO_RESET : slbit := '0';
signal FIFO_EMPTY : slbit := '0';
signal FIFO_FULL : slbit := '0';
signal FIFO_SIZE : slv4 := (others=>'0');
signal FIFO_DO : slv16 := (others=>'0');
begin
FIFO : fifo_simple_dram
generic map (
AWIDTH => 4,
DWIDTH => 16)
port map (
CLK => CLK,
RESET => FIFO_RESET,
CE => FIFO_CE,
WE => FIFO_WE,
DI => IB_MREQ.din,
DO => FIFO_DO,
EMPTY => FIFO_EMPTY,
FULL => FIFO_FULL,
SIZE => FIFO_SIZE
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, RESET, FIFO_DO, FIFO_EMPTY, FIFO_FULL)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibreq : slbit := '0';
variable ibbusy : slbit := '0';
variable iback : slbit := '0';
variable idout : slv16 := (others=>'0');
variable ififo_rst : slbit := '0';
variable ififo_ce : slbit := '0';
variable ififo_we : slbit := '0';
variable dlyok : slbit := '0'; -- fifo/data delay ok
variable dodly : slbit := '0'; -- fifo/data do delay
variable wrok : slbit := '0'; -- fifo/data write ok
variable rdok : slbit := '0'; -- fifo/data read ok
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibbusy := '0';
iback := r.ibsel and ibreq;
ififo_rst := RESET;
ififo_ce := '0';
ififo_we := '0';
dlyok := '0';
if IB_MREQ.racc = '0' then -- loc
dlyok := (r.dlyr and IB_MREQ.re) or (r.dlyw and IB_MREQ.we);
end if;
dodly := '0';
if IB_MREQ.racc = '1' then -- rem
wrok := r.remw;
rdok := r.remr;
else -- loc
wrok := r.locw;
rdok := r.locr;
end if;
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- re,we,rmw edge detectors
n.req_1 := r.ibsel and (ibreq);
n.rwm_1 := r.ibsel and (ibreq or IB_MREQ.rmw);
-- ibus mreq monitor
if r.ibsel = '1' then
if (ibreq or IB_MREQ.rmw) = '1' and -- re or we or rmw
IB_MREQ.addr(2) = '1' then -- and addr = (data or fifo)
if r.rwm_1 = '0' then -- leading edge
n.racc := IB_MREQ.racc;
n.cacc := IB_MREQ.cacc;
n.be1 := IB_MREQ.be1;
n.be0 := IB_MREQ.be0;
n.rmw := IB_MREQ.rmw;
n.we := IB_MREQ.we;
n.re := IB_MREQ.re;
else -- later
n.we := r.we or IB_MREQ.we;
n.re := r.re or IB_MREQ.re;
end if;
end if;
end if;
-- delay counter
if r.ibsel='1' and ibreq='1' and dlyok='1' then -- selected,active,delayed
if r.req_1 = '0' then -- leading edge
n.dcnt := "111";
dodly := '1';
else -- later
if r.dcnt /= "000" then
n.dcnt := slv(unsigned(r.dcnt) - 1);
dodly := '1';
end if;
end if;
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
if IB_MREQ.racc = '1' then -- rem
if IB_MREQ.we = '1' then -- write
ififo_rst := IB_MREQ.din(cntl_ibf_fclr);
n.datto := IB_MREQ.din(cntl_ibf_datto);
n.nobyt := IB_MREQ.din(cntl_ibf_nobyt);
n.dlyw := IB_MREQ.din(cntl_ibf_dlyw);
n.dlyr := IB_MREQ.din(cntl_ibf_dlyr);
n.remw := IB_MREQ.din(cntl_ibf_remw);
n.remr := IB_MREQ.din(cntl_ibf_remr);
n.locw := IB_MREQ.din(cntl_ibf_locw);
n.locr := IB_MREQ.din(cntl_ibf_locr);
end if;
else -- loc
iback := '0'; -- reject loc access to CNTL
end if;
when ibaddr_stat => -- STAT
if IB_MREQ.racc = '0' then -- loc
iback := '0'; -- reject loc access to STAT
end if;
when ibaddr_data => -- DATA
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write ok
if r.nobyt = '1' and -- byte write allowed check
(IB_MREQ.be1='0' or IB_MREQ.be0='0') then
iback := '0'; -- send nak
else -- byte check ok
if dodly = '1' then -- delay active
iback := '0';
ibbusy := '1';
else -- no delay active
if IB_MREQ.be1 = '1' then
n.data(ibf_byte1) := IB_MREQ.din(ibf_byte1);
end if;
if IB_MREQ.be0 = '1' then
n.data(ibf_byte0) := IB_MREQ.din(ibf_byte0);
end if;
end if; -- dodly = '1'
end if; -- byte check
else -- write not ok
iback := '0'; -- send nak
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read enabled
if dodly = '1' then -- delay active
iback := '0';
ibbusy := '1';
end if;
else -- read disabled
if r.datto = '1' then -- data time out enabled
iback := '0';
ibbusy := '1'; -- will cause timeout !
else
iback := '0'; -- send nak
end if;
end if; -- rdok = '0'
end if; -- IB_MREQ.re = '1'
when ibaddr_fifo => -- FIFO
if IB_MREQ.we = '1' then -- write
if wrok = '1' then -- write ok
if dodly = '1' then -- delay active
iback := '0';
ibbusy := '1';
else -- delay not active
if FIFO_FULL = '0' then -- fifo not full
ififo_ce := '1';
ififo_we := '1';
else -- fifo full
iback := '0'; -- send nak
end if; -- FIFO_FULL = '0'
end if; -- dodly = '1'
else -- write not ok
iback := '0'; -- send nak
end if; -- wrok = '1'
end if; -- IB_MREQ.we = '1'
if IB_MREQ.re = '1' then -- read
if rdok = '1' then -- read ok
if dodly = '1' then -- delay active
iback := '0';
ibbusy := '1';
else -- delay not active
if FIFO_EMPTY = '0' then -- fifo not empty
ififo_ce := '1';
else -- fifo empty
iback := '0'; -- send nak
end if; -- FIFO_EMPTY = '0'
end if; -- dodly = '1'
else -- read not ok
iback := '0'; -- send nak
end if; -- rdok = '1'
end if; -- IB_MREQ.re = '1'
when others => null;
end case; --
end if; --r.ibsel = '1'
-- ibus output driver
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_cntl => -- CNTL
idout(cntl_ibf_datto) := r.datto;
idout(cntl_ibf_nobyt) := r.nobyt;
idout(cntl_ibf_dlyw) := r.dlyw;
idout(cntl_ibf_dlyr) := r.dlyr;
idout(cntl_ibf_remw) := r.remw;
idout(cntl_ibf_remr) := r.remr;
idout(cntl_ibf_locw) := r.locw;
idout(cntl_ibf_locr) := r.locr;
when ibaddr_stat => -- STAT
idout(stat_ibf_fsize) := FIFO_SIZE;
idout(stat_ibf_racc) := r.racc;
idout(stat_ibf_cacc) := r.cacc;
idout(stat_ibf_be1) := r.be1;
idout(stat_ibf_be0) := r.be0;
idout(stat_ibf_rmw) := r.rmw;
idout(stat_ibf_we) := r.we;
idout(stat_ibf_re) := r.re;
when ibaddr_data => -- DATA
idout := r.data;
when ibaddr_fifo => -- FIFO
idout := FIFO_DO;
when others => null;
end case;
end if;
N_REGS <= n;
FIFO_RESET <= ififo_rst;
FIFO_CE <= ififo_ce;
FIFO_WE <= ififo_we;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= ibbusy;
end process proc_next;
end syn;

18
rtl/ibus/iblib.vhd
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@ -1,6 +1,6 @@
-- $Id: iblib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: iblib.vhd 1111 2019-02-10 16:13:55Z mueller $
--
-- Copyright 2008-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -16,9 +16,10 @@
-- Description: Definitions for ibus interface and bus entities
--
-- Dependencies: -
-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Tool versions: ise 8.1-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-10 1111 2.2.1 add ibd_ibtst
-- 2017-01-28 846 2.2 add ib_intmap24
-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type
-- 2015-04-24 668 2.1 add ibd_ibmon
@ -165,6 +166,17 @@ component ibd_ibmon is -- ibus dev: ibus monitor
);
end component;
component ibd_ibtst is -- ibus dev(rem): ibus tester
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#170000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
--
-- components for use in test benches (not synthesizable)
--

3
rtl/w11a/pdp11_sys70.vbom
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@ -10,7 +10,8 @@ pdp11_core.vbom
pdp11_cache.vbom
pdp11_mem70.vbom
../ibus/ibd_ibmon.vbom
../ibus/ib_sres_or_3.vbom
../ibus/ibd_ibtst.vbom
../ibus/ib_sres_or_4.vbom
pdp11_dmscnt.vbom
pdp11_dmcmon.vbom
pdp11_dmhbpt.vbom

29
rtl/w11a/pdp11_sys70.vhd
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@ -1,6 +1,6 @@
-- $Id: pdp11_sys70.vhd 1056 2018-10-13 16:01:17Z mueller $
-- $Id: pdp11_sys70.vhd 1112 2019-02-17 11:10:04Z mueller $
--
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@ -20,7 +20,8 @@
-- w11a/pdp11_cache
-- w11a/pdp11_mem70
-- ibus/ibd_ibmon
-- ibus/ib_sres_or_3
-- ibus/ibd_ibtst
-- ibus/ib_sres_or_4
-- w11a/pdp11_dmscnt
-- w11a/pdp11_dmcmon
-- w11a/pdp11_dmhpbt
@ -31,10 +32,11 @@
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2018.2; ghdl 0.33-0.34
-- Tool versions: ise 14.7; viv 2014.4-2018.3; ghdl 0.33-0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-16 1112 1.3.1 add ibd_ibtst
-- 2018-10-13 1055 1.3 drop ITIMER,DM_STAT_DP out ports, use DM_STAT_EXP
-- add PERFEXT in port
-- 2018-10-06 1053 1.2.3 drop DM_STAT_SY; add DM_STAT_CA; use _SE.pcload
@ -132,6 +134,7 @@ architecture syn of pdp11_sys70 is
signal IB_SRES_M : ib_sres_type := ib_sres_init;
signal IB_SRES_MEM70 : ib_sres_type := ib_sres_init;
signal IB_SRES_IBMON : ib_sres_type := ib_sres_init;
signal IB_SRES_IBTST : ib_sres_type := ib_sres_init;
constant rbaddr_ibus0 : slv16 := x"4000"; -- 4000/1000: 0100 xxxx xxxx xxxx
constant rbaddr_core0 : slv16 := x"0000"; -- 0000/0020: 0000 0000 000x xxxx
@ -233,11 +236,27 @@ begin
);
end generate IBMON;
IB_SRES_OR : ib_sres_or_3
IBTST : if sys_conf_ibtst generate
signal RESET_IBTST : slbit := '0';
begin
RESET_IBTST <= RESET or GRESET_L or BRESET_L;
I0 : ibd_ibtst
generic map (
IB_ADDR => slv(to_unsigned(8#170000#,16)))
port map (
CLK => CLK,
RESET => RESET_IBTST,
IB_MREQ => IB_MREQ_M,
IB_SRES => IB_SRES_IBTST
);
end generate IBTST;
IB_SRES_OR : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_MEM70,
IB_SRES_2 => IB_SRES,
IB_SRES_3 => IB_SRES_IBMON,
IB_SRES_4 => IB_SRES_IBTST,
IB_SRES_OR => IB_SRES_M
);

21
tools/src/librw11/Rw11Cpu.cpp
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@ -1,6 +1,6 @@
// $Id: Rw11Cpu.cpp 1091 2018-12-23 12:38:29Z mueller $
// $Id: Rw11Cpu.cpp 1112 2019-02-17 11:10:04Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-02-16 1112 1.2.16 add ibmon setup and HasIbtst()
// 2018-12-23 1091 1.2.19 AddWbibr(): add move version
// 2018-12-19 1090 1.2.18 use RosPrintf(bool)
// 2018-12-17 1085 1.2.17 use std::mutex,condition_variable instead of boost
@ -195,6 +196,7 @@ Rw11Cpu::Rw11Cpu(const std::string& type)
fHasCmon(false),
fHasHbpt(0),
fHasIbmon(false),
fHasIbtst(false),
fHasKw11l(false),
fHasKw11p(false),
fHasIist(false),
@ -891,6 +893,7 @@ void Rw11Cpu::Dump(std::ostream& os, int ind, const char* text,
os << bl << " fHasCmon: " << RosPrintf(fHasCmon) << endl;
os << bl << " fHasHbpt: " << fHasHbpt << endl;
os << bl << " fHasIbmon: " << RosPrintf(fHasIbmon) << endl;
os << bl << " fHasIbtst: " << RosPrintf(fHasIbtst) << endl;
os << bl << " fHasKw11l: " << RosPrintf(fHasKw11l) << endl;
os << bl << " fHasKw11p: " << RosPrintf(fHasKw11p) << endl;
os << bl << " fHasIist: " << RosPrintf(fHasIist) << endl;
@ -983,7 +986,7 @@ void Rw11Cpu::SetupStd()
void Rw11Cpu::SetupOpt()
{
// probe optional cpu components: dmscnt, dmcmon, dmhbpt and ibmon
// probe optional cpu components: dmscnt, dmcmon, dmhbpt and ibmon, ibtst
RlinkCommandList clist;
int isc = clist.AddRreg(Base()+kSCBASE+kSCCNTL);
@ -997,9 +1000,13 @@ void Rw11Cpu::SetupOpt()
ihb[i] = clist.AddRreg(Base()+kHBBASE+i*kHBSIZE+kHBCNTL);
clist.SetLastExpectStatus(0,0);
}
int iim = AddRibr(clist, kIMBASE+kIMCNTL); // ibmon probe rem (no loc resp)
clist.SetLastExpectStatus(0,0);
int iit = AddRibr(clist, kITBASE+kITCNTL); // ibtst probe rem (loc disabled)
clist.SetLastExpectStatus(0,0);
int ipc = clist.AddRreg(Base()+kPCBASE+kPCCNTL);
clist.SetLastExpectStatus(0,0); // disable stat check
@ -1071,6 +1078,14 @@ void Rw11Cpu::SetupOpt()
AllIAddrMapInsert("im.data", kIMBASE + kIMDATA);
}
fHasIbtst = (clist[iit].Status() & statmsk) == 0;
if (fHasIbtst) {
AllIAddrMapInsert("it.cntl", kITBASE + kITCNTL);
AllIAddrMapInsert("it.stat", kITBASE + kITSTAT);
AllIAddrMapInsert("it.data", kITBASE + kITDATA);
AllIAddrMapInsert("it.fifo", kITBASE + kITFIFO);
}
fHasKw11l = (clist[ikwl].Status() & statmsk) == 0;
if (fHasKw11l) {
AllIAddrMapInsert("kwl.csr", kKWLBASE);

15
tools/src/librw11/Rw11Cpu.hpp
View File

@ -1,6 +1,6 @@
// $Id: Rw11Cpu.hpp 1091 2018-12-23 12:38:29Z mueller $
// $Id: Rw11Cpu.hpp 1112 2019-02-17 11:10:04Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-02-15 1112 1.2.16 add HasIbtst()
// 2018-12-23 1091 1.2.15 AddWbibr(): add move version
// 2018-12-17 1085 1.2.14 use std::mutex,condition_variable instead of boost
// 2018-12-16 1084 1.2.13 use =delete for noncopyable instead of boost
@ -92,6 +93,7 @@ namespace Retro {
bool HasCmon() const;
uint16_t HasHbpt() const;
bool HasIbmon() const;
bool HasIbtst() const;
bool HasKw11l() const;
bool HasKw11p() const;
bool HasIist() const;
@ -259,13 +261,19 @@ namespace Retro {
static const uint16_t kPCSTAT = 0x0001; //!< PC.STAT reg offset
static const uint16_t kPCDATA = 0x0002; //!< PC.DATA reg offset
static const uint16_t kIMBASE = 0160000; //!< Ibmon ibus address
static const uint16_t kIMBASE = 0160000; //!< Ibmon ibus address
static const uint16_t kIMCNTL = 0x0000; //!< IM.CNTL reg offset
static const uint16_t kIMSTAT = 0x0002; //!< IM.STAT reg offset
static const uint16_t kIMHILIM = 0x0004; //!< IM.HILIM reg offset
static const uint16_t kIMLOLIM = 0x0006; //!< IM.LOLIM reg offset
static const uint16_t kIMADDR = 0x0008; //!< IM.ADDR reg offset
static const uint16_t kIMDATA = 0x000a; //!< IM.DATA reg offset
static const uint16_t kITBASE = 0170000; //!< Ibtst ibus address
static const uint16_t kITCNTL = 0x0000; //!< IT.CNTL reg offset
static const uint16_t kITSTAT = 0x0002; //!< IT.STAT reg offset
static const uint16_t kITDATA = 0x0004; //!< IT.DATA reg offset
static const uint16_t kITFIFO = 0x0006; //!< IT.FIFO reg offset
// defs for optional w11 aux components
static const uint16_t kKWLBASE = 0177546; //!< KW11-L ibus address
@ -295,6 +303,7 @@ namespace Retro {
bool fHasCmon; //!< has dmcmon (cpu monitor)
uint16_t fHasHbpt; //!< has dmhbpt (hardware breakpoint)
bool fHasIbmon; //!< has ibmon (ibus monitor)
bool fHasIbtst; //!< has ibtst (ibus tester)
bool fHasKw11l; //!< has kw11-l (line clock)
bool fHasKw11p; //!< has kw11-p (prog clock)
bool fHasIist; //!< has iist (smp comm)

13
tools/src/librw11/Rw11Cpu.ipp
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@ -1,6 +1,6 @@
// $Id: Rw11Cpu.ipp 1066 2018-11-10 11:21:53Z mueller $
// $Id: Rw11Cpu.ipp 1112 2019-02-17 11:10:04Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-02-15 1112 1.2.4 add HasIbtst()
// 2018-09-23 1050 1.2.3 add HasPcnt()
// 2017-02-17 851 1.2.2 probe/setup auxilliary devices: kw11l,kw11p,iist
// 2015-07-12 700 1.2.1 use ..CpuAct instead ..CpuGo (new active based lam)
@ -137,6 +138,14 @@ inline bool Rw11Cpu::HasIbmon() const
//------------------------------------------+-----------------------------------
//! FIXME_docs
inline bool Rw11Cpu::HasIbtst() const
{
return fHasIbtst;
}
//------------------------------------------+-----------------------------------
//! FIXME_docs
inline bool Rw11Cpu::HasKw11l() const
{
return fHasKw11l;

10
tools/src/librwxxtpp/RtclRw11Cpu.cpp
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@ -1,6 +1,6 @@
// $Id: RtclRw11Cpu.cpp 1091 2018-12-23 12:38:29Z mueller $
// $Id: RtclRw11Cpu.cpp 1112 2019-02-17 11:10:04Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
@ -13,6 +13,8 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-02-15 1112 1.2.25 add HasIbtst() getter
// add return type for lambdas with const type&
// 2018-12-23 1091 1.2.24 use AddWbibr(move),AddWblk(move)
// 2018-12-18 1089 1.2.23 use c++ style casts
// 2018-12-17 1085 1.2.22 use std::lock_guard instead of boost
@ -1480,7 +1482,8 @@ int RtclRw11Cpu::M_default(RtclArgs& args)
void RtclRw11Cpu::SetupGetSet()
{
Rw11Cpu* pobj = &Obj();
fGets.Add<const string&>("type", [pobj](){ return pobj->Type(); });
fGets.Add<const string&>("type", [pobj]() -> const string&
{ return pobj->Type(); });
fGets.Add<size_t> ("index", [pobj](){ return pobj->Index(); });
fGets.Add<uint16_t> ("base", [pobj](){ return pobj->Base(); });
fGets.Add<uint16_t> ("ibase", [pobj](){ return pobj->IBase(); });
@ -1489,6 +1492,7 @@ void RtclRw11Cpu::SetupGetSet()
fGets.Add<bool> ("hascmon", [pobj](){ return pobj->HasCmon(); });
fGets.Add<uint16_t> ("hashbpt", [pobj](){ return pobj->HasHbpt(); });
fGets.Add<bool> ("hasibmon", [pobj](){ return pobj->HasIbmon(); });
fGets.Add<bool> ("hasibtst", [pobj](){ return pobj->HasIbtst(); });
fGets.Add<bool> ("haskw11l", [pobj](){ return pobj->HasKw11l(); });
fGets.Add<bool> ("haskw11p", [pobj](){ return pobj->HasKw11p(); });
fGets.Add<bool> ("hasiist", [pobj](){ return pobj->HasIist(); });

5
tools/tbench/cpu_all.dat
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@ -1,8 +1,11 @@
# $Id: cpu_all.dat 1050 2018-09-23 15:46:42Z mueller $
# $Id: cpu_all.dat 1112 2019-02-17 11:10:04Z mueller $
#
## steering file for all cpu tests
#
@cp/cp_all.dat
#
@w11a_ibtst/w11a_ibtst_all.dat
#
@w11a/w11a_all.dat
#
@w11a_cmon/w11a_cmon_all.dat

35
tools/tbench/w11a/test_w11a_sdreg.tcl Normal file
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@ -0,0 +1,35 @@
# $Id: test_ibtst_regs.tcl 1112 2019-02-17 11:10:04Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-02-17 1113 1.0 Initial version
#
# Test cntl register response
#
# Note: display/swich register is a processor register
# --> use ribr/wibr for rem accesses
# --> use rm /wm for loc accesses
# ----------------------------------------------------------------------------
rlc log "test_w11a_sdreg: test switch and display register access -------------"
# test write/read aaaa/5555 dead/beef 0000/0000
# for display loc write --> rem read
# for switch rem write --> loc read
$cpu cp \
-wa [cpu0 imap sdreg] \
-wm 0xaaaa \
-wibr sdreg 0x5555 \
-ribr sdreg -edata 0xaaaa \
-rm -edata 0x5555 \
-wm 0xdead \
-wibr sdreg 0xbeef \
-ribr sdreg -edata 0xdead \
-rm -edata 0xbeef \
-wm 0x0000 \
-wibr sdreg 0x0000 \
-ribr sdreg -edata 0x0000 \
-rm -edata 0x0000

2
tools/tbench/w11a/w11a_all.dat
View File

@ -2,6 +2,8 @@
#
## steering file for all w11a tests
#
test_w11a_sdreg.tcl
#
test_w11a_mem70.tcl
#
test_w11a_srcr_word_flow.tcl

94
tools/tbench/w11a_ibtst/test_ibtst_data.tcl Normal file
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@ -0,0 +1,94 @@
# $Id: test_ibtst_data.tcl 1112 2019-02-17 11:10:04Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-02-16 1112 1.0 Initial version
#
# Test data register response
#
# Note: ibtst is more a processor extension than an ibus device
# ctrl/stat are only rem accessible (acts like bridged rbus device)
# data/fifo can be rem/loc enabled
# --> use rreg/wreg for cntl/stat accesses
# --> use ribr/wibr for data/fifo rem accesses
# --> use rm /wm for data/fifo loc accesses
# ----------------------------------------------------------------------------
rlc log "test_ibtst_data: test data register response -------------------------"
if {[$cpu get hasibtst] == 0} {
rlc log " test_ibtst_data-W: no ibtest unit found, test aborted"
return
}
package require ibd_ibtst
rlc log " A1: data loc/rem access ----------------------------"
# test loc/rem write: n/n; y/n; n/y; y/y
# test loc/rem read: n/n; y/n; n/y; y/y
$cpu cp \
-wa [cpu0 imap it.data] \
-wreg it.cntl [regbld ibd_ibtst::CNTL ] \
-wm 0xdead -estaterr \
-wibr it.data 0xdead -estaterr \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw ] \
-wm 0xdead \
-wibr it.data 0xdead -estaterr \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw ] \
-wm 0xdead -estaterr \
-wibr it.data 0xdead \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw locw ] \
-wm 0xdead \
-wibr it.data 0xdead \
-wreg it.cntl [regbld ibd_ibtst::CNTL ] \
-rm -estaterr \
-ribr it.data -estaterr \
-wreg it.cntl [regbld ibd_ibtst::CNTL locr ] \
-rm -edata 0xdead \
-ribr it.data -estaterr \
-wreg it.cntl [regbld ibd_ibtst::CNTL remr ] \
-rm -estaterr \
-ribr it.data -edata 0xdead \
-wreg it.cntl [regbld ibd_ibtst::CNTL remr locr ] \
-rm -edata 0xdead \
-ribr it.data -edata 0xdead
rlc log " A2: data loc nak and timeout -----------------------"
# test datto; should look like nak
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL datto ] \
-wm 0xdead -estaterr \
-rm -estaterr
rlc log " A3: data byte access (loc only) --------------------"
# test loc byte write; test nobyt
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw locr ] \
-wm 0xffff \
-wmembe 0x01 \
-wm 0xee11 \
-rm -edata 0xff11 \
-wmembe 0x02 \
-wm 0x22dd \
-rm -edata 0x2211 \
-wmembe 0x03 \
-wm 0x4433 \
-rm -edata 0x4433 \
-wreg it.cntl [regbld ibd_ibtst::CNTL nobyt locw locr ] \
-wmembe 0x01 \
-wm 0xdead -estaterr \
-wmembe 0x02 \
-wm 0xdead -estaterr \
-wmembe 0x03 \
-wm 0xbeef \
-rm -edata 0xbeef
rlc log " A4: reset data -------------------------------------"
# check that data is cleared
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw remr ] \
-wibr it.data 0xdead \
-breset \
-ribr it.data -edata 0x0000

134
tools/tbench/w11a_ibtst/test_ibtst_fifo.tcl Normal file
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@ -0,0 +1,134 @@
# $Id: test_ibtst_fifo.tcl 1112 2019-02-17 11:10:04Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-02-16 1112 1.0 Initial version
#
# Test fifo register response
#
# Note: ibtst is more a processor extension than an ibus device
# ctrl/stat are only rem accessible (acts like bridged rbus device)
# data/fifo can be rem/loc enabled
# --> use rreg/wreg for cntl/stat accesses
# --> use ribr/wibr for data/fifo rem accesses
# --> use rm /wm for data/fifo loc accesses
# ----------------------------------------------------------------------------
rlc log "test_ibtst_fifo: test fifo register response -------------------------"
if {[$cpu get hasibtst] == 0} {
rlc log " test_ibtst_fifo-W: no ibtest unit found, test aborted"
return
}
package require ibd_ibtst
rlc log " A1: fifo loc/rem access ----------------------------"
# test off->off; loc->loc; loc->rem; rem->loc; rem->rem
$cpu cp \
-wa [cpu0 imap it.fifo] \
-wreg it.cntl [regbld ibd_ibtst::CNTL fclr ] \
-wm 0xdead -estaterr \
-wibr it.fifo 0xdead -estaterr \
-rm -estaterr \
-ribr it.fifo -estaterr \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw locr ] \
-wm 0x1111 \
-wibr it.fifo 0xdead -estaterr \
-rm -edata 0x1111 \
-ribr it.fifo -estaterr \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw remr ] \
-wm 0x2222 \
-wibr it.fifo 0xdead -estaterr \
-rm -estaterr \
-ribr it.fifo -edata 0x2222 \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw locr ] \
-wm 0xdead -estaterr \
-wibr it.fifo 0x3333 \
-rm -edata 0x3333 \
-ribr it.fifo -estaterr \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw remr ] \
-wm 0xdead -estaterr \
-wibr it.fifo 0x4444 \
-rm -estaterr \
-ribr it.fifo -edata 0x4444
rlc log " A2: fifo scalar (loc->rem); fifo clr ---------------"
# write 2; fclr; write 2; read 3
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw remr ] \
-wm 0x1011 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 1} cacc be1 be0 we ] \
-wm 0x1012 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 2} cacc be1 be0 we ] \
-wreg it.cntl [regbld ibd_ibtst::CNTL fclr locw remr ] \
-wm 0x2011 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 1} cacc be1 be0 we ] \
-wm 0x2012 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 2} cacc be1 be0 we ] \
-ribr it.fifo -edata 0x2011 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 1} racc cacc be1 be0 re]\
-ribr it.fifo -edata 0x2012 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 0} racc cacc be1 be0 re]\
-ribr it.fifo -estaterr \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 0} racc cacc be1 be0 re]
rlc log " A3: fifo scalar (rem->loc) -------------------------"
# write 2; read 3
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw locr ] \
-wibr it.fifo 0x3011 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 1} racc cacc be1 be0 we]\
-wibr it.fifo 0x3012 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 2} racc cacc be1 be0 we]\
-rm -edata 0x3011 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 1} cacc be1 be0 re]\
-rm -edata 0x3012 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 0} cacc be1 be0 re]\
-rm -estaterr \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 0} cacc be1 be0 re]
rlc log " A4: fifo block read (loc->rem, rblk, test abort) ---"
# write 2; fclr; write 2; read 3 (get 2)
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw remr ] \
-wm 0x4011 \
-wm 0x4012 \
-rbibr it.fifo 3 -edata {0x4011 0x4012} -edone 2 -estaterr
rlc log " A5: fifo block write (rem->loc, wblk, test abort) --"
# write 8; write 8; read 16 (get 15)
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw locr ] \
-wbibr it.fifo {0x5000 0x5011 0x5022 0x5033 0x5044 0x5055 0x5066 0x5077} \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 8} racc cacc be1 be0 we]\
-wbibr it.fifo {0x5088 0x5099 0x50aa 0x50bb 0x50cc 0x50dd 0x50ee 0x50ff} \
-edone 7 -estaterr \
-ribr it.stat -edata [regbld ibd_ibtst::STAT {fsize 15} racc cacc be1 be0 we]\
-rm -edata 0x5000 \
-rm -edata 0x5011 \
-rm -edata 0x5022 \
-rm -edata 0x5033 \
-rm -edata 0x5044 \
-rm -edata 0x5055 \
-rm -edata 0x5066 \
-rm -edata 0x5077 \
-rm -edata 0x5088 \
-rm -edata 0x5099 \
-rm -edata 0x50aa \
-rm -edata 0x50bb \
-rm -edata 0x50cc \
-rm -edata 0x50dd \
-rm -edata 0x50ee \
-rm -estaterr
rlc log " A6: reset fifo (and stat) --------------------------"
# check that fifo is cleared
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL fclr remw remr ] \
-wibr it.fifo 0xdead \
-breset \
-ribr it.stat -edata [regbld ibd_ibtst::STAT] \
-ribr it.fifo -estaterr

66
tools/tbench/w11a_ibtst/test_ibtst_regs.tcl Normal file
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@ -0,0 +1,66 @@
# $Id: test_ibtst_regs.tcl 1112 2019-02-17 11:10:04Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-02-16 1112 1.0 Initial version
#
# Test cntl register response
#
# Note: ibtst is more a processor extension than an ibus device
# ctrl/stat are only rem accessible (acts like bridged rbus device)
# data/fifo can be rem/loc enabled
# --> use rreg/wreg for cntl/stat accesses
# --> use ribr/wibr for data/fifo rem accesses
# --> use rm /wm for data/fifo loc accesses
# ----------------------------------------------------------------------------
rlc log "test_ibtst_regs: test cntl/stat register access ----------------------"
if {[$cpu get hasibtst] == 0} {
rlc log " test_ibtst_regs-W: no ibtest unit found, test aborted"
return
}
package require ibd_ibtst
rlc log " A1: write/read cntl---------------------------------"
# test cntl option flags
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL locr] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL locr] \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL locw] \
-wreg it.cntl [regbld ibd_ibtst::CNTL remr] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL remr] \
-wreg it.cntl [regbld ibd_ibtst::CNTL remw] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL remw] \
-wreg it.cntl [regbld ibd_ibtst::CNTL dlyr] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL dlyr] \
-wreg it.cntl [regbld ibd_ibtst::CNTL dlyw] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL dlyw] \
-wreg it.cntl [regbld ibd_ibtst::CNTL nobyt] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL nobyt] \
-wreg it.cntl [regbld ibd_ibtst::CNTL datto] \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL datto] \
-wreg it.cntl 0x0000 \
-rreg it.cntl -edata -0x0000
rlc log " A2: reset cntl -------------------------------------"
# check that only data/fifo rem access enable after reset
$cpu cp \
-wreg it.cntl 0xffff \
-breset \
-rreg it.cntl -edata [regbld ibd_ibtst::CNTL remw remr] \
-rreg it.stat -edata 0x0000
rlc log " A3: cntl,stat only rem accessible ------------------"
$cpu cp \
-rreg it.stat -edata 0x0000 \
-wa [cpu0 imap it.cntl] \
-wm 0xdead -estaterr \
-rm -estaterr \
-wa [cpu0 imap it.stat] \
-wm 0xdead -estaterr \
-rm -estaterr

129
tools/tbench/w11a_ibtst/test_ibtst_stat.tcl Normal file
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@ -0,0 +1,129 @@
# $Id: test_ibtst_stat.tcl 1112 2019-02-17 11:10:04Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-02-16 1112 1.0 Initial version
#
# Test stat register response
#
# Note: ibtst is more a processor extension than an ibus device
# ctrl/stat are only rem accessible (acts like bridged rbus device)
# data/fifo can be rem/loc enabled
# --> use rreg/wreg for cntl/stat accesses
# --> use ribr/wibr for data/fifo rem accesses
# --> use rm /wm for data/fifo loc accesses
# ----------------------------------------------------------------------------
rlc log "test_ibtst_stat: test stat register response -------------------------"
if {[$cpu get hasibtst] == 0} {
rlc log " test_ibtst_data-W: no ibtest unit found, test aborted"
return
}
package require ibd_ibtst
rlc log " A1: data rem access --------------------------------"
$cpu cp \
-wa [cpu0 imap it.data] \
-wreg it.cntl [regbld ibd_ibtst::CNTL fclr remw remr ] \
-wibr it.data 0x1234 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT racc cacc be1 be0 we ] \
-ribr it.data -edata 0x1234 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT racc cacc be1 be0 re ]
rlc log " A2: data loc access --------------------------------"
$cpu cp \
-wreg it.cntl [regbld ibd_ibtst::CNTL locw locr ] \
-wm 0xffff \
-ribr it.stat -edata [regbld ibd_ibtst::STAT cacc be1 be0 we ] \
-wmembe 0x01 \
-wm 0xee11 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT cacc be0 we ] \
-rm -edata 0xff11 \
-wmembe 0x02 \
-wm 0x22dd \
-ribr it.stat -edata [regbld ibd_ibtst::STAT cacc be1 we ] \
-rm -edata 0x2211 \
-ribr it.stat -edata [regbld ibd_ibtst::STAT cacc be1 be0 re ]
rlc log " A3: data cpu write -> rem read (busy=0) ------------"
# load test code
$cpu ldasm -lst lst -sym sym {
. = 002000 ; code base
start: mov #100200,(r0) ; wr 11 0x8080
movb #377,(r0) ; wr 01 0x00ff -> 0x80ff
movb #377,(r1) ; wr 10 0x1100 -> 0xffff
inc (r0) ; rmw 11 0xffff -> 0x0000
incb (r0) ; rmw 01 0x0000 -> 0x0001
incb (r1) ; rmw 10 0x0001 -> 0x0101
mov (r0),r2 ; rd 11 0x0101
}
# setup code and ibtst
$cpu cp \
-wr0 [cpu0 imap it.data] \
-wr1 [expr {[cpu0 imap it.data] + 1}] \
-wr2 0xdead \
-wpc 02000 \
-wa [cpu0 imap it.data] \
-wreg it.cntl [regbld ibd_ibtst::CNTL fclr remr locw locr ]
# step through code and check
$cpu cp \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be1 be0 we ] \
-ribr it.data -edata 0x8080 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be0 we ] \
-ribr it.data -edata 0x80ff \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be1 we ] \
-ribr it.data -edata 0xffff \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT rmw be1 be0 we re ] \
-ribr it.data -edata 0x0000 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT rmw be0 we re ] \
-ribr it.data -edata 0x0001 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT rmw be1 we re ] \
-ribr it.data -edata 0x0101 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be1 be0 re ] \
-rr2 -edata 0x0101
rlc log " A4: data cpu write -> rem read (busy=8) ------------"
# setup for run with response delay enabled
$cpu cp \
-wr2 0xdead \
-wpc 02000 \
-wreg it.cntl [regbld ibd_ibtst::CNTL fclr dlyw dlyr remr locw locr ]
# step through code and check (same sequence as above)
$cpu cp \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be1 be0 we ] \
-ribr it.data -edata 0x8080 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be0 we ] \
-ribr it.data -edata 0x80ff \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be1 we ] \
-ribr it.data -edata 0xffff \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT rmw be1 be0 we re ] \
-ribr it.data -edata 0x0000 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT rmw be0 we re ] \
-ribr it.data -edata 0x0001 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT rmw be1 we re ] \
-ribr it.data -edata 0x0101 \
-step \
-ribr it.stat -edata [regbld ibd_ibtst::STAT be1 be0 re ] \
-rr2 -edata 0x0101

9
tools/tbench/w11a_ibtst/w11a_ibtst_all.dat Normal file
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@ -0,0 +1,9 @@
# $Id: w11a_ibtst_all.dat 1112 2019-02-17 11:10:04Z mueller $
#
## steering file for all w11a_ibtst tests
#
test_ibtst_regs.tcl
test_ibtst_data.tcl
test_ibtst_stat.tcl
test_ibtst_fifo.tcl
#

38
tools/tcl/ibd_ibtst/util.tcl Normal file
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@ -0,0 +1,38 @@
# $Id: util.tcl 1112 2019-02-17 11:10:04Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 3, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2019-02-16 1112 1.0 Initial version
#
package provide ibd_ibtst 1.0
package require rlink
package require rw11util
package require rw11
namespace eval ibd_ibtst {
#
# setup register descriptions for ibd_ibtst --------------------------------
#
regdsc CNTL {fclr 15} {datto 7} {nobyt 6} {dlyw 5} {dlyr 4} \
{remw 3} {remr 2} {locw 1} {locr 0}
regdsc STAT {fsize 15 4} {racc 6} {cacc 5} \
{be1 4} {be0 3} {rmw 2} {we 1} {re 0}
rw11util::regmap_add ibd_ibtst it.cntl {r? CNTL}
rw11util::regmap_add ibd_ibtst it.stat {r? STAT}
}

21
tools/tcl/setup_packages
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@ -1,5 +1,5 @@
#! /usr/bin/env tclshcpp
# $Id: setup_packages 1093 2018-12-25 19:52:53Z mueller $
# $Id: setup_packages 1111 2019-02-10 16:13:55Z mueller $
#
# pkg_mkIndex uses tclLog to write, which by default writes to stderr
# this is 'make -s' unfriendly, so redefined tclLog to use plain puts
@ -26,15 +26,16 @@ pkg_mkIndex -verbose rbsysmon *.tcl
pkg_mkIndex -verbose rw11 *.tcl
pkg_mkIndex -verbose rw11util *.tcl
#
pkg_mkIndex -verbose ibd_deuna *.tcl
pkg_mkIndex -verbose ibd_dl11 *.tcl
pkg_mkIndex -verbose ibd_ibmon *.tcl
pkg_mkIndex -verbose ibd_lp11 *.tcl
pkg_mkIndex -verbose ibd_pc11 *.tcl
pkg_mkIndex -verbose ibd_rhrp *.tcl
pkg_mkIndex -verbose ibd_rk11 *.tcl
pkg_mkIndex -verbose ibd_rl11 *.tcl
pkg_mkIndex -verbose ibd_tm11 *.tcl
pkg_mkIndex -verbose ibd_deuna *.tcl
pkg_mkIndex -verbose ibd_dl11 *.tcl
pkg_mkIndex -verbose ibd_ibmon *.tcl
pkg_mkIndex -verbose ibd_ibtst *.tcl
pkg_mkIndex -verbose ibd_lp11 *.tcl
pkg_mkIndex -verbose ibd_pc11 *.tcl
pkg_mkIndex -verbose ibd_rhrp *.tcl
pkg_mkIndex -verbose ibd_rk11 *.tcl
pkg_mkIndex -verbose ibd_rl11 *.tcl
pkg_mkIndex -verbose ibd_tm11 *.tcl
#
pkg_mkIndex -verbose tst_mig *.tcl
pkg_mkIndex -verbose tst_rlink *.tcl