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https://github.com/wfjm/w11.git
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Some minor updates
- rtl/vlib/rlink/tbcore/rlink_cext_dpi.c: add function prototypes - rtl/sys_gen/tst_rlink/cmoda7/tb: add missing ssim vbom - tools/bin - ti_w11: update --help text, add -ar,-n4d,-bn4d - tmuconv: add DEUNA defs
This commit is contained in:
wfjm
@@ -70,7 +70,7 @@ which is
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### License
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This project is released under the
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[GPL V3 license](https://www.gnu.org/licenses/gpl-3.0.html),
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all files contain a [SPDX](https://spdx.org/)-style disclaimer:
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all files contain an [SPDX](https://spdx.org/)-style disclaimer:
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SPDX-License-Identifier: GPL-3.0-or-later
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@@ -38,6 +38,8 @@ The full set of tests is only run for tagged releases.
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- **/tbrun.yml: since nexys4 not longer available switch to nexys4d
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- tools/bin
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- njobihtm: add -n and -h options
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- ti_w11: update --help text, add -ar,-n4d,-bn4d
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- tmuconv: add DEUNA defs
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- tools/dox
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- w11_(cpp|vhd_all).Doxyfile: for Doxygen V1.9.4
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- w11_tcl.Doxyfile: removed, Tcl support removed in Doxygen V1.8.18
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@@ -187,13 +187,6 @@ simulations currently fail due to startup and initialization problems.
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Cause is MMCM/PLL startup, which is not properly reflected in the test
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bench. Will be resolved in an upcoming release.
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### V0.73-1 {[issue #9](https://github.com/wfjm/w11/issues/9)} -- Vivado xelab sometimes extremely slow
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as of Vivado 2016.2 `xelab` shows sometimes extremely long build times,
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especially for generated post-synthesis VHDL models. But also building a
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behavioral simulation for a w11a design can take 25 min. Even though
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post-synthesis or post-routing models are now generated in Verilog working
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with `xsim` is cumbersome and time consuming.
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### V0.65-2 {[issue #7](https://github.com/wfjm/w11/issues/7)} -- Some exotic RH70/RP/RM features not implemented
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some exotic RH70/RP/RM features and conditions not implemented yet
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- last block transfered flag (in DS)
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@@ -382,6 +375,19 @@ still deconfigured for Vivado designs, but this has much less practical impact.
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## Closed issues
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### V0.73-1 {[issue #9](https://github.com/wfjm/w11/issues/9)} -- Vivado xelab sometimes extremely slow
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#### Original Issue
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as of Vivado 2016.2 `xelab` shows sometimes extremely long build times,
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especially for generated post-synthesis VHDL models. But also building a
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behavioral simulation for a w11a design can take 25 min. Even though
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post-synthesis or post-routing models are now generated in Verilog working
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with `xsim` is cumbersome and time consuming.
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#### Reason for closure on 2022-07-05
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Re-checked with Vivado 2022.1.
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Building models with `xelab` is now quite fast.
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The issue disappeared somewhere between Vivado 2016.3 and 2022.1.
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### V0.76-2 {[issue #17](https://github.com/wfjm/w11/issues/17)} -- Help wanted: Testing with Arty S7 appreciated
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#### Original Issue
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The w11a design for Arty S7 (50 die size), see rtl/sys_gen/w11a/artys7,
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@@ -394,7 +400,7 @@ documentation of your board to avoid potential damage.
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Looking forward to receive test reports.
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#### Reason for closure
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#### Reason for closure on 2020-04-20
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Apparently nobody invested into an Arty S7.
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The sys_w11a_as7 will be marked untested, removed from the default build
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and test flows, but kept in the repository.
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@@ -0,0 +1,8 @@
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# configure for _*sim case
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# Note: this tb uses sys_tst_rlink_c7.vbom in local directory
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# (not in .. as usual) to allow a tb specific configure !!!
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# configure
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cmoda7_aif = sys_tst_rlink_c7_ssim.vhd
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# design
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tb_tst_rlink_c7.vbom
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@top:tb_tst_rlink_c7
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@@ -1,9 +1,10 @@
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/* $Id: rlink_cext_dpi.c 1190 2019-07-13 17:05:39Z mueller $
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/* $Id: rlink_cext_dpi.c 1247 2022-07-06 07:04:33Z mueller $
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* SPDX-License-Identifier: GPL-3.0-or-later
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* Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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* Copyright 2016-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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*
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* Revision History:
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* Date Rev Vers Comment
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* 2022-07-05 1247 1.0.1 add function declarations to avoid xelab warnings
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* 2016-02-07 729 1.0 Initial version
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*/
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@@ -11,6 +12,9 @@
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/* simple forwarders to call the old VHPI interface from DPI */
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int rlink_cext_getbyte(int clk);
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int rlink_cext_putbyte(int dat);
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DPI_DLLESPEC
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int rlink_cext_getbyte_dpi(int clk)
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{
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@@ -1,10 +1,11 @@
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#!/usr/bin/perl -w
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# $Id: ti_w11 1172 2019-06-29 07:27:24Z mueller $
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# $Id: ti_w11 1248 2022-07-07 06:25:50Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2022-07-06 1248 1.4.5 update --help text, add -ar,-n4d,-bn4d
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# 2019-04-19 1133 1.4.4 for -e use .end start address when available
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# 2019-01-04 1103 1.4.3 add -ar,-n4d (ddr versions)
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# 2017-06-25 916 1.4.2 add -c7 (cmoda7 support)
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@@ -368,10 +369,13 @@ sub print_usage {
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print "usage: ti_w11 <setup options> <ti_rri opts and cmds>...\n";
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print " setup options for ghdl simulation runs:\n";
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print " -c7 start tb_w11a_c7 simulation (default: -fx)\n";
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print " -ar start tb_w11a_arty simulation (default: -fx)\n";
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print " -bar start tb_w11a_br_arty simulation (default: -fx)\n";
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print " -n4d start tb_w11a_n4d simulation (default: -fx)\n";
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print " -bn4d start tb_w11a_br_n4d simulation (default: -fx)\n";
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print " -b3 start tb_w11a_b3 simulation (default: -fx)\n";
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print " -n4 start tb_w11a_n4 simulation\n";
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print " -bn4 start tb_w11a_br_n4 simulation\n";
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print " -bar start tb_w11a_br_arty simulation (default: -fx)\n";
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print " -n3 start tb_w11a_n3 simulation (default: -fc)\n";
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print " -n2 start tb_w11a_n2 simulation (default: -fc)\n";
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print " -s3 start tb_w11a_s3 simulation (default: -f2)\n";
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@@ -400,6 +404,6 @@ sub print_usage {
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print " file type '.mac': on the fly compile with asm-11\n";
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print " any other file type: assume lda format\n";
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print "\n";
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print " either one of -s3,-n2,-n3,-b3,-n4,-bn4 must be given -> sim run\n";
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print " or one of -t or -u must be given -> fpga run\n";
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print " either one of -c7,-ar,-arb, ... ,-n2,-s3 must be given -> sim run\n";
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print " or one of -t or -u must be given -> fpga run\n";
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}
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@@ -1,10 +1,11 @@
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#!/usr/bin/perl -w
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# $Id: tmuconv 1189 2019-07-13 16:41:07Z mueller $
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# $Id: tmuconv 1248 2022-07-07 06:25:50Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2008-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2022-07-06 1246 1.1.5 add DEUNA defs
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# 2019-07-13 1189 1.1.4 drop superfluous exists for $opts
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# 2018-12-18 1089 1.1.3 add and use bailout
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# 2018-10-05 1053 1.1.2 use 'ca.*' instead of 'sy.*' fields
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@@ -350,6 +351,10 @@ my %pdp11_regs = ( # use simh naming convention
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176502=> "tib.bu",
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176504=> "tob.cs",
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176506=> "tob.bu",
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174516=> "de.pr3",
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174514=> "de.pr2",
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174512=> "de.pr1",
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174510=> "de.pr0",
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174400=> "rl.cs ",
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174402=> "rl.ba ",
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174404=> "rl.da ",
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@@ -722,6 +727,7 @@ sub do_file {
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$emtyp_str .= " 074 PC11-PTP" if ($emlast_addr == 0074);
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$emtyp_str .= " 100 KW11-L" if ($emlast_addr == 0100);
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$emtyp_str .= " 104 KW11-P" if ($emlast_addr == 0104);
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$emtyp_str .= " 120 DEUNA" if ($emlast_addr == 0120);
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$emtyp_str .= " 160 RL11" if ($emlast_addr == 0160);
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$emtyp_str .= " 200 LP11" if ($emlast_addr == 0200);
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$emtyp_str .= " 220 RK11" if ($emlast_addr == 0220);
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@@ -1,11 +1,11 @@
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.\" -*- nroff -*-
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.\" $Id: tmuconv.1 1237 2022-05-15 07:51:47Z mueller $
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.\" $Id: tmuconv.1 1248 2022-07-07 06:25:50Z mueller $
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.\" SPDX-License-Identifier: GPL-3.0-or-later
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.\" Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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.\"
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.\" ------------------------------------------------------------------
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.
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.TH TMUCONV 1 2010-10-22 "Retro Project" "Retro Project Manual"
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.TH TMUCONV 1 2022-07-06 "Retro Project" "Retro Project Manual"
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.\" ------------------------------------------------------------------
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.SH NAME
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tmuconv \- convert w11a tmu output into human readable format
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@@ -60,6 +60,139 @@ trace ib transactions (ibus cycles)
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.\" ----------------------------------------------
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.IP "\fB\-help\fR"
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print full help text and exit.
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.
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.\" ------------------------------------------------------------------
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.SH TRACE OUTPUT FORMAT
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Each output line starts with the cycle number and the trace type.
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The format of the rest of the line depends on trace type.
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\fB\-t_id\fP: the instruction decode trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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the PC of the instruction
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.IP "-"
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the PSW at the beginning(!) of the instruction
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.IP "-"
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the instruction word (as loaded into the instruction register)
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.IP "-"
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the instruction in MACRO-11 syntax
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.IP "-"
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the number of cycles of the previous(!) instruction
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.PD
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.RE
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.PP
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.EX
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cycle pc psw ireg code nc
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71587 id 006054 000011 012410 mov (r4)+,(r0) (4)
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71683 id 002146 000340 116767 movb nnn(pc),nnn(pc) (9)
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.EE
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\fB\-t_ru\fP: the register update trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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the byte update indicator
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.IP "-"
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the register set (0 pr 1)
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.IP "-"
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the register number (0 to 7)
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.IP "-"
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the loaded data value
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.IP "-"
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in case of a stack pointer update the values of kernel, supervisor and user
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stack pointers
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.IP "-"
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in case of an R0-R5 update the values of all these six registers
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.IP "-"
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the symbolic name of the register
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.PD
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.RE
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.PP
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.EX
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cycle b sr data
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71578 ru 0 07 006102 pc
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71649 ru 0 06 002000 002000*------ ------ ksp
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71634 ru 0 04 010752 006110 006112 177776 010752 010752*010642 r04
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.EE
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\fB\-t_em\fP: the memory transaction trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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the r/w flag
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.IP "-"
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the byte enables
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.IP "-"
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the memory address (as 22bit number)
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.IP "-"
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the data written to memory
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.IP "-"
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the data received from memory
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.IP "-"
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four flag bits 'crwh' indicating cancel, read, write, and cache-hit
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.IP "-"
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the number of extra wait cycles
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.IP "-"
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in case of vector fetches and associated stack pushes some descriptive text
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.PD
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.RE
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.PP
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.EX
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cycle be addr wdat rdat crwh nc
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11374 em w 11 00000004 000006 0010 (1)
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52574 em r 11 00002164 177624 0101 (1)
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52530 em r 11 00000020 002142 0101 (1)
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52532 em r 11 00000022 000340 0101 (1) VFETCH 020 IOT
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52536 em w 11 00001776 000017 0010 (1)
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52538 em w 11 00001774 004316 0010 (1) SPUSH
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.EE
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\fB\-t_ib\fP: the ibus transaction trace gives
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.RS 2
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.PD 0
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.IP "-" 2
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two flag bits 'cr' indicating console and remote access
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.IP "-"
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two flag bits 'rm' indicating read/write and modify
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.IP "-"
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the byte enables
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.IP "-"
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the bus address (as 16bit number)
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.IP "-"
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the data written to bus
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.IP "-"
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the data received from bus
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.IP "-"
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the acknowledge flag
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.IP "-"
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the number of extra wait cycles
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.IP "-"
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if known, the symbolic name of the register
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.PD
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.RE
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.PP
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.EX
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cycle cr rmbe addr wdat rdat a nc name
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988 ib cr r 11 177500 000000 1 (0) ii.acr
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52583 ib -- w 11 177570 000001 1 (0) sdreg
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70729 ib -- r 11 177776 000004 1 (0) psw
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.EE
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The w11 CPU starts a cache cycle for each read or write, and cancels the
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cache request when an ibus access is detected. That's why an 'ib' line
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is usually preceded by an 'em' line with the 'cancel' flag, like
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.EX
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52582 em w 11 00177570 000001 cancel 1000 (1)
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52583 ib -- w 11 177570 000001 1 (0) sdreg
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.EE
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.
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.\" ------------------------------------------------------------------
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.SH EXAMPLES
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Reference in New Issue
Block a user