mirror of
https://github.com/wfjm/w11.git
synced 2026-03-27 10:41:30 +00:00
renames, cleanups, SimH V3.12-3 ready
- rtl/w11a - pdp11.vhd: rename cpuerr_type adderr->oddadr etc - pdp11_mmu.vhd: rename mmu_mmr0_type dspace->page_dspace - pdp11_sequencer.vhd: rename adderr -> oddadr, don't set after err_mmu - tools/asm-11/lib/defs_reg70.mac: rename cp.aer -> cp.odd - tools/dasm-11/lib/defs_reg70.das: rename cp.aer -> cp.odd - tools/tcl/rw11/defs.tcl: rename adderr -> oddadr (in cpuerr) - tools/tcode - cpu_details.mac: minor updates; get SimH V3.12-3 ready - cpu_mmu.mac: minor updates; get SimH V3.12-3 ready
This commit is contained in:
wfjm
@@ -1,4 +1,4 @@
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-- $Id: pdp11.vhd 1321 2022-11-24 15:06:47Z mueller $
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-- $Id: pdp11.vhd 1323 2022-12-01 08:00:41Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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@@ -11,6 +11,8 @@
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2022-11-29 1323 1.5.18 rename cpuerr_type adderr->oddadr, mmu_mmr0_type
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-- dspace->page_dspace; drop mmu_cntl_type.trap_done
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-- 2022-11-24 1321 1.5.17 add cpustat_type intpend
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-- 2022-11-21 1320 1.6.16 rename some rsv->ser and cpustat_type trap_->treq_;
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-- remove vm_cntl_type.trap_done; add in_vecysv;
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@@ -403,7 +405,7 @@ package pdp11 is
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type cpuerr_type is record -- CPU error register
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illhlt : slbit; -- illegal halt (in non-kernel mode)
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adderr : slbit; -- address error (odd, jmp/jsr reg)
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oddadr : slbit; -- odd address error
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nxm : slbit; -- non-existent memory
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iobto : slbit; -- I/O bus timeout (non-exist UB)
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ysv : slbit; -- yellow stack violation
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@@ -477,12 +479,11 @@ package pdp11 is
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cacc : slbit; -- console access (bypass mmu)
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dspace : slbit; -- dspace access
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mode : slv2; -- processor mode
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trap_done : slbit; -- mmu trap taken (set mmr0 bit)
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end record mmu_cntl_type;
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constant mmu_cntl_init : mmu_cntl_type := (
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'0','0','0','0', -- req, wacc, macc, cacc
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'0',"00",'0' -- dspace, mode, trap_done
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'0',"00" -- dspace, mode
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);
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type mmu_stat_type is record -- mmu status port
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@@ -520,7 +521,7 @@ package pdp11 is
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ena_trap : slbit; -- enable traps
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inst_compl : slbit; -- instruction complete
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page_mode : slv2; -- page mode
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dspace : slbit; -- address space (D=1, I=0)
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page_dspace : slbit; -- page address space (D=1, I=0)
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page_num : slv3; -- page number
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ena_mmu : slbit; -- enable memory management
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trace_prev : slbit; -- mmr12 trace status in prev. state
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@@ -1,4 +1,4 @@
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-- $Id: pdp11_mmu.vhd 1294 2022-09-07 14:21:20Z mueller $
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-- $Id: pdp11_mmu.vhd 1323 2022-12-01 08:00:41Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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@@ -17,7 +17,8 @@
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2022-09-05 1294 1,4.4 BUGFIX: correct trap and PDR A logic
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-- 2022-11-29 1323 1.4.5 rename mmu_mmr0_type dspace->page_dspace
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-- 2022-09-05 1294 1.4.4 BUGFIX: correct trap and PDR A logic
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-- 2022-08-13 1279 1.4.3 ssr->mmr rename
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-- 2011-11-18 427 1.4.2 now numeric_std clean
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-- 2010-10-23 335 1.4.1 use ib_sel
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@@ -78,7 +79,7 @@ architecture syn of pdp11_mmu is
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constant mmr0_ibf_ena_trap : integer := 9;
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constant mmr0_ibf_inst_compl : integer := 7;
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subtype mmr0_ibf_page_mode is integer range 6 downto 5;
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constant mmr0_ibf_dspace : integer := 4;
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constant mmr0_ibf_page_dspace : integer := 4;
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subtype mmr0_ibf_page_num is integer range 3 downto 1;
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constant mmr0_ibf_ena_mmu : integer := 0;
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@@ -171,7 +172,7 @@ begin
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mmr0out(mmr0_ibf_ena_trap) := R_MMR0.ena_trap;
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mmr0out(mmr0_ibf_inst_compl) := R_MMR0.inst_compl;
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mmr0out(mmr0_ibf_page_mode) := R_MMR0.page_mode;
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mmr0out(mmr0_ibf_dspace) := R_MMR0.dspace;
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mmr0out(mmr0_ibf_page_dspace):= R_MMR0.page_dspace;
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mmr0out(mmr0_ibf_page_num) := R_MMR0.page_num;
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mmr0out(mmr0_ibf_ena_mmu) := R_MMR0.ena_mmu;
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end if;
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@@ -386,9 +387,9 @@ begin
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end if;
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if mmr_freeze = '0' then
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nmmr0.dspace := DSPACE;
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nmmr0.page_num := apf;
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nmmr0.page_mode := CNTL.mode;
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nmmr0.page_dspace := DSPACE;
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nmmr0.page_num := apf;
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nmmr0.page_mode := CNTL.mode;
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end if;
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end if;
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end if;
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@@ -1,4 +1,4 @@
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-- $Id: pdp11_sequencer.vhd 1322 2022-11-28 19:31:57Z mueller $
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-- $Id: pdp11_sequencer.vhd 1323 2022-12-01 08:00:41Z mueller $
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-- SPDX-License-Identifier: GPL-3.0-or-later
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-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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@@ -13,6 +13,7 @@
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2022-11-29 1323 1.6.22 rename adderr -> oddadr, don't set after err_mmu
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-- 2022-11-28 1322 1.6.21 BUGFIX: correct mmu trap vs interrupt priority
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-- 2022-11-24 1321 1.6.20 BUGFIX: correct mmu trap handing in s_idecode
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-- 2022-11-21 1320 1.6.19 rename some rsv->ser and cpustat_type trap_->treq_;
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@@ -125,7 +126,7 @@ architecture syn of pdp11_sequencer is
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constant ibaddr_cpuerr : slv16 := slv(to_unsigned(8#177766#,16));
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constant cpuerr_ibf_illhlt : integer := 7;
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constant cpuerr_ibf_adderr : integer := 6;
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constant cpuerr_ibf_oddadr : integer := 6;
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constant cpuerr_ibf_nxm : integer := 5;
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constant cpuerr_ibf_iobto : integer := 4;
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constant cpuerr_ibf_ysv : integer := 3;
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@@ -296,7 +297,7 @@ begin
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idout := (others=>'0');
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if IBSEL_CPUERR = '1' then
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idout(cpuerr_ibf_illhlt) := R_CPUERR.illhlt;
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idout(cpuerr_ibf_adderr) := R_CPUERR.adderr;
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idout(cpuerr_ibf_oddadr) := R_CPUERR.oddadr;
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idout(cpuerr_ibf_nxm) := R_CPUERR.nxm;
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idout(cpuerr_ibf_iobto) := R_CPUERR.iobto;
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idout(cpuerr_ibf_ysv) := R_CPUERR.ysv;
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@@ -2383,8 +2384,8 @@ begin
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nstatus.in_vecysv := '0'; -- cancel ysv flow
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ndpcntl.gr_we := '1';
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if R_VMSTAT.err_odd='1' or R_VMSTAT.err_mmu='1' then
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ncpuerr.adderr := '1';
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if R_VMSTAT.err_odd='1' then
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ncpuerr.oddadr := '1';
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elsif R_VMSTAT.err_nxm = '1' then
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ncpuerr.nxm := '1';
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elsif R_VMSTAT.err_iobto = '1' then
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@@ -2394,7 +2395,7 @@ begin
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nstate := s_abort_4;
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elsif R_VMSTAT.err_odd = '1' then
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ncpuerr.adderr := '1';
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ncpuerr.oddadr := '1';
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nstate := s_abort_4;
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elsif R_VMSTAT.err_nxm = '1' then
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ncpuerr.nxm := '1';
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@@ -1,6 +1,6 @@
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; $Id: defs_reg70.mac 1184 2019-07-10 20:39:44Z mueller $
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; $Id: defs_reg70.mac 1323 2022-12-01 08:00:41Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; definitions for 11/70 CPU registers (as in defs_reg70.das)
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;
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@@ -23,7 +23,7 @@
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; symbol definitions for cpuerr
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;
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cp.hlt = 000200
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cp.aer = 000100
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cp.odd = 000100
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cp.nxm = 000040
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cp.ito = 000020
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cp.ysv = 000010
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@@ -1,4 +1,4 @@
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# $Id: defs_reg70.das 1286 2022-08-25 06:53:38Z mueller $
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# $Id: defs_reg70.das 1323 2022-12-01 08:00:41Z mueller $
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#
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# definitions for 11/70 cpu registers
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#
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@@ -20,7 +20,7 @@
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.symbol cp.ubm=170200
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#
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.symset %cp.err = cp.hlt=000200,\
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cp.aer=000100,\
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cp.odd=000100,\
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cp.nxm=000040,\
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cp.ito=000020,\
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cp.ysv=000010,\
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@@ -1,9 +1,10 @@
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# $Id: defs.tcl 1320 2022-11-22 18:52:59Z mueller $
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# $Id: defs.tcl 1323 2022-12-01 08:00:41Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2022-11-29 1323 1.0.12 rename adderr -> oddadr (in cpuerr)
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# 2022-11-21 1320 1.0.11 rename RUST recrsv -> recser
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# 2022-09-03 1292 1.0.10 shorter field names for MMR0,MMR1
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# 2022-08-07 1273 1.0.9 ssr->mmr rename
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@@ -89,7 +90,7 @@ namespace eval rw11 {
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#
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# CPUERR - CPU Error Register -------------------------------------
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set A_CPUERR 0177766
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regdsc CPUERR {illhlt 7} {adderr 6} {nxm 5} {iobto 4} {ysv 3} {rsv 2}
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regdsc CPUERR {illhlt 7} {oddadr 6} {nxm 5} {iobto 4} {ysv 3} {rsv 2}
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#
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# CNTRL - Memory System Control Register -------------------------
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set A_CNTRL 0177746
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@@ -1,10 +1,10 @@
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; $Id: cpu_details.mac 1322 2022-11-28 19:31:57Z mueller $
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; $Id: cpu_details.mac 1323 2022-12-01 08:00:41Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-11-22 1320 1.0 Initial version
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; 2022-11-29 1323 1.0 Initial version
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; 2022-07-18 1259 0.1 First draft
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;
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; Test CPU details
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@@ -174,7 +174,7 @@ ta0102: spl 0 ; ensure execution at PR0
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; Test cp.hlt: halt in non-kernel mode
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;
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ta0201: mov #177777,(r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; ensure that CPUERR is zero
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htsteq (r0) ; ensure that CPUERR is zero
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;
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mov #4000$,r2 ; mode list (user,supervisor)
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mov #2,r3 ; number of modes
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@@ -194,7 +194,7 @@ ta0201: mov #177777,(r0) ; clear CPUERR (any write should)
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3000$: hcmpeq r1,#1 ; check tracer
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hcmpeq (r0),#cp.hlt ; check CPUERR
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mov #cp.rsv,(r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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htsteq (r0) ; check CPUERR
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;
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sob r3,1000$ ; go for next mode
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;
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@@ -205,15 +205,15 @@ ta0201: mov #177777,(r0) ; clear CPUERR (any write should)
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;
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9999$: iot ; end of test A2.1
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;
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; Test A2.2 -- CPUERR cp.aer +++++++++++++++++++++++++++++++++++++++++
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; Test cp.aer: address error abort
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; Test A2.2 -- CPUERR cp.odd +++++++++++++++++++++++++++++++++++++++++
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; Test cp.odd: odd address error abort
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;
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ta0202: mov #1000$,vhustp ; continuation address
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tst @#001 ; odd address access
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halt
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1000$: hcmpeq (r0),#cp.aer ; check CPUERR
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1000$: hcmpeq (r0),#cp.odd ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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htsteq (r0) ; check CPUERR
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;
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9999$: iot ; end of test A2.2
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;
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@@ -235,7 +235,7 @@ ta0203: cmpb systyp,#sy.e11 ; e11 V7.3 return wrong CPUERR value
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halt
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1000$: hcmpeq (r0),#cp.nxm ; check CPUERR
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com (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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htsteq (r0) ; check CPUERR
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;
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reset ; disable mmu ;! MMU off
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pop kipar6 ; restore kipar6
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@@ -250,7 +250,7 @@ ta0204: mov #1000$,vhustp ; continuation address
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halt
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1000$: hcmpeq (r0),#cp.ito ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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htsteq (r0) ; check CPUERR
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;
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9999$: iot ; end of test A2.4
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;
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@@ -266,7 +266,7 @@ ta0205: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt trap, runs on hold
|
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halt ; not executed, handler continues at 1000$
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1000$: hcmpeq (r0),#cp.ysv ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
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htsteq (r0) ; check CPUERR
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;
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mov #stack,sp
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9999$: iot ; end of test A2.5
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@@ -280,36 +280,46 @@ ta0206: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt abort, runs on hold
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mov #340,sp
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clr -(sp) ; should abort (not trap)
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halt
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1000$: mov #stack,sp ; direct iit handler
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1000$: htsteq sp ; check SP=0
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hcmpeq (r0),#cp.rsv ; check CPUERR
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clr (r0) ; clear CPUERR (any write should)
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hcmpeq (r0),#0 ; check CPUERR
|
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htsteq (r0) ; check CPUERR
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mov #stack,sp ; restore stack
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;
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9999$: iot ; end of test A2.6
|
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;
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; Test A2.7 -- CPUERR cp.rsv+cp.aer (odd address) ++++++++++++++++++++
|
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; Test cp.aer: fatal stack error after odd stack
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; Test A2.7 -- CPUERR cp.odd + stack error +++++++++++++++++++++++++++
|
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; Test cp.odd: fatal stack error after odd stack
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;
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ta0207: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to odd stack, abort after halt
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beq 9999$
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mov #1000$,v..iit ; setup direct iit handler
|
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cmpb systyp,#sy.sih ; SimH uses J11 semantics
|
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bne 100$
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||||
mov #<cp.rsv+cp.odd>,1010$+2 ; and sets rsv for all stack errors
|
||||
;
|
||||
100$: mov #1000$,v..iit ; setup direct iit handler
|
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mov #stack-1,sp
|
||||
clr -(sp) ; odd-address abort, fatal stack error
|
||||
halt
|
||||
1000$: mov #stack,sp ; direct iit handler
|
||||
hcmpeq (r0),#<cp.rsv+cp.aer> ; check CPUERR
|
||||
1000$: htsteq sp ; check SP=0
|
||||
1010$: hcmpeq (r0),#<cp.rsv+cp.odd> ; check CPUERR
|
||||
clr (r0) ; clear CPUERR (any write should)
|
||||
hcmpeq (r0),#0 ; check CPUERR
|
||||
htsteq (r0) ; check CPUERR
|
||||
mov #stack,sp ; restore stack
|
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;
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||||
9999$: iot ; end of test A2.7
|
||||
;
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||||
; Test A2.8 -- CPUERR cp.rsv+cp.nxm ++++++++++++++++++++++++++++++++++
|
||||
; Test A2.8 -- CPUERR cp.nxm + stack error +++++++++++++++++++++++++++
|
||||
; Test cp.nxm: fatal stack error after non-existent memory abort
|
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; Setup like in A2.3, put stack at p6base+4
|
||||
;
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||||
ta0208: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
|
||||
beq 9999$
|
||||
mov #1000$,v..iit ; setup direct iit handler
|
||||
cmpb systyp,#sy.sih ; SimH uses J11 semantics
|
||||
bne 100$
|
||||
mov #<cp.rsv+cp.nxm>,1010$+2 ; and sets rsv for all stack errors
|
||||
;
|
||||
100$: mov #1000$,v..iit ; setup direct iit handler
|
||||
mov #177400,kipar6
|
||||
mov #m3.e22,mmr3 ; 22-bit mode
|
||||
mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
|
||||
@@ -317,42 +327,48 @@ ta0208: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
|
||||
mov #p6base+4,sp ; stack in non-existing memory
|
||||
clr -(sp) ; non-existing memory, fatal stack error
|
||||
halt
|
||||
1000$: mov #stack,sp ; direct iit handler
|
||||
hcmpeq (r0),#<cp.rsv+cp.nxm> ; check CPUERR
|
||||
1000$: htsteq sp ; check SP=0
|
||||
1010$: hcmpeq (r0),#<cp.rsv+cp.nxm> ; check CPUERR
|
||||
clr (r0) ; clear CPUERR (any write should)
|
||||
hcmpeq (r0),#0 ; check CPUERR
|
||||
htsteq (r0) ; check CPUERR
|
||||
mov #stack,sp ; restore stack
|
||||
;
|
||||
reset ;! MMU off
|
||||
mov #001400,kipar6 ; restore kipar6
|
||||
;
|
||||
9999$: iot ; end of test A2.8
|
||||
;
|
||||
; Test A2.9 -- CPUERR cp.rsv+cp.ito ++++++++++++++++++++++++++++++++++
|
||||
; Test A2.9 -- CPUERR cp.ito + stack error +++++++++++++++++++++++++++
|
||||
; Test cp.ito: fatal stack error after unibus timeout
|
||||
; Setup like in A2.4, put stack at 160004
|
||||
;
|
||||
ta0209: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
|
||||
beq 9999$
|
||||
mov #1000$,v..iit ; setup direct iit handler
|
||||
cmpb systyp,#sy.sih ; SimH uses J11 semantics
|
||||
bne 100$
|
||||
mov #<cp.rsv+cp.ito>,1010$+2 ; and sets rsv for all stack errors
|
||||
;
|
||||
100$: mov #1000$,v..iit ; setup direct iit handler
|
||||
mov #160004,sp ; stack at non-existing unibus device
|
||||
clr -(sp) ; non-existing memory, fatal stack error
|
||||
halt
|
||||
1000$: mov #stack,sp ; direct iit handler
|
||||
hcmpeq (r0),#<cp.rsv+cp.ito> ; check CPUERR
|
||||
1000$: htsteq sp ; check SP=0
|
||||
1010$: hcmpeq (r0),#<cp.rsv+cp.ito> ; check CPUERR
|
||||
clr (r0) ; clear CPUERR (any write should)
|
||||
hcmpeq (r0),#0 ; check CPUERR
|
||||
htsteq (r0) ; check CPUERR
|
||||
mov #stack,sp ; restore stack
|
||||
;
|
||||
9999$: iot ; end of test A2.9
|
||||
;
|
||||
; Test A2.10 -- CPUERR cp.rsv+cp.aer (mmu abort) +++++++++++++++++++++
|
||||
; Test cp.rsv: fatal stack error after mmu abort
|
||||
; Test A2.10 -- CPUERR mmu abort + stack error +++++++++++++++++++++++
|
||||
; Test cp.rsv: fatal stack error after mmu abort
|
||||
; Set kernel I page 6 to non-resident
|
||||
;
|
||||
ta0210: cmpb systyp,#sy.sih ; this fatal stack error fails in SimH
|
||||
beq 9999$
|
||||
cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, does MMU 250
|
||||
beq 9999$
|
||||
mov #1000$,v..iit ; setup direct iit handler
|
||||
ta0210: cmpb systyp,#sy.sih ; SimH uses J11 semantics
|
||||
bne 100$
|
||||
mov #cp.rsv,1010$+2 ; and sets rsv for all stack errors
|
||||
;
|
||||
100$: mov #1000$,v..iit ; setup direct iit handler
|
||||
clr kipdr6 ; set non-resident
|
||||
mov #m3.e22,mmr3 ; 22-bit mode
|
||||
mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
|
||||
@@ -360,10 +376,11 @@ ta0210: cmpb systyp,#sy.sih ; this fatal stack error fails in SimH
|
||||
mov #p6base+4,sp ; stack in non-resident memory
|
||||
clr -(sp) ; MMU abort, fatal stack error
|
||||
halt
|
||||
1000$: mov #stack,sp ; direct iit handler
|
||||
hcmpeq (r0),#<cp.rsv+cp.aer> ; check CPUERR
|
||||
1000$: htsteq sp ; check SP=0
|
||||
1010$: hcmpeq (r0),#cp.rsv ; check CPUERR
|
||||
clr (r0) ; clear CPUERR (any write should)
|
||||
hcmpeq (r0),#0 ; check CPUERR
|
||||
htsteq (r0) ; check CPUERR
|
||||
mov #stack,sp ; restore stack
|
||||
;
|
||||
reset ;! MMU off
|
||||
mov kipdr5,kipdr6 ; restore kipdr6 (default kipdr are identical)
|
||||
@@ -406,8 +423,8 @@ ta0301:
|
||||
;
|
||||
2000$: movb #7,1(r3) ; write MSB
|
||||
hcmpeq #3400,(r3) ; check MSB written
|
||||
;; movb #70,(r3) ; write LSB (SimH not yet!)
|
||||
;; hcmpeq #3400,(r3) ; check MSB unchanged (SimH not yet!)
|
||||
movb #70,(r3) ; write LSB
|
||||
hcmpeq #3400,(r3) ; check MSB unchanged
|
||||
clr (r3) ; STKLIM to default
|
||||
;
|
||||
9999$: iot ; end of test A3.1
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
; $Id: cpu_mmu.mac 1322 2022-11-28 19:31:57Z mueller $
|
||||
; $Id: cpu_mmu.mac 1323 2022-12-01 08:00:41Z mueller $
|
||||
; SPDX-License-Identifier: GPL-3.0-or-later
|
||||
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
;
|
||||
; Revision History:
|
||||
; Date Rev Version Comment
|
||||
; 2022-09-10 1297 1.0 Initial version
|
||||
; 2022-11-29 1323 1.0 Initial version
|
||||
; 2022-07-24 1262 0.1 First draft
|
||||
;
|
||||
; Test CPU MMU: all aspects of the MMU
|
||||
@@ -639,9 +639,7 @@ tb0401: clr mmr3 ; no d dspace, no 22bit
|
||||
; test abort PS on stack
|
||||
1020$: hcmpeq (sp)+,#^b1010000000000000 ; abort PS
|
||||
;
|
||||
mov mmr0,r5
|
||||
bic #m0.ico,r5
|
||||
hcmpeq r5,#m0.anr!m0.ale!0100!<6*m0.pno>!m0.ena ; check mmr0
|
||||
hcmpeq mmr0,#m0.anr!m0.ale!0100!<6*m0.pno>!m0.ena ; check mmr0
|
||||
hcmpeq mmr2,#p6base+200 ; check mmr2
|
||||
;
|
||||
reset ;! MMU off
|
||||
@@ -1326,13 +1324,8 @@ td0101:
|
||||
hcmpeq vc2sek+0,vc2dat+2 ; 2nd push
|
||||
hcmpeq vc2sek-2,vc2dat+4 ; 3rd push
|
||||
hcmpeq vc2sek-4,vc2dat+6 ; 4th push
|
||||
;
|
||||
; SimH wrongly sets m0.ico, skip mmr0 check for SimH
|
||||
cmpb systyp,#sy.sih
|
||||
beq 1010$
|
||||
hcmpeq 3000$,#<m0.ale!m0.pmu!m0.dsp!<1*m0.pno>!m0.ena>
|
||||
;
|
||||
1010$: hcmpeq 3001$,#^b1111011000010100 ; -2,sp;2,r4
|
||||
hcmpeq 3001$,#^b1111011000010100 ; -2,sp;2,r4
|
||||
hcmpeq 3002$,#<vc2l1-vc2>
|
||||
;
|
||||
; reset user mode pdr/par
|
||||
@@ -1946,9 +1939,7 @@ tf0102: mov #154345,@#p6base ; inititialize target
|
||||
;
|
||||
vhmmua: mov vhvmmu,r1 ; get context
|
||||
beq 1000$ ; if 0 halt
|
||||
mov mmr0,r0
|
||||
bic #m0.ico,r0 ; mask ico (for Simh compatibility)
|
||||
hcmpeq r0,(r1)+ ; check mmr0
|
||||
hcmpeq mmr0,(r1)+ ; check mmr0
|
||||
hcmpeq mmr1,(r1)+ ; check mmr1
|
||||
bic #m0.anr!m0.ale!m0.ard,mmr0 ; reset mmr0 abort flags
|
||||
mov r1,(sp) ; set up kernel return address
|
||||
|
||||
Reference in New Issue
Block a user