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renames, cleanups, SimH V3.12-3 ready

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- rtl/w11a
  - pdp11.vhd: rename cpuerr_type adderr->oddadr etc
  - pdp11_mmu.vhd: rename mmu_mmr0_type dspace->page_dspace
  - pdp11_sequencer.vhd: rename adderr -> oddadr, don't set after err_mmu
- tools/asm-11/lib/defs_reg70.mac: rename cp.aer -> cp.odd
- tools/dasm-11/lib/defs_reg70.das: rename cp.aer -> cp.odd
- tools/tcl/rw11/defs.tcl: rename adderr -> oddadr (in cpuerr)
- tools/tcode
  - cpu_details.mac: minor updates; get SimH V3.12-3 ready
  - cpu_mmu.mac:  minor updates; get SimH V3.12-3 ready
This commit is contained in:
wfjm
2022-12-01 09:04:57 +01:00
parent f6ff0fa701
commit 2421554d4e
8 changed files with 92 additions and 80 deletions
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99
tools/tcode/cpu_details.mac
View File

@@ -1,10 +1,10 @@
; $Id: cpu_details.mac 1322 2022-11-28 19:31:57Z mueller $
; $Id: cpu_details.mac 1323 2022-12-01 08:00:41Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2022-11-22 1320 1.0 Initial version
; 2022-11-29 1323 1.0 Initial version
; 2022-07-18 1259 0.1 First draft
;
; Test CPU details
@@ -174,7 +174,7 @@ ta0102: spl 0 ; ensure execution at PR0
; Test cp.hlt: halt in non-kernel mode
;
ta0201: mov #177777,(r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; ensure that CPUERR is zero
htsteq (r0) ; ensure that CPUERR is zero
;
mov #4000$,r2 ; mode list (user,supervisor)
mov #2,r3 ; number of modes
@@ -194,7 +194,7 @@ ta0201: mov #177777,(r0) ; clear CPUERR (any write should)
3000$: hcmpeq r1,#1 ; check tracer
hcmpeq (r0),#cp.hlt ; check CPUERR
mov #cp.rsv,(r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
;
sob r3,1000$ ; go for next mode
;
@@ -205,15 +205,15 @@ ta0201: mov #177777,(r0) ; clear CPUERR (any write should)
;
9999$: iot ; end of test A2.1
;
; Test A2.2 -- CPUERR cp.aer +++++++++++++++++++++++++++++++++++++++++
; Test cp.aer: address error abort
; Test A2.2 -- CPUERR cp.odd +++++++++++++++++++++++++++++++++++++++++
; Test cp.odd: odd address error abort
;
ta0202: mov #1000$,vhustp ; continuation address
tst @#001 ; odd address access
halt
1000$: hcmpeq (r0),#cp.aer ; check CPUERR
1000$: hcmpeq (r0),#cp.odd ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
;
9999$: iot ; end of test A2.2
;
@@ -235,7 +235,7 @@ ta0203: cmpb systyp,#sy.e11 ; e11 V7.3 return wrong CPUERR value
halt
1000$: hcmpeq (r0),#cp.nxm ; check CPUERR
com (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
;
reset ; disable mmu ;! MMU off
pop kipar6 ; restore kipar6
@@ -250,7 +250,7 @@ ta0204: mov #1000$,vhustp ; continuation address
halt
1000$: hcmpeq (r0),#cp.ito ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
;
9999$: iot ; end of test A2.4
;
@@ -266,7 +266,7 @@ ta0205: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt trap, runs on hold
halt ; not executed, handler continues at 1000$
1000$: hcmpeq (r0),#cp.ysv ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
;
mov #stack,sp
9999$: iot ; end of test A2.5
@@ -280,36 +280,46 @@ ta0206: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt abort, runs on hold
mov #340,sp
clr -(sp) ; should abort (not trap)
halt
1000$: mov #stack,sp ; direct iit handler
1000$: htsteq sp ; check SP=0
hcmpeq (r0),#cp.rsv ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
mov #stack,sp ; restore stack
;
9999$: iot ; end of test A2.6
;
; Test A2.7 -- CPUERR cp.rsv+cp.aer (odd address) ++++++++++++++++++++
; Test cp.aer: fatal stack error after odd stack
; Test A2.7 -- CPUERR cp.odd + stack error +++++++++++++++++++++++++++
; Test cp.odd: fatal stack error after odd stack
;
ta0207: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to odd stack, abort after halt
beq 9999$
mov #1000$,v..iit ; setup direct iit handler
cmpb systyp,#sy.sih ; SimH uses J11 semantics
bne 100$
mov #<cp.rsv+cp.odd>,1010$+2 ; and sets rsv for all stack errors
;
100$: mov #1000$,v..iit ; setup direct iit handler
mov #stack-1,sp
clr -(sp) ; odd-address abort, fatal stack error
halt
1000$: mov #stack,sp ; direct iit handler
hcmpeq (r0),#<cp.rsv+cp.aer> ; check CPUERR
1000$: htsteq sp ; check SP=0
1010$: hcmpeq (r0),#<cp.rsv+cp.odd> ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
mov #stack,sp ; restore stack
;
9999$: iot ; end of test A2.7
;
; Test A2.8 -- CPUERR cp.rsv+cp.nxm ++++++++++++++++++++++++++++++++++
; Test A2.8 -- CPUERR cp.nxm + stack error +++++++++++++++++++++++++++
; Test cp.nxm: fatal stack error after non-existent memory abort
; Setup like in A2.3, put stack at p6base+4
;
ta0208: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
beq 9999$
mov #1000$,v..iit ; setup direct iit handler
cmpb systyp,#sy.sih ; SimH uses J11 semantics
bne 100$
mov #<cp.rsv+cp.nxm>,1010$+2 ; and sets rsv for all stack errors
;
100$: mov #1000$,v..iit ; setup direct iit handler
mov #177400,kipar6
mov #m3.e22,mmr3 ; 22-bit mode
mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
@@ -317,42 +327,48 @@ ta0208: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
mov #p6base+4,sp ; stack in non-existing memory
clr -(sp) ; non-existing memory, fatal stack error
halt
1000$: mov #stack,sp ; direct iit handler
hcmpeq (r0),#<cp.rsv+cp.nxm> ; check CPUERR
1000$: htsteq sp ; check SP=0
1010$: hcmpeq (r0),#<cp.rsv+cp.nxm> ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
mov #stack,sp ; restore stack
;
reset ;! MMU off
mov #001400,kipar6 ; restore kipar6
;
9999$: iot ; end of test A2.8
;
; Test A2.9 -- CPUERR cp.rsv+cp.ito ++++++++++++++++++++++++++++++++++
; Test A2.9 -- CPUERR cp.ito + stack error +++++++++++++++++++++++++++
; Test cp.ito: fatal stack error after unibus timeout
; Setup like in A2.4, put stack at 160004
;
ta0209: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
beq 9999$
mov #1000$,v..iit ; setup direct iit handler
cmpb systyp,#sy.sih ; SimH uses J11 semantics
bne 100$
mov #<cp.rsv+cp.ito>,1010$+2 ; and sets rsv for all stack errors
;
100$: mov #1000$,v..iit ; setup direct iit handler
mov #160004,sp ; stack at non-existing unibus device
clr -(sp) ; non-existing memory, fatal stack error
halt
1000$: mov #stack,sp ; direct iit handler
hcmpeq (r0),#<cp.rsv+cp.ito> ; check CPUERR
1000$: htsteq sp ; check SP=0
1010$: hcmpeq (r0),#<cp.rsv+cp.ito> ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
mov #stack,sp ; restore stack
;
9999$: iot ; end of test A2.9
;
; Test A2.10 -- CPUERR cp.rsv+cp.aer (mmu abort) +++++++++++++++++++++
; Test cp.rsv: fatal stack error after mmu abort
; Test A2.10 -- CPUERR mmu abort + stack error +++++++++++++++++++++++
; Test cp.rsv: fatal stack error after mmu abort
; Set kernel I page 6 to non-resident
;
ta0210: cmpb systyp,#sy.sih ; this fatal stack error fails in SimH
beq 9999$
cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, does MMU 250
beq 9999$
mov #1000$,v..iit ; setup direct iit handler
ta0210: cmpb systyp,#sy.sih ; SimH uses J11 semantics
bne 100$
mov #cp.rsv,1010$+2 ; and sets rsv for all stack errors
;
100$: mov #1000$,v..iit ; setup direct iit handler
clr kipdr6 ; set non-resident
mov #m3.e22,mmr3 ; 22-bit mode
mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
@@ -360,10 +376,11 @@ ta0210: cmpb systyp,#sy.sih ; this fatal stack error fails in SimH
mov #p6base+4,sp ; stack in non-resident memory
clr -(sp) ; MMU abort, fatal stack error
halt
1000$: mov #stack,sp ; direct iit handler
hcmpeq (r0),#<cp.rsv+cp.aer> ; check CPUERR
1000$: htsteq sp ; check SP=0
1010$: hcmpeq (r0),#cp.rsv ; check CPUERR
clr (r0) ; clear CPUERR (any write should)
hcmpeq (r0),#0 ; check CPUERR
htsteq (r0) ; check CPUERR
mov #stack,sp ; restore stack
;
reset ;! MMU off
mov kipdr5,kipdr6 ; restore kipdr6 (default kipdr are identical)
@@ -406,8 +423,8 @@ ta0301:
;
2000$: movb #7,1(r3) ; write MSB
hcmpeq #3400,(r3) ; check MSB written
;; movb #70,(r3) ; write LSB (SimH not yet!)
;; hcmpeq #3400,(r3) ; check MSB unchanged (SimH not yet!)
movb #70,(r3) ; write LSB
hcmpeq #3400,(r3) ; check MSB unchanged
clr (r3) ; STKLIM to default
;
9999$: iot ; end of test A3.1

19
tools/tcode/cpu_mmu.mac
View File

@@ -1,10 +1,10 @@
; $Id: cpu_mmu.mac 1322 2022-11-28 19:31:57Z mueller $
; $Id: cpu_mmu.mac 1323 2022-12-01 08:00:41Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2022-09-10 1297 1.0 Initial version
; 2022-11-29 1323 1.0 Initial version
; 2022-07-24 1262 0.1 First draft
;
; Test CPU MMU: all aspects of the MMU
@@ -639,9 +639,7 @@ tb0401: clr mmr3 ; no d dspace, no 22bit
; test abort PS on stack
1020$: hcmpeq (sp)+,#^b1010000000000000 ; abort PS
;
mov mmr0,r5
bic #m0.ico,r5
hcmpeq r5,#m0.anr!m0.ale!0100!<6*m0.pno>!m0.ena ; check mmr0
hcmpeq mmr0,#m0.anr!m0.ale!0100!<6*m0.pno>!m0.ena ; check mmr0
hcmpeq mmr2,#p6base+200 ; check mmr2
;
reset ;! MMU off
@@ -1326,13 +1324,8 @@ td0101:
hcmpeq vc2sek+0,vc2dat+2 ; 2nd push
hcmpeq vc2sek-2,vc2dat+4 ; 3rd push
hcmpeq vc2sek-4,vc2dat+6 ; 4th push
;
; SimH wrongly sets m0.ico, skip mmr0 check for SimH
cmpb systyp,#sy.sih
beq 1010$
hcmpeq 3000$,#<m0.ale!m0.pmu!m0.dsp!<1*m0.pno>!m0.ena>
;
1010$: hcmpeq 3001$,#^b1111011000010100 ; -2,sp;2,r4
hcmpeq 3001$,#^b1111011000010100 ; -2,sp;2,r4
hcmpeq 3002$,#<vc2l1-vc2>
;
; reset user mode pdr/par
@@ -1946,9 +1939,7 @@ tf0102: mov #154345,@#p6base ; inititialize target
;
vhmmua: mov vhvmmu,r1 ; get context
beq 1000$ ; if 0 halt
mov mmr0,r0
bic #m0.ico,r0 ; mask ico (for Simh compatibility)
hcmpeq r0,(r1)+ ; check mmr0
hcmpeq mmr0,(r1)+ ; check mmr0
hcmpeq mmr1,(r1)+ ; check mmr1
bic #m0.anr!m0.ale!m0.ard,mmr0 ; reset mmr0 abort flags
mov r1,(sp) ; set up kernel return address