- interim release w11a_V0.561 (untagged)

- Added simple simulation model of Cypress FX2 and test benches for functional verifcation of FX2 controller - Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys - Added test systems for rlink over USB verification for Nexys3 & Atlys
2026-03-04 10:45:39 +00:00 · 2013-01-06 16:19:26 +00:00
parent cbd8ce3468
commit 29d2dc5bef
67 changed files with 6004 additions and 3227 deletions
--- a/6
+++ b/6
@@ -1,4 +1,4 @@
-# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
+# $Id: Makefile 472 2013-01-06 14:39:10Z mueller $
 #
 # 'Meta Makefile' for whole retro project
 #   allows to make all synthesis targets
@@ -19,6 +19,9 @@ SYN_all += rtl/sys_gen/tst_rlink/nexys2
 SYN_all += rtl/sys_gen/tst_rlink/nexys3
 SYN_all += rtl/sys_gen/tst_rlink/s3board
 SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
+SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
+SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
+SYN_all += rtl/sys_gen/tst_rlink_cuff/atlys/ic
 SYN_all += rtl/sys_gen/tst_serloop/nexys2
 SYN_all += rtl/sys_gen/tst_serloop/nexys3
 SYN_all += rtl/sys_gen/tst_serloop/s3board
@@ -34,6 +37,7 @@ SIM_all += rtl/bplib/nxcramlib/tb
 SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
 SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
 SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
+SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
 SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
 SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
 SIM_all += rtl/sys_gen/tst_serloop/s3board/tb
--- a/doc/README.txt
+++ b/doc/README.txt
@@ -1,4 +1,4 @@
-# $Id: README.txt 467 2013-01-02 19:49:05Z mueller $
+# $Id: README.txt 472 2013-01-06 14:39:10Z mueller $

 Release notes for w11a

@@ -40,7 +40,7 @@ Release notes for w11a
   rtl/sys_gen/tst_rlink          - top level designs for an rlink tester
     nexys2,nexys3,s3board          - systems for Nexsy2,Nexsy3,S3BOARD
   rtl/sys_gen/tst_rlink_cuff     - top level designs for rlink over FX2 tester
-     nexys2                         - systems for Nexsy2
+     nexys2,nexys3,atlys            - systems for Atlys,Nexsy2,Nexsy3
   rtl/sys_gen/tst_serloop        - top level designs for serport loop tester
     nexys2,nexys3,s3board          - systems for Nexsy2,Nexsy3,S3BOARD
   rtl/sys_gen/tst_snhumanio      - top level designs for human I/O tester
@@ -75,6 +75,26 @@ Release notes for w11a

 3. Change Log ----------------------------------------------------------------

+- trunk (2013-01-06: svn rev 18(oc) 472(wfjm); untagged w11a_V0.561) +++++++++
+
+  - Summary
+    - Added simple simulation model of Cypress FX2 and test benches for
+      functional verifcation of FX2 controller
+    - Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys
+    - Added test systems for rlink over USB verification for Nexys3 & Atlys
+
+  - New features
+    - new test benches
+      - rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2
+    - new systems
+      - rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n3
+      - rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_atlys
+
+  - Bug fixes
+    - tools/fx2/src: FX2 firmware now properly re-initializes hardware registers
+        and will work on Nexys3 and Atlys boards with default Digilent EPROM
+    - rtl/bplib/fx2lib: read pipeline logic in FX2 controller corrected
+
 - trunk (2013-01-02: svn rev 17(oc) 467(wfjm); untagged w11a_V0.56) ++++++++++

  - Summary
@@ -89,7 +109,7 @@ Release notes for w11a
            in the file README_USB-VID-PID.txt. You'll be responsible for any
            misuse of the defaults provided with the project sources !!

-  - New refernce system
+  - New reference system
    The development and test system was upgraded from Kubuntu 10.04 to 12.04.
    The version of several key tools and libraries changed:
       linux kernel    3.2.0    (was  2.6.32)
--- a/doc/w11a_os_guide.txt
+++ b/doc/w11a_os_guide.txt
@@ -1,4 +1,4 @@
-# $Id: w11a_os_guide.txt 442 2011-12-23 10:03:28Z mueller $
+# $Id: w11a_os_guide.txt 469 2013-01-05 12:29:44Z mueller $

 Guide to run operating system images on w11a systems

@@ -52,7 +52,7 @@ Guide to run operating system images on w11a systems
 3. Unix V5 system ---------------------------------------------------------

   - A disk set is available from
-       http://www-linux.gsi.de/~mueller/retro/oc_w11/data/unix_v5_rkset.tgz
+       http://www.retro11.de/data/oc_w11/unix_v5_rkset.tgz
     Download, unpack and copy the disk images (*.dsk) to
       $RETROBASE/rtl/sys_gen/w11a/tb

@@ -97,7 +97,7 @@ Guide to run operating system images on w11a systems

 4. 2.11BSD system ---------------------------------------------------------
   - A disk set is available from
-       http://www-linux.gsi.de/~mueller/retro/oc_w11/data/211bsd_rkset.tgz
+       http://www.retro11.de/data/oc_w11/211bsd_rkset.tgz
     Download, unpack and copy the disk images (*.dsk) to
       $RETROBASE/rtl/sys_gen/w11a/tb

--- a/rtl/bplib/atlys/atlys_pins_fx2.ucf
+++ b/rtl/bplib/atlys/atlys_pins_fx2.ucf
@@ -0,0 +1,36 @@
+## $Id: atlys_pins_fx2.ucf 471 2013-01-05 19:46:38Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2013-01-05   471   1.0    Initial version 
+##
+## Cypress EZ-USB FX2 Interface -- in Bank 0 ---------------------------------
+##
+##
+NET "I_FX2_IFCLK" LOC = "c10"    | IOSTANDARD=LVCMOS33;
+## 
+NET "IO_FX2_DATA<0>" LOC = "a2"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<1>" LOC = "d6"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<2>" LOC = "c6"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<3>" LOC = "b3"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<4>" LOC = "a3"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<5>" LOC = "b4"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<6>" LOC = "a4"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<7>" LOC = "c5"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER;
+##
+NET "O_FX2_SLWR_N" LOC = "e13"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_SLRD_N" LOC = "f13"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_SLOE_N" LOC = "a15"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_FX2_PKTEND_N" LOC = "c4"  | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_FX2_FIFO<0>" LOC = "a14"  | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_FIFO<1>" LOC = "b14"  | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+## assume that PA.7 is used as FLAGD (and not as SLCS#)
+NET "I_FX2_FLAG<0>" LOC = "b9"   | IOSTANDARD=LVCMOS33;   ## flag a (program)
+NET "I_FX2_FLAG<1>" LOC = "a9"   | IOSTANDARD=LVCMOS33;   ## flag b (full)
+NET "I_FX2_FLAG<2>" LOC = "c15"  | IOSTANDARD=LVCMOS33;   ## flag c (empty)
+NET "I_FX2_FLAG<3>" LOC = "b2"   | IOSTANDARD=LVCMOS33;   ## flag d (slcs)
+##
--- a/rtl/bplib/atlys/atlys_time_fx2_ic.ucf
+++ b/rtl/bplib/atlys/atlys_time_fx2_ic.ucf
@@ -0,0 +1,17 @@
+## $Id: atlys_time_fx2_ic.ucf 471 2013-01-05 19:46:38Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2013-01-05   471   1.0    Initial version (copied from nexys3)
+##
+## timing rules for a 30 MHz internal clock design:
+##   Period:   30 MHz
+##   clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
+##               clk->out < 33.3-18.7 = 14.6 ns
+##               --> use 10 ns
+##
+
+NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
+TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
+OFFSET =  IN  2 ns BEFORE "I_FX2_IFCLK";
+OFFSET = OUT 10 ns  AFTER "I_FX2_IFCLK";
--- a/rtl/bplib/bpgen/bpgenlib.vhd
+++ b/rtl/bplib/bpgen/bpgenlib.vhd
@@ -1,6 +1,6 @@
-- $Id: bpgenlib.vhd 426 2011-11-18 18:14:08Z mueller $
+-- $Id: bpgenlib.vhd 472 2013-01-06 14:39:10Z mueller $
 --
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
 -- Description:    Generic Board/Part components
 -- 
 -- Dependencies:   -
-- Tool versions:  12.1; ghdl 0.26-0.29
+-- Tool versions:  12.1, 13.3; ghdl 0.26-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2013-01-06   472   1.0.7  add sn_humanio_demu_rbus
 -- 2011-11-16   426   1.0.6  now numeric_std clean
 -- 2011-10-10   413   1.0.5  add sn_humanio_demu
 -- 2011-08-07   404   1.0.4  add RELAY generic for bp_rs232_2l4l_iob
@@ -197,4 +198,25 @@ component sn_humanio_rbus is            -- human i/o handling /w rbus intercept
  );
 end component;

+component sn_humanio_demu_rbus is       -- human i/o swi,btn,led only /w rbus
+  generic (
+    DEBOUNCE : boolean := true;         -- instantiate debouncer for SWI,BTN
+    RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
+  port (
+    CLK : in slbit;                     -- clock
+    RESET : in slbit := '0';            -- reset
+    CE_MSEC : in slbit;                 -- 1 ms clock enable
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    SWI : out slv8;                     -- switch settings, debounced
+    BTN : out slv4;                     -- button settings, debounced
+    LED : in slv8;                      -- led data
+    DSP_DAT : in slv16;                 -- display data
+    DSP_DP : in slv4;                   -- display decimal points
+    I_SWI : in slv8;                    -- pad-i: switches
+    I_BTN : in slv6;                    -- pad-i: buttons
+    O_LED : out slv8                    -- pad-o: leds
+  );
+end component;
+
 end package bpgenlib;
--- a/rtl/bplib/bpgen/sn_humanio_demu_rbus.vbom
+++ b/rtl/bplib/bpgen/sn_humanio_demu_rbus.vbom
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/rbus/rblib.vhd
+bpgenlib.vbom
+# components
+sn_humanio_demu.vbom
+# design
+sn_humanio_demu_rbus.vhd
--- a/rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd
+++ b/rtl/bplib/bpgen/sn_humanio_demu_rbus.vhd
@@ -0,0 +1,300 @@
+-- $Id: sn_humanio_demu_rbus.vhd 472 2013-01-06 14:39:10Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name:    sn_humanio_demu_rbus - syn
+-- Description:    sn_humanio_demu with rbus interceptor
+--
+-- Dependencies:   bpgen/sn_humanio_demu
+--
+-- Test bench:     -
+--
+-- Target Devices: generic
+-- Tool versions:  xst 13.3; ghdl 0.0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2013-01-06   472 13.3   O76xd xc3s1000-4   160  136    0  124 s  6.1 ns 
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-06   472   1.0    Initial version (cloned from sn_humanio_rbus
+------------------------------------------------------------------------------
+--
+-- rbus registers:
+--
+-- Address   Bits Name        r/w/f  Function
+-- bbbbbb00       cntl        r/w/-  Control register and BTN access
+--           x:08   btn       r/w/-    r: return hio BTN status
+--                                     w: ored with hio BTN to drive BTN
+--              3   dsp_en    r/w/-    if 1 display data will be driven by rbus
+--              2   dp_en     r/w/-    if 1 display dp's will be driven by rbus
+--              1   led_en    r/w/-    if 1 LED will be driven by rri
+--              0   swi_en    r/w/-    if 1 SWI will be driven by rri
+--
+-- bbbbbb01  7:00   swi       r/w/-    r: return hio SWI status
+--                                     w: will drive SWI when swi_en=1
+--
+-- bbbbbb10         led       r/w/-  Interface to LED and DSP_DP
+--          15:12     dp      r/w/-    r: returns DSP_DP status
+--                                     w: will drive display dp's when dp_en=1
+--           7:00     led     r/w/-    r: returns LED status
+--                                     w: will drive led's when led_en=1
+--
+-- bbbbbb11 15:00   dsp       r/w/-    r: return hio DSP_DAT status
+--                                     w: will drive DSP_DAT when dsp_en=1
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.rblib.all;
+use work.bpgenlib.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sn_humanio_demu_rbus is          -- human i/o swi,btn,led only /w rbus
+  generic (
+    DEBOUNCE : boolean := true;         -- instantiate debouncer for SWI,BTN
+    RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
+  port (
+    CLK : in slbit;                     -- clock
+    RESET : in slbit := '0';            -- reset
+    CE_MSEC : in slbit;                 -- 1 ms clock enable
+    RB_MREQ : in rb_mreq_type;          -- rbus: request
+    RB_SRES : out rb_sres_type;         -- rbus: response
+    SWI : out slv8;                     -- switch settings, debounced
+    BTN : out slv4;                     -- button settings, debounced
+    LED : in slv8;                      -- led data
+    DSP_DAT : in slv16;                 -- display data
+    DSP_DP : in slv4;                   -- display decimal points
+    I_SWI : in slv8;                    -- pad-i: switches
+    I_BTN : in slv6;                    -- pad-i: buttons
+    O_LED : out slv8                    -- pad-o: leds
+  );
+end sn_humanio_demu_rbus;
+
+architecture syn of sn_humanio_demu_rbus is
+
+  type regs_type is record
+    rbsel : slbit;                      -- rbus select
+    swi : slv8;                         -- rbus swi
+    btn : slv4;                         -- rbus btn
+    led : slv8;                         -- rbus led
+    dsp_dat : slv16;                    -- rbus dsp_dat
+    dsp_dp  : slv4;                     -- rbus dsp_dp
+    ledin : slv8;                       -- led from design
+    swieff : slv8;                      -- effective swi
+    btneff : slv4;                      -- effective btn
+    ledeff : slv8;                      -- effective led
+    dpeff : slv4;                       -- effective dsp_dp
+    dateff : slv16;                     -- effective dsp_dat
+    swi_en : slbit;                     -- enable: swi from rbus
+    led_en : slbit;                     -- enable: led from rbus
+    dsp_en : slbit;                     -- enable: dsp_dat from rbus
+    dp_en : slbit;                      -- enable: dsp_dp  from rbus
+  end record regs_type;
+
+  constant regs_init : regs_type := (
+    '0',                                -- rbsel
+    (others=>'0'),                      -- swi
+    (others=>'0'),                      -- btn
+    (others=>'0'),                      -- led
+    (others=>'0'),                      -- dsp_dat
+    (others=>'0'),                      -- dsp_dp
+    (others=>'0'),                      -- ledin
+    (others=>'0'),                      -- swieff
+    (others=>'0'),                      -- btneff
+    (others=>'0'),                      -- ledeff
+    (others=>'0'),                      -- dpeff
+    (others=>'0'),                      -- dateff
+    '0','0','0','0'                     -- (swi|led|dsp|dp)_en
+  );
+
+  signal R_REGS : regs_type := regs_init;  -- state registers
+  signal N_REGS : regs_type := regs_init;  -- next value state regs
+
+  subtype  cntl_rbf_btn      is integer range 11 downto 8;
+  constant cntl_rbf_dsp_en:  integer :=  3;
+  constant cntl_rbf_dp_en:   integer :=  2;
+  constant cntl_rbf_led_en:  integer :=  1;
+  constant cntl_rbf_swi_en:  integer :=  0;
+  subtype  led_rbf_dp      is integer range 15 downto 12;
+  subtype  led_rbf_led     is integer range  7 downto  0;
+
+  constant rbaddr_cntl:  slv2 := "00";  --  0    r/w/-
+  constant rbaddr_swi:   slv2 := "01";  --  1    r/w/-
+  constant rbaddr_led:   slv2 := "10";  --  2    r/w/-
+  constant rbaddr_dsp:   slv2 := "11";  --  3    r/w/-
+
+  signal HIO_SWI : slv8 := (others=>'0');
+  signal HIO_BTN : slv4 := (others=>'0');
+  signal HIO_LED : slv8 := (others=>'0');
+  signal HIO_DSP_DAT : slv16 := (others=>'0');
+  signal HIO_DSP_DP  : slv4 := (others=>'0');
+
+begin
+
+  HIO : sn_humanio_demu
+    generic map (
+      DEBOUNCE => DEBOUNCE)
+    port map (
+      CLK     => CLK,
+      RESET   => RESET,
+      CE_MSEC => CE_MSEC,
+      SWI     => HIO_SWI,                   
+      BTN     => HIO_BTN,                   
+      LED     => HIO_LED,                   
+      DSP_DAT => HIO_DSP_DAT,               
+      DSP_DP  => HIO_DSP_DP,
+      I_SWI   => I_SWI,                 
+      I_BTN   => I_BTN,
+      O_LED   => O_LED
+    );
+  
+  proc_regs: process (CLK)
+  begin
+
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        R_REGS <= regs_init;
+      else
+        R_REGS <= N_REGS;
+      end if;
+    end if;
+
+  end process proc_regs;
+  
+  proc_next: process (R_REGS, RB_MREQ, LED, DSP_DAT, DSP_DP,
+                      HIO_SWI, HIO_BTN, HIO_DSP_DAT, HIO_DSP_DP)
+
+    variable r : regs_type := regs_init;
+    variable n : regs_type := regs_init;
+
+    variable irb_ack  : slbit := '0';
+    variable irb_busy : slbit := '0';
+    variable irb_err  : slbit := '0';
+    variable irb_dout : slv16 := (others=>'0');
+    variable irbena   : slbit := '0';
+    
+  begin
+
+    r := R_REGS;
+    n := R_REGS;
+
+    irb_ack  := '0';
+    irb_busy := '0';
+    irb_err  := '0';
+    irb_dout := (others=>'0');
+
+    irbena  := RB_MREQ.re or RB_MREQ.we;
+
+    -- input register for LED signal
+    n.ledin  := LED;
+
+    -- rbus address decoder
+    n.rbsel := '0';
+    if RB_MREQ.aval='1' and RB_MREQ.addr(7 downto 2)=RB_ADDR(7 downto 2) then
+      n.rbsel := '1';
+    end if;
+
+    -- rbus transactions
+    if r.rbsel = '1' then
+      irb_ack := irbena;                  -- ack all accesses
+
+      case RB_MREQ.addr(1 downto 0) is
+
+        when rbaddr_cntl =>
+          irb_dout(cntl_rbf_btn)    := HIO_BTN;
+          irb_dout(cntl_rbf_dsp_en) := r.dsp_en;
+          irb_dout(cntl_rbf_dp_en)  := r.dp_en;
+          irb_dout(cntl_rbf_led_en) := r.led_en;
+          irb_dout(cntl_rbf_swi_en) := r.swi_en;
+          if RB_MREQ.we = '1' then
+            n.btn    := RB_MREQ.din(cntl_rbf_btn);
+            n.dsp_en := RB_MREQ.din(cntl_rbf_dsp_en);
+            n.dp_en  := RB_MREQ.din(cntl_rbf_dp_en);
+            n.led_en := RB_MREQ.din(cntl_rbf_led_en);
+            n.swi_en := RB_MREQ.din(cntl_rbf_swi_en);
+          end if;
+          
+        when rbaddr_swi =>
+          irb_dout(HIO_SWI'range) := HIO_SWI;
+          if RB_MREQ.we = '1' then
+            n.swi := RB_MREQ.din(n.swi'range);
+          end if;
+          
+        when rbaddr_led =>
+          irb_dout(led_rbf_dp)  := HIO_DSP_DP;
+          irb_dout(led_rbf_led) := r.ledin;
+          if RB_MREQ.we = '1' then
+            n.dsp_dp := RB_MREQ.din(led_rbf_dp);
+            n.led    := RB_MREQ.din(led_rbf_led);
+          end if;
+          
+        when rbaddr_dsp =>
+          irb_dout := HIO_DSP_DAT;
+          if RB_MREQ.we = '1' then
+            n.dsp_dat := RB_MREQ.din;
+          end if;
+
+        when others => null;
+      end case;
+
+    end if;
+
+    n.btneff := HIO_BTN or r.btn;
+    
+    if r.swi_en = '0' then
+      n.swieff := HIO_SWI;
+    else
+      n.swieff := r.swi;
+    end if;
+
+    if r.led_en = '0' then
+      n.ledeff := r.ledin;
+    else
+      n.ledeff := r.led;
+    end if;
+    
+    if r.dp_en = '0' then
+      n.dpeff  := DSP_DP;
+    else
+      n.dpeff  := r.dsp_dp;
+    end if;
+    
+    if r.dsp_en = '0' then
+      n.dateff := DSP_DAT;
+    else
+      n.dateff := r.dsp_dat;
+    end if;
+    
+    N_REGS       <= n;
+
+    BTN         <= R_REGS.btneff;
+    SWI         <= R_REGS.swieff;
+    HIO_LED     <= R_REGS.ledeff;
+    HIO_DSP_DP  <= R_REGS.dpeff;
+    HIO_DSP_DAT <= R_REGS.dateff;
+  
+    RB_SRES      <= rb_sres_init;
+    RB_SRES.ack  <= irb_ack;
+    RB_SRES.busy <= irb_busy;
+    RB_SRES.err  <= irb_err;
+    RB_SRES.dout <= irb_dout;
+
+  end process proc_next;
+
+end syn;
--- a/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd
+++ b/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd
@@ -1,6 +1,6 @@
-- $Id: fx2_2fifoctl_ic.vhd 453 2012-01-15 17:51:18Z mueller $
+-- $Id: fx2_2fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $
 --
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -27,11 +27,13 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
-- 2012-01-14   453  13.3   O76x xc3s1200e-4  101  173   64  159 s  8.3/7.4
+-- 2013-01-04   469  13.3   O76x xc3s1200e-4  112  172   64  169 s  7.4/7.4
+-- 2012-01-14   453  13.3   O76x xc3s1200e-4  101? 173   64  159 s  8.3/7.4
 -- 2012-01-08   451  13.3   O76x xc3s1200e-4  110  166   64  163 s  7.5
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2013-01-04   469   1.2    BUGFIX: redo rx logic, now properly pipelined
 -- 2012-01-15   453   1.1    use aempty/afull logic; collapse tx and pe flows
 -- 2012-01-09   451   1.0    Initial version
 -- 2012-01-01   448   0.5    First draft 
@@ -95,7 +97,7 @@ architecture syn of fx2_2fifoctl_ic is
    s_rxprep1,                          -- s_rxprep1: fifo addr setup
    s_rxprep2,                          -- s_rxprep2: wait for flags
    s_rxdisp,                           -- s_rxdisp: read, dispatch
-    s_rxpipe,                           -- s_rxpipe: read, pipe drain
+    s_rxpipe,                           -- s_rxpipe: read, pipe wait
    s_txprep0,                          -- s_txprep0: switch to tx-fifo
    s_txprep1,                          -- s_txprep1: fifo addr setup
    s_txprep2,                          -- s_txprep2: wait for flags
@@ -106,7 +108,8 @@ architecture syn of fx2_2fifoctl_ic is
    state : state_type;                 -- state
    petocnt : slv(PETOWIDTH-1 downto 0);  -- pktend time out counter
    pepend : slbit;                     -- pktend pending
-    rxpipe : slbit;                     -- read transaction in flight
+    rxpipe1 : slbit;                    -- read pipe 1: iob capture stage
+    rxpipe2 : slbit;                    -- read pipe 2: fifo write stage
    ccnt : slv(CCWIDTH-1 downto 0);     -- chunk counter
    moni_ep4_sel : slbit;               -- ep4 (rx) select
    moni_ep6_sel : slbit;               -- ep6 (tx) select
@@ -120,7 +123,8 @@ architecture syn of fx2_2fifoctl_ic is
  constant regs_init : regs_type := (
    s_idle,                             -- state
    petocnt_init,                       -- petocnt
-    '0','0',                            -- pepend,rxpipe
+    '0',                                -- pepend
+    '0','0',                            -- rxpipe1, rxpipe2
    ccnt_init,                          -- ccnt
    '0','0',                            -- moni_ep(4|6)_sel
    '0','0'                             -- moni_ep(4|6)_pf
@@ -313,8 +317,6 @@ begin
    variable idata_ceo : slbit := '0';
    variable idata_oe  : slbit := '0';

-    variable imoni  : fx2ctl_moni_type := fx2ctl_moni_init;
-
    variable slrxok : slbit := '0';
    variable sltxok : slbit := '0';
    variable pipeok : slbit := '0';
@@ -343,8 +345,6 @@ begin
    idata_ceo := '0';
    idata_oe  := '0';

-    imoni := fx2ctl_moni_init;
-    
    slrxok := FX2_FLAG_N(c_flag_rx_ef); -- empty flag is act.low!
    sltxok := FX2_FLAG_N(c_flag_tx_ff); --  full flag is act.low!
    pipeok := FX2_FLAG_N(c_flag_prog);  -- almost flag is act.low!
@@ -357,6 +357,8 @@ begin
      cc_done := '0';
    end if;

+    n.rxpipe1  := '0';
+    
    case r.state is
      when s_idle =>                    -- s_idle:
        if slrxok='1' and RXFIFO_BUSY='0' then
@@ -384,39 +386,37 @@ begin

      when s_rxdisp =>                  -- s_rxdisp: read, dispatch
        isloe := '1';
-        if r.rxpipe = '1' then            -- read in flight ?
-          irxfifo_ena := '1';               -- capture rxdata
-          n.rxpipe := '0';
-        end if;
-
        -- if chunk done and tx or pe pending and possible
        if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
-          n.state := s_txprep0;
+          if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
+            n.state := s_rxdisp;            -- wait
+          else
+            n.state := s_txprep0;           -- otherwise switch to tx flow
+          end if;
        -- if more rx to do and possible
-        elsif slrxok='1' and RXFIFO_BUSY='0' then
-          cc_cnt := '1';
-          idata_cei := '1';
+        elsif slrxok='1' and unsigned(RXSIZE_FX2)>3 then  -- !thres must be >3!
          islrd := '1';
-          if false and pipeok='1' and unsigned(RXSIZE_FX2)>2 then
-            n.rxpipe := '1';
-            n.state := s_rxdisp;
+          cc_cnt := '1';
+          n.rxpipe1 := '1';
+          if pipeok='1' then
+            n.state := s_rxdisp;             -- 1 cycle read
+            --n.state := s_rxprep2;            -- 2 cycle read
          else
            n.state := s_rxpipe;
-          end if;          
+          end if;
        -- otherwise back to idle
        else
-          n.state  := s_idle;
+          if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
+            n.state := s_rxdisp;            -- wait
+          else
+            n.state := s_idle;              -- to idle
+          end if;
        end if;

-      when s_rxpipe =>                  -- s_rxpipe:  read, pipe drain
+      when s_rxpipe =>                  -- s_rxpipe:  read, pipe wait
        isloe := '1';
-        irxfifo_ena := '1';               -- capture rxdata
-        if pipeok='1' and unsigned(RXSIZE_FX2)>1 then
-          n.state := s_rxdisp;
-        else
-          n.state := s_rxprep2;
-        end if;
-
+        n.state := s_rxprep2;
+        
      when s_txprep0 =>                 -- s_txprep0: switch to tx-fifo
        ififo_ce := '1';
        ififo    := c_txfifo;
@@ -459,6 +459,11 @@ begin
      when others => null;
    end case;

+    -- rx pipe handling
+    idata_cei   := r.rxpipe1;
+    n.rxpipe2   := r.rxpipe1;
+    irxfifo_ena := r.rxpipe2;
+    
    -- chunk counter handling
    if cc_clr = '1' then
      n.ccnt := (others=>'1');
--- a/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd
+++ b/rtl/bplib/fx2lib/fx2_3fifoctl_ic.vhd
@@ -1,6 +1,6 @@
-- $Id: fx2_3fifoctl_ic.vhd 453 2012-01-15 17:51:18Z mueller $
+-- $Id: fx2_3fifoctl_ic.vhd 472 2013-01-06 14:39:10Z mueller $
 --
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -27,10 +27,12 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri
+-- 2012-01-15   453  13.3   O76x xc3s1200e-4  157  265   96  243 s  7.7/7.4
 -- 2012-01-15   453  13.3   O76x xc3s1200e-4  156  259   96  238 s  7.9/7.5
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2013-01-04   469   1.1    BUGFIX: redo rx logic, now properly pipelined
 -- 2012-01-09   453   1.0    Initial version (derived from 2fifo_ic)
 --
 ------------------------------------------------------------------------------
@@ -98,7 +100,7 @@ architecture syn of fx2_3fifoctl_ic is
    s_rxprep1,                          -- s_rxprep1: fifo addr setup
    s_rxprep2,                          -- s_rxprep2: wait for flags
    s_rxdisp,                           -- s_rxdisp: read, dispatch
-    s_rxpipe,                           -- s_rxpipe: read, pipe drain
+    s_rxpipe,                           -- s_rxpipe: read, pipe wait
    s_txprep0,                          -- s_txprep0: switch to tx-fifo
    s_txprep1,                          -- s_txprep1: fifo addr setup
    s_txprep2,                          -- s_txprep2: wait for flags
@@ -115,7 +117,8 @@ architecture syn of fx2_3fifoctl_ic is
    pe2tocnt : slv(PETOWIDTH-1 downto 0); -- pktend 2 time out counter
    pepend : slbit;                     -- pktend 1 pending
    pe2pend : slbit;                    -- pktend 2 pending
-    rxpipe : slbit;                     -- read transaction in flight
+    rxpipe1 : slbit;                    -- read pipe 1: iob capture stage
+    rxpipe2 : slbit;                    -- read pipe 2: fifo write stage
    ccnt : slv(CCWIDTH-1 downto 0);     -- chunk counter
    moni_ep4_sel : slbit;               -- ep4 (rx) select
    moni_ep6_sel : slbit;               -- ep6 (tx) select
@@ -132,7 +135,8 @@ architecture syn of fx2_3fifoctl_ic is
    s_idle,                             -- state
    petocnt_init,                       -- petocnt
    petocnt_init,                       -- pe2tocnt
-    '0','0','0',                        -- pepend,pe2pend,rxpipe
+    '0','0',                            -- pepend,pe2pend
+    '0','0',                            -- rxpipe1, rxpipe2
    ccnt_init,                          -- ccnt
    '0','0','0',                        -- moni_ep(4|6|8)_sel
    '0','0','0'                         -- moni_ep(4|6|8)_pf
@@ -355,8 +359,6 @@ begin
    variable idata_oe  : slbit := '0';
    variable idata_do  : slv8 := (others=>'0');

-    variable imoni  : fx2ctl_moni_type := fx2ctl_moni_init;
-
    variable slrxok  : slbit := '0';
    variable sltxok  : slbit := '0';
    variable sltx2ok : slbit := '0';
@@ -388,8 +390,6 @@ begin
    idata_oe  := '0';
    idata_do  := TXFIFO_DO;

-    imoni := fx2ctl_moni_init;
-    
    slrxok  := FX2_FLAG_N(c_flag_rx_ef);  -- empty flag is act.low!
    sltxok  := FX2_FLAG_N(c_flag_tx_ff);  --  full flag is act.low!
    sltx2ok := FX2_FLAG_N(c_flag_tx2_ff); --  full flag is act.low!
@@ -402,6 +402,8 @@ begin
    else
      cc_done := '0';
    end if;
+    
+    n.rxpipe1  := '0';

    case r.state is
      when s_idle =>                    -- s_idle:
@@ -434,42 +436,44 @@ begin

      when s_rxdisp =>                  -- s_rxdisp: read, dispatch
        isloe := '1';
-        if r.rxpipe = '1' then            -- read in flight ?
-          irxfifo_ena := '1';               -- capture rxdata
-          n.rxpipe := '0';
-        end if;
-
        -- if chunk done and tx or pe pending and possible
        if cc_done='1' and sltxok='1' and (TXFIFO_VAL='1' or r.pepend='1') then
-          n.state := s_txprep0;
+          if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
+            n.state := s_rxdisp;            -- wait
+          else
+            n.state := s_txprep0;           -- otherwise switch to tx flow
+          end if;
        -- if chunk done and tx2 or pe2 pending and possible
        elsif cc_done='1' and sltx2ok='1' and (TX2FIFO_VAL='1' or r.pe2pend='1')
        then
-          n.state := s_tx2prep0;
+          if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
+            n.state := s_rxdisp;            -- wait
+          else
+            n.state := s_tx2prep0;
+          end if;
        -- if more rx to do and possible
-        elsif slrxok='1' and RXFIFO_BUSY='0' then
-          cc_cnt := '1';
-          idata_cei := '1';
+        elsif slrxok='1' and unsigned(RXSIZE_FX2)>3 then  -- !thres must be >3!
          islrd := '1';
-          if false and pipeok='1' and unsigned(RXSIZE_FX2)>2 then
-            n.rxpipe := '1';
-            n.state := s_rxdisp;
+          cc_cnt := '1';
+          n.rxpipe1 := '1';
+          if pipeok='1' then
+            n.state := s_rxdisp;             -- 1 cycle read
+            --n.state := s_rxprep2;            -- 2 cycle read
          else
            n.state := s_rxpipe;
-          end if;          
+          end if;
        -- otherwise back to idle
        else
-          n.state  := s_idle;
+          if r.rxpipe1='1' or r.rxpipe2='1' then -- rx pipe busy ?
+            n.state := s_rxdisp;            -- wait
+          else
+            n.state := s_idle;              -- to idle
+          end if;
        end if;

-      when s_rxpipe =>                  -- s_rxpipe:  read, pipe drain
+      when s_rxpipe =>                  -- s_rxpipe:  read, pipe wait
        isloe := '1';
-        irxfifo_ena := '1';               -- capture rxdata
-        if pipeok='1' and unsigned(RXSIZE_FX2)>1 then
-          n.state := s_rxdisp;
-        else
-          n.state := s_rxprep2;
-        end if;
+        n.state := s_rxprep2;

      when s_txprep0 =>                 -- s_txprep0: switch to tx-fifo
        ififo_ce := '1';
@@ -562,6 +566,11 @@ begin
      when others => null;
    end case;

+    -- rx pipe handling
+    idata_cei   := r.rxpipe1;
+    n.rxpipe2   := r.rxpipe1;
+    irxfifo_ena := r.rxpipe2;
+    
    -- chunk counter handling
    if cc_clr = '1' then
      n.ccnt := (others=>'1');
--- a/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vbom
+++ b/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vbom
@@ -0,0 +1,9 @@
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/simlib/simlib.vhd
+../fx2lib.vhd
+../../../vlib/memlib/memlib.vhd
+# components
+../../../vlib/memlib/fifo_2c_dram.vbom
+# design
+fx2_2fifo_core.vhd
--- a/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd
+++ b/rtl/bplib/fx2lib/tb/fx2_2fifo_core.vhd
@@ -0,0 +1,277 @@
+-- $Id: fx2_2fifo_core.vhd 469 2013-01-05 12:29:44Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    fx2_2fifo_core - sim
+-- Description:    Cypress EZ-USB FX2 (2 fifo core model)
+--
+-- Dependencies:   memlib/fifo_2c_dram
+-- Test bench:     -
+-- Target Devices: generic
+-- Tool versions:  xst 13.3; ghdl 0.29
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-04   469   1.0    Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.simbus.all;
+use work.fx2lib.all;
+use work.memlib.all;
+
+entity fx2_2fifo_core is                -- EZ-USB FX2 (2 fifo core model)
+  port (
+    CLK : in slbit;                     -- uplink clock
+    RESET : in slbit;                   -- reset
+    RXDATA : in slv8;                   -- rx data   (ext->fx2)
+    RXENA  : in slbit;                  -- rx enable
+    RXBUSY  : out slbit;                -- rx busy
+    TXDATA : out slv8;                  -- tx data   (fx2->ext)
+    TXVAL  : out slbit;                 -- tx valid
+    IFCLK : out slbit;                  -- fx2 interface clock
+    FIFO : in slv2;                     -- fx2 fifo address
+    FLAG : out slv4;                    -- fx2 fifo flags
+    SLRD_N : in slbit;                  -- fx2 read enable    (act.low)
+    SLWR_N : in slbit;                  -- fx2 write enable   (act.low)
+    SLOE_N : in slbit;                  -- fx2 output enable  (act.low)
+    PKTEND_N : in slbit;                -- fx2 packet end     (act.low)
+    DATA : inout slv8                   -- fx2 data lines
+  );
+end fx2_2fifo_core;
+
+
+architecture sim of fx2_2fifo_core is
+  
+  constant c_rxfifo : slv2 := c_fifo_ep4;
+  constant c_txfifo : slv2 := c_fifo_ep6;
+
+  constant c_flag_prog   : integer := 0;
+  constant c_flag_tx_ff  : integer := 1;
+  constant c_flag_rx_ef  : integer := 2;
+  constant c_flag_tx2_ff : integer := 3;
+
+  constant bufsize : positive := 1024;
+  constant datzero : slv(DATA'range) := (others=>'0');
+  type buf_type is array (0 to bufsize-1) of slv(DATA'range);
+
+  signal CLK30 : slbit := '0';
+
+  signal RXFIFO_DO : slv8 := (others=>'0');
+  signal RXFIFO_VAL : slbit := '0';
+  signal RXFIFO_HOLD : slbit := '0';
+  signal TXFIFO_DI : slv8 := (others=>'0');
+  signal TXFIFO_ENA : slbit := '0';
+  signal TXFIFO_BUSY : slbit := '0';
+
+  signal R_FLAG : slv4 := (others=>'0');
+  signal R_DATA : slv8 := (others=>'0');
+
+  -- added for debug purposes
+  signal R_rxbuf_rind : natural := 0;
+  signal R_rxbuf_wind : natural := 0;
+  signal R_rxbuf_nbyt : natural := 0;
+  signal R_txbuf_rind : natural := 0;
+  signal R_txbuf_wind : natural := 0;
+  signal R_txbuf_nbyt : natural := 0;
+  
+begin
+
+  RXFIFO : fifo_2c_dram
+    generic map (
+      AWIDTH => 5,
+      DWIDTH => 8)
+    port map (
+      CLKW   => CLK,
+      CLKR   => CLK30,
+      RESETW => '0',
+      RESETR => '0',
+      DI     => RXDATA,
+      ENA    => RXENA,
+      BUSY   => RXBUSY,
+      DO     => RXFIFO_DO,
+      VAL    => RXFIFO_VAL,
+      HOLD   => RXFIFO_HOLD,
+      SIZEW  => open,
+      SIZER  => open
+    );
+
+  TXFIFO : fifo_2c_dram
+    generic map (
+      AWIDTH => 5,
+      DWIDTH => 8)
+    port map (
+      CLKW   => CLK30,
+      CLKR   => CLK,
+      RESETW => '0',
+      RESETR => '0',
+      DI     => TXFIFO_DI,
+      ENA    => TXFIFO_ENA,
+      BUSY   => TXFIFO_BUSY,
+      DO     => TXDATA,
+      VAL    => TXVAL,
+      HOLD   => '0',
+      SIZEW  => open,
+      SIZER  => open
+    );
+
+  proc_ifclk: process
+    constant offset : time := 200 ns;
+    constant halfperiod_7 : time := 16700 ps;
+    constant halfperiod_6 : time := 16600 ps;
+  begin
+
+    CLK30 <= '0';
+    wait for offset;
+
+    clk_loop: loop
+      CLK30 <= '1';
+      wait for halfperiod_7;
+      CLK30 <= '0';
+      wait for halfperiod_7;
+      CLK30 <= '1';
+      wait for halfperiod_6;
+      CLK30 <= '0';
+      wait for halfperiod_7;
+      CLK30 <= '1';
+      wait for halfperiod_7;
+      CLK30 <= '0';
+      wait for halfperiod_6;
+      exit clk_loop when to_x01(SB_CLKSTOP) = '1';
+    end loop;    
+    
+    wait;                               -- endless wait, simulator will stop
+    
+  end process proc_ifclk;
+
+  proc_state: process (CLK30)
+    variable rxbuf : buf_type := (others=>datzero);
+    variable rxbuf_rind : natural := 0;
+    variable rxbuf_wind : natural := 0;
+    variable rxbuf_nbyt : natural := 0;
+
+    variable txbuf : buf_type := (others=>datzero);
+    variable txbuf_rind : natural := 0;
+    variable txbuf_wind : natural := 0;
+    variable txbuf_nbyt : natural := 0;
+
+    variable oline : line;
+
+  begin
+
+    if rising_edge(CLK30) then
+
+      RXFIFO_HOLD <= '0';
+      TXFIFO_ENA  <= '0';
+
+      -- rxfifo -> rxbuf
+      if RXFIFO_VAL = '1' then
+        if rxbuf_nbyt < bufsize then
+          rxbuf(rxbuf_wind) := RXFIFO_DO;
+          rxbuf_wind := (rxbuf_wind + 1) mod bufsize;
+          rxbuf_nbyt := rxbuf_nbyt + 1;
+        else
+          RXFIFO_HOLD <= '1';
+        end if;
+      end if;
+
+      -- txbuf -> txfifo
+      if txbuf_nbyt>0 and TXFIFO_BUSY='0' then
+        TXFIFO_DI  <= txbuf(txbuf_rind);
+        TXFIFO_ENA <= '1';
+        txbuf_rind := (txbuf_rind + 1) mod bufsize;
+        txbuf_nbyt := txbuf_nbyt - 1;
+      end if;
+
+      -- slrd cycle: rxbuf -> data
+      if SLRD_N = '0' then
+        if rxbuf_nbyt > 0 then
+          rxbuf_rind := (rxbuf_rind + 1) mod bufsize;
+          rxbuf_nbyt := rxbuf_nbyt - 1;
+        else
+          write(oline, string'("fx2_2fifo_core: SLRD_N=0 when rxbuf empty"));
+          writeline(output, oline);
+        end if;
+      end if;
+      R_DATA <= rxbuf(rxbuf_rind);
+      
+      -- slwr cycle: data -> txbuf
+      if SLWR_N = '0' then
+        if txbuf_nbyt < bufsize then
+          txbuf(txbuf_wind) := DATA;
+          txbuf_wind := (txbuf_wind + 1) mod bufsize;
+          txbuf_nbyt := txbuf_nbyt + 1;
+        else
+          write(oline, string'("fx2_2fifo_core: SLWR_N=0 when txbuf full"));
+          writeline(output, oline);
+        end if;
+      end if;
+
+      -- prepare flags (note that FLAGs are act.low!)
+      R_FLAG <= (others=>'1');
+      --   FLAGA = indexed, PF
+      --     rx endpoint -> PF 'almost empty' at 3 bytes to go
+      if FIFO = c_rxfifo then
+        if rxbuf_nbyt < 4 then
+          R_FLAG(0) <= '0';
+        end if;
+      --     tx endpoint -> PF 'almost full' at 3 bytes to go
+      elsif FIFO = c_txfifo then
+        if txbuf_nbyt > bufsize-4 then
+          R_FLAG(0) <= '0';
+        end if;
+      end if;
+
+      --   FLAGB = EP6 FF
+      if txbuf_nbyt = bufsize then
+        R_FLAG(1) <= '0';
+      end if;
+
+      --   FLAGC = EP4 EF
+      if rxbuf_nbyt = 0 then
+        R_FLAG(2) <= '0';
+      end if;
+      
+      --   FLAGD = EP8 FF
+      R_FLAG(3) <= '1';
+
+      -- added for debug purposes
+      R_rxbuf_rind <= rxbuf_rind;
+      R_rxbuf_wind <= rxbuf_wind;
+      R_rxbuf_nbyt <= rxbuf_nbyt;
+      R_txbuf_rind <= txbuf_rind;
+      R_txbuf_wind <= txbuf_wind;
+      R_txbuf_nbyt <= txbuf_nbyt;
+      
+    end if;
+    
+  end process proc_state;
+
+  IFCLK <= CLK30;
+  FLAG  <= R_FLAG;
+
+  proc_data: process (SLOE_N, R_DATA)
+  begin
+    if SLOE_N = '1' then
+      DATA <= (others=>'Z');
+    else
+      DATA <= R_DATA;
+    end if;
+  end process proc_data;
+  
+end sim;
--- a/rtl/bplib/nexys2/tb/.cvsignore
+++ b/rtl/bplib/nexys2/tb/.cvsignore
@@ -1,2 +1,3 @@
 tb_nexys2_dummy
 tb_nexys2_fusp_dummy
+tb_nexys2_fusp_cuff_dummy
--- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
+++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
@@ -0,0 +1,26 @@
+# Not meant for direct top level usage. Used with 
+# tb_nexys2_fusp_cuff_(....)[_ssim].vbom and config
+# lines to generate the different cases.
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/rlink/rlinklib.vbom
+../../../vlib/rlink/tb/rlinktblib.vhd
+../../../vlib/serport/serport.vhd
+../../../vlib/xlib/xlib.vhd
+../nexys2lib.vhd
+../../../vlib/simlib/simlib.vhd
+../../../vlib/simlib/simbus.vhd
+${sys_conf := sys_conf_sim.vhd}
+# components
+../../../vlib/simlib/simclk.vbom
+../../../vlib/simlib/simclkcnt.vbom
+../../../vlib/rlink/tb/tbcore_rlink.vbom
+../../../vlib/xlib/dcm_sfs_gsim.vbom
+tb_nexys2_core.vbom
+../../../vlib/serport/serport_uart_rxtx.vbom
+../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
+${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom}
+# design
+tb_nexys2_fusp_cuff.vhd
+@top:tb_nexys2_fusp_cuff
--- a/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
+++ b/rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
@@ -0,0 +1,329 @@
+-- $Id: tb_nexys2_fusp_cuff.vhd 469 2013-01-05 12:29:44Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    tb_nexys2_fusp_cuff - sim
+-- Description:    Test bench for nexys2 (base+fusp+cuff)
+--
+-- Dependencies:   simlib/simclk
+--                 simlib/simclkcnt
+--                 xlib/dcm_sfs
+--                 rlink/tb/tbcore_rlink_dcm
+--                 tb_nexys2_core
+--                 serport/serport_uart_rxtx
+--                 fx2lib/tb/fx2_2fifo_core
+--                 nexys2_fusp_aif [UUT]
+--
+-- To test:        generic, any nexys2_fusp_cuff_aif target
+--
+-- Target Devices: generic
+-- Tool versions:  xst 13.3; ghdl 0.29
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-03   469   1.1    add fx2 model and data path
+-- 2013-01-01   467   1.0    Initial version (derived from tb_nexys2_fusp)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.rlinklib.all;
+use work.rlinktblib.all;
+use work.serport.all;
+use work.xlib.all;
+use work.nexys2lib.all;
+use work.simlib.all;
+use work.simbus.all;
+use work.sys_conf.all;
+
+entity tb_nexys2_fusp_cuff is
+end tb_nexys2_fusp_cuff;
+
+architecture sim of tb_nexys2_fusp_cuff is
+  
+  signal CLKOSC : slbit := '0';
+  signal CLKCOM : slbit := '0';
+
+  signal CLK_STOP : slbit := '0';
+  signal CLKCOM_CYCLE : integer := 0;
+
+  signal RESET : slbit := '0';
+  signal CLKDIV : slv2 := "00";         -- run with 1 clocks / bit !!
+
+  signal TBC_RXDATA : slv8 := (others=>'0');
+  signal TBC_RXVAL  : slbit := '0';
+  signal TBC_RXHOLD : slbit := '0';
+  signal TBC_TXDATA : slv8 := (others=>'0');
+  signal TBC_TXENA  : slbit := '0';
+
+  signal UART_RXDATA : slv8 := (others=>'0');
+  signal UART_RXVAL  : slbit := '0';
+  signal UART_RXERR  : slbit := '0';
+  signal UART_RXACT  : slbit := '0';
+  signal UART_TXDATA : slv8 := (others=>'0');
+  signal UART_TXENA  : slbit := '0';
+  signal UART_TXBUSY : slbit := '0';
+
+  signal FX2_RXDATA : slv8 := (others=>'0');
+  signal FX2_RXENA : slbit := '0';
+  signal FX2_RXBUSY : slbit := '0';
+  signal FX2_TXDATA : slv8 := (others=>'0');
+  signal FX2_TXVAL : slbit := '0';
+
+  signal I_RXD : slbit := '1';
+  signal O_TXD : slbit := '1';
+  signal I_SWI : slv8 := (others=>'0');
+  signal I_BTN : slv4 := (others=>'0');
+  signal O_LED : slv8 := (others=>'0');
+  signal O_ANO_N : slv4 := (others=>'0');
+  signal O_SEG_N : slv8 := (others=>'0');
+
+  signal O_MEM_CE_N  : slbit := '1';
+  signal O_MEM_BE_N  : slv2 := (others=>'1');
+  signal O_MEM_WE_N  : slbit := '1';
+  signal O_MEM_OE_N  : slbit := '1';
+  signal O_MEM_ADV_N : slbit := '1';
+  signal O_MEM_CLK   : slbit := '0';
+  signal O_MEM_CRE   : slbit := '0';
+  signal I_MEM_WAIT  : slbit := '0';
+  signal O_MEM_ADDR  : slv23 := (others=>'Z');
+  signal IO_MEM_DATA : slv16 := (others=>'0');
+  signal O_FLA_CE_N  : slbit := '0';
+
+  signal O_FUSP_RTS_N : slbit := '0';
+  signal I_FUSP_CTS_N : slbit := '0';
+  signal I_FUSP_RXD : slbit := '1';
+  signal O_FUSP_TXD : slbit := '1';
+
+  signal I_FX2_IFCLK : slbit := '0';
+  signal O_FX2_FIFO : slv2 := (others=>'0');
+  signal I_FX2_FLAG : slv4 := (others=>'0');
+  signal O_FX2_SLRD_N : slbit := '1';
+  signal O_FX2_SLWR_N : slbit := '1';
+  signal O_FX2_SLOE_N : slbit := '1';
+  signal O_FX2_PKTEND_N : slbit := '1';
+  signal IO_FX2_DATA : slv8 := (others=>'Z');
+  
+  signal UART_RESET : slbit := '0';
+  signal UART_RXD : slbit := '1';
+  signal UART_TXD : slbit := '1';
+  signal CTS_N : slbit := '0';
+  signal RTS_N : slbit := '0';
+
+  signal R_PORTSEL_SER : slbit := '0';       -- if 1 use alternate serport
+  signal R_PORTSEL_FX2 : slbit := '0';       -- if 1 use fx2
+
+  constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
+
+  constant clock_period : time :=  20 ns;
+  constant clock_offset : time := 200 ns;
+
+begin
+  
+  CLKGEN : simclk
+    generic map (
+      PERIOD => clock_period,
+      OFFSET => clock_offset)
+    port map (
+      CLK      => CLKOSC,
+      CLK_STOP => CLK_STOP
+    );
+
+  SB_CLKSTOP <= CLK_STOP;
+  
+  DCM_COM : dcm_sfs
+    generic map (
+      CLKFX_DIVIDE   => sys_conf_clkfx_divide,
+      CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
+      CLKIN_PERIOD   => 20.0)
+    port map (
+      CLKIN   => CLKOSC,
+      CLKFX   => CLKCOM,
+      LOCKED  => open
+    );
+
+  CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
+
+  TBCORE : tbcore_rlink
+    port map (
+      CLK      => CLKCOM,
+      CLK_STOP => CLK_STOP,
+      RX_DATA  => TBC_RXDATA,
+      RX_VAL   => TBC_RXVAL,
+      RX_HOLD  => TBC_RXHOLD,
+      TX_DATA  => TBC_TXDATA,
+      TX_ENA   => TBC_TXENA
+    );
+
+  N2CORE : entity work.tb_nexys2_core
+    port map (
+      I_SWI       => I_SWI,
+      I_BTN       => I_BTN,
+      O_MEM_CE_N  => O_MEM_CE_N,
+      O_MEM_BE_N  => O_MEM_BE_N,
+      O_MEM_WE_N  => O_MEM_WE_N,
+      O_MEM_OE_N  => O_MEM_OE_N,
+      O_MEM_ADV_N => O_MEM_ADV_N,
+      O_MEM_CLK   => O_MEM_CLK,
+      O_MEM_CRE   => O_MEM_CRE,
+      I_MEM_WAIT  => I_MEM_WAIT,
+      O_MEM_ADDR  => O_MEM_ADDR,
+      IO_MEM_DATA => IO_MEM_DATA
+    );
+
+  UUT : nexys2_fusp_cuff_aif
+    port map (
+      I_CLK50      => CLKOSC,
+      I_RXD        => I_RXD,
+      O_TXD        => O_TXD,
+      I_SWI        => I_SWI,
+      I_BTN        => I_BTN,
+      O_LED        => O_LED,
+      O_ANO_N      => O_ANO_N,
+      O_SEG_N      => O_SEG_N,
+      O_MEM_CE_N   => O_MEM_CE_N,
+      O_MEM_BE_N   => O_MEM_BE_N,
+      O_MEM_WE_N   => O_MEM_WE_N,
+      O_MEM_OE_N   => O_MEM_OE_N,
+      O_MEM_ADV_N  => O_MEM_ADV_N,
+      O_MEM_CLK    => O_MEM_CLK,
+      O_MEM_CRE    => O_MEM_CRE,
+      I_MEM_WAIT   => I_MEM_WAIT,
+      O_MEM_ADDR   => O_MEM_ADDR,
+      IO_MEM_DATA  => IO_MEM_DATA,
+      O_FLA_CE_N   => O_FLA_CE_N,
+      O_FUSP_RTS_N => O_FUSP_RTS_N,
+      I_FUSP_CTS_N => I_FUSP_CTS_N,
+      I_FUSP_RXD   => I_FUSP_RXD,
+      O_FUSP_TXD   => O_FUSP_TXD,
+      I_FX2_IFCLK    => I_FX2_IFCLK,
+      O_FX2_FIFO     => O_FX2_FIFO,
+      I_FX2_FLAG     => I_FX2_FLAG,
+      O_FX2_SLRD_N   => O_FX2_SLRD_N,
+      O_FX2_SLWR_N   => O_FX2_SLWR_N,
+      O_FX2_SLOE_N   => O_FX2_SLOE_N,
+      O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+      IO_FX2_DATA    => IO_FX2_DATA
+    );
+
+  UART : serport_uart_rxtx
+    generic map (
+      CDWIDTH => CLKDIV'length)
+    port map (
+      CLK    => CLKCOM,
+      RESET  => UART_RESET,
+      CLKDIV => CLKDIV,
+      RXSD   => UART_RXD,
+      RXDATA => UART_RXDATA,
+      RXVAL  => UART_RXVAL,
+      RXERR  => UART_RXERR,
+      RXACT  => UART_RXACT,
+      TXSD   => UART_TXD,
+      TXDATA => UART_TXDATA,
+      TXENA  => UART_TXENA,
+      TXBUSY => UART_TXBUSY
+    );
+
+  FX2 : entity work.fx2_2fifo_core
+    port map (
+      CLK      => CLKCOM,
+      RESET    => '0',
+      RXDATA   => FX2_RXDATA,
+      RXENA    => FX2_RXENA,
+      RXBUSY   => FX2_RXBUSY,
+      TXDATA   => FX2_TXDATA,
+      TXVAL    => FX2_TXVAL,
+      IFCLK    => I_FX2_IFCLK,
+      FIFO     => O_FX2_FIFO,
+      FLAG     => I_FX2_FLAG,
+      SLRD_N   => O_FX2_SLRD_N,
+      SLWR_N   => O_FX2_SLWR_N,
+      SLOE_N   => O_FX2_SLOE_N,
+      PKTEND_N => O_FX2_PKTEND_N,
+      DATA     => IO_FX2_DATA
+    );
+
+  proc_fx2_mux: process (R_PORTSEL_FX2, TBC_RXDATA, TBC_RXVAL,
+                         UART_TXBUSY, RTS_N, UART_RXDATA, UART_RXVAL,
+                         FX2_RXBUSY, FX2_TXDATA, FX2_TXVAL
+                         )
+  begin
+
+    if R_PORTSEL_FX2 = '0' then         -- use serport
+      UART_TXDATA <= TBC_RXDATA;
+      UART_TXENA  <= TBC_RXVAL;
+      TBC_RXHOLD  <= UART_TXBUSY or RTS_N;
+      TBC_TXDATA  <= UART_RXDATA;
+      TBC_TXENA   <= UART_RXVAL;
+    else                                -- otherwise use fx2
+      FX2_RXDATA  <= TBC_RXDATA;
+      FX2_RXENA   <= TBC_RXVAL;
+      TBC_RXHOLD  <= FX2_RXBUSY;
+      TBC_TXDATA  <= FX2_TXDATA;
+      TBC_TXENA   <= FX2_TXVAL;
+    end if;
+    
+  end process proc_fx2_mux;
+
+  proc_ser_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
+                         O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
+  begin
+
+    if R_PORTSEL_SER = '0' then         -- use main board rs232, no flow cntl
+      I_RXD        <= UART_TXD;           -- write port 0 inputs
+      UART_RXD     <= O_TXD;              -- get port 0 outputs
+      RTS_N        <= '0';
+      I_FUSP_RXD   <= '1';                -- port 1 inputs to idle state
+      I_FUSP_CTS_N <= '0';
+    else                                -- otherwise use pmod1 rs232
+      I_FUSP_RXD   <= UART_TXD;           -- write port 1 inputs
+      I_FUSP_CTS_N <= CTS_N;
+      UART_RXD     <= O_FUSP_TXD;         -- get port 1 outputs
+      RTS_N        <= O_FUSP_RTS_N;
+      I_RXD        <= '1';                -- port 0 inputs to idle state
+    end if;
+    
+  end process proc_ser_mux;
+
+  proc_moni: process
+    variable oline : line;
+  begin
+    
+    loop
+      wait until rising_edge(CLKCOM);
+
+      if UART_RXERR = '1' then
+        writetimestamp(oline, CLKCOM_CYCLE, " : seen UART_RXERR=1");
+        writeline(output, oline);
+      end if;
+      
+    end loop;
+    
+  end process proc_moni;
+
+  proc_simbus: process (SB_VAL)
+  begin
+    if SB_VAL'event and to_x01(SB_VAL)='1' then
+      if SB_ADDR = sbaddr_portsel then
+        R_PORTSEL_SER <= to_x01(SB_DATA(0));
+        R_PORTSEL_FX2 <= to_x01(SB_DATA(1));
+      end if;
+    end if;
+  end process proc_simbus;
+
+end sim;
--- a/rtl/bplib/nexys3/nexys3_pins_fx2.ucf
+++ b/rtl/bplib/nexys3/nexys3_pins_fx2.ucf
@@ -0,0 +1,38 @@
+## $Id: nexys3_pins_fx2.ucf 455 2012-01-24 09:11:25Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2012-01-23   455   1.2    fix SLOE_N (h4->h6)
+## 2012-01-01   448   1.1    use 12/FAST instead of 6/SLOW for _DATA<*>
+## 2011-11-27   433   1.0    Initial version 
+##
+## Cypress EZ-USB FX2 Interface -- in Bank 3 ---------------------------------
+##
+##
+NET "I_FX2_IFCLK" LOC = "h2"     | IOSTANDARD=LVCMOS33;
+## 
+NET "IO_FX2_DATA<0>" LOC = "e1"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<1>" LOC = "f4"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<2>" LOC = "f3"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<3>" LOC = "d2"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<4>" LOC = "d1"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<5>" LOC = "h7"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<6>" LOC = "g6"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<7>" LOC = "e4"  | IOSTANDARD=LVCMOS33;
+NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER;
+##
+NET "O_FX2_SLWR_N" LOC = "c1"    | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_SLRD_N" LOC = "c2"    | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_SLOE_N" LOC = "h6"    | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_FX2_PKTEND_N" LOC = "d3"  | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+NET "O_FX2_FIFO<0>" LOC = "h5"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+NET "O_FX2_FIFO<1>" LOC = "e3"   | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
+##
+## assume that PA.7 is used as FLAGD (and not as SLCS#)
+NET "I_FX2_FLAG<0>" LOC = "h1"   | IOSTANDARD=LVCMOS33;   ## flag a (program)
+NET "I_FX2_FLAG<1>" LOC = "k4"   | IOSTANDARD=LVCMOS33;   ## flag b (full)
+NET "I_FX2_FLAG<2>" LOC = "f5"   | IOSTANDARD=LVCMOS33;   ## flag c (empty)
+NET "I_FX2_FLAG<3>" LOC = "f6"   | IOSTANDARD=LVCMOS33;   ## flag d (slcs)
+##
--- a/rtl/bplib/nexys3/nexys3_time_fx2_ic.ucf
+++ b/rtl/bplib/nexys3/nexys3_time_fx2_ic.ucf
@@ -0,0 +1,17 @@
+## $Id: nexys3_time_fx2_ic.ucf 448 2012-01-02 21:55:11Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2012-01-01   448   1.0    Initial version
+##
+## timing rules for a 30 MHz internal clock design:
+##   Period:   30 MHz
+##   clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
+##               clk->out < 33.3-18.7 = 14.6 ns
+##               --> use 10 ns
+##
+
+NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
+TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
+OFFSET =  IN  2 ns BEFORE "I_FX2_IFCLK";
+OFFSET = OUT 10 ns  AFTER "I_FX2_IFCLK";
--- a/rtl/make/generic_xflow.mk
+++ b/rtl/make/generic_xflow.mk
@@ -1,7 +1,8 @@
-# $Id: generic_xflow.mk 456 2012-02-05 22:19:44Z mueller $
+# $Id: generic_xflow.mk 470 2013-01-05 17:28:46Z mueller $
 #
 #  Revision History: 
 # Date         Rev Version  Comment
+# 2013-01-05   470   1.7.6  remove '-r' from all non-dir clean rm's
 # 2012-02-05   456   1.7.5  use vbomvonv --get_top for xflow calls
 # 2012-01-08   451   1.7.4  use xilinx_ghdl_sdf_filter
 # 2012-01-04   450   1.7.3  display isemsg_filter for ncd and bit targets too
@@ -300,25 +301,25 @@ endif
 .PHONY : ise_clean ise_tmp_clean
 #
 ise_clean: ise_tmp_clean
-	rm -rf *.ngc
-	rm -rf *.ncd
-	rm -rf *.pcf
-	rm -rf *.bit
-	rm -rf *.msk
-	rm -rf *.svf
-	rm -rf *_[sft]sim.vhd
-	rm -rf *_tsim.sdf
-	rm -rf *_tsim.sdf_ghdl
-	rm -rf *_xst.log
-	rm -rf *_tra.log
-	rm -rf *_map.log
-	rm -rf *_par.log
-	rm -rf *_pad.log
-	rm -rf *_twr.log
-	rm -rf *_bgn.log
-	rm -rf *_ngn_[sft]sim.log
-	rm -rf *_svn.log
-	rm -rf *_sum.log
+	rm -f *.ngc
+	rm -f *.ncd
+	rm -f *.pcf
+	rm -f *.bit
+	rm -f *.msk
+	rm -f *.svf
+	rm -f *_[sft]sim.vhd
+	rm -f *_tsim.sdf
+	rm -f *_tsim.sdf_ghdl
+	rm -f *_xst.log
+	rm -f *_tra.log
+	rm -f *_map.log
+	rm -f *_par.log
+	rm -f *_pad.log
+	rm -f *_twr.log
+	rm -f *_bgn.log
+	rm -f *_ngn_[sft]sim.log
+	rm -f *_svn.log
+	rm -f *_sum.log
 #
 ise_tmp_clean:
 	rm -rf ./ise
--- a/rtl/make/generic_xflow_cpld.mk
+++ b/rtl/make/generic_xflow_cpld.mk
@@ -1,7 +1,8 @@
-# $Id: generic_xflow_cpld.mk 405 2011-08-14 08:16:28Z mueller $
+# $Id: generic_xflow_cpld.mk 470 2013-01-05 17:28:46Z mueller $
 #
 #  Revision History: 
 # Date         Rev Version  Comment
+# 2013-01-05   470   1.1.1  remove '-r' from all non-dir clean rm's
 # 2011-08-13   405   1.1    renamed, moved to rtl/make;
 # 2010-03-13   268   1.0    Initial version, cloned from .xflow Rev 252
 #---
@@ -116,14 +117,14 @@ XFLOW    = xflow -p ${ISE_PATH}
 .PHONY : ise_clean ise_tmp_clean
 #
 ise_clean: ise_tmp_clean
-	rm -rf *.ngc
-	rm -rf *.ncd
-	rm -rf *.jed
-	rm -rf *_xst.log
-	rm -rf *_tra.log
-	rm -rf *_fit.log
-	rm -rf *_tim.log
-	rm -rf *_pad.log
+	rm -f *.ngc
+	rm -f *.ncd
+	rm -f *.jed
+	rm -f *_xst.log
+	rm -f *_tra.log
+	rm -f *_fit.log
+	rm -f *_tim.log
+	rm -f *_pad.log
 #
 ise_tmp_clean:
 	rm -rf ./ise
--- a/rtl/sys_gen/tst_fx2loop/Makefile
+++ b/rtl/sys_gen/tst_fx2loop/Makefile
@@ -1,7 +1,8 @@
-# $Id: Makefile 461 2012-04-09 21:17:54Z mueller $
+# $Id: Makefile 470 2013-01-05 17:28:46Z mueller $
 #
 #  Revision History: 
 # Date         Rev Version  Comment
+# 2013-01-05   470   1.2    fix LDLIBS (must come after objs)
 # 2012-02-26   458   1.1    add tst_fx2loop_si
 # 2011-12-26   445   1.0    Initial version
 #
@@ -15,16 +16,19 @@ ISE_PATH = xc3s1200e-fg320-4
 all : tst_fx2loop tst_fx2loop_si
 #
 clean : ise_clean
+	rm -f tst_fx2loop
+	rm -f tst_fx2loop_si
 #
 realclean :
 	rm -f tst_fx2loop tst_fx2loop_si
 #
-CFLAGS = -Wall -O2 -g -lusb-1.0 
+CFLAGS = -Wall -O2 -g
+LDLIBS = -lusb-1.0
 #
 tst_fx2loop : tst_fx2loop.c
-	${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c
+	${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS}
 tst_fx2loop_si : tst_fx2loop_si.c
-	${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c
+	${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS}
 #
 #----
 #
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/.cvsignore
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/.cvsignore
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_rlink_cuff_ic_atlys.ucf
+*.dep_ucf_cpp
+*.svf
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile
@@ -0,0 +1,32 @@
+# $Id: Makefile 472 2013-01-06 14:39:10Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2013-01-06   472   1.0    Initial version
+#
+#
+VBOM_all  = $(wildcard *.vbom)
+BIT_all   = $(VBOM_all:.vbom=.bit)
+#
+ISE_BOARD = atlys
+ISE_PATH  = xc6slx45-csg324-2
+FX2_FILE  = nexys3_jtag_2fifo_ic.ihx
+#
+XFLOWOPT_SYN = syn_s6_speed.opt
+XFLOWOPT_IMP = imp_s6_speed.opt
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+	rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_conf.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_conf.vhd
@@ -0,0 +1,62 @@
+-- $Id: sys_conf.vhd 472 2013-01-06 14:39:10Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   sys_conf
+-- Description:    Definitions for sys_tst_rlink_cuff_ic_atlys (for synthesis)
+--
+-- Dependencies:   -
+-- Tool versions:  xst 13.3; ghdl 0.29
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-06   472   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+  constant sys_conf_clkfx_divide : positive   :=  1;
+  constant sys_conf_clkfx_multiply : positive :=  1;
+
+  constant sys_conf_ser2rri_defbaud : integer := 115200;   -- default 115k baud
+  constant sys_conf_hio_debounce : boolean := true;    -- instantiate debouncers
+
+  constant sys_conf_fx2_type : string := "ic2";
+
+  -- dummy values defs for generic parameters of as controller
+  constant sys_conf_fx2_rdpwldelay : positive := 1;
+  constant sys_conf_fx2_rdpwhdelay : positive := 1;
+  constant sys_conf_fx2_wrpwldelay : positive := 1;
+  constant sys_conf_fx2_wrpwhdelay : positive := 1;
+  constant sys_conf_fx2_flagdelay  : positive := 1;
+
+  -- pktend timer setting
+  --   petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
+  constant sys_conf_fx2_petowidth  : positive := 10;
+
+  constant sys_conf_fx2_ccwidth  : positive := 5;
+   
+  -- derived constants
+  
+  constant sys_conf_clksys : integer :=
+    (100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
+  constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+  constant sys_conf_ser2rri_cdinit : integer :=
+    (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
+
+end package sys_conf;
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset
@@ -0,0 +1,97 @@
+# $Id: sys_tst_rlink_cuff_ic_atlys.mfset 472 2013-01-06 14:39:10Z mueller $
+#
+# ----------------------------------------------------------------------------
+[xst]
+Case statement is complete. others clause is never selected
+Using initial value '0' for reset since it is never assigned
+Using initial value '0' for fx2_tx2ena_l since it is never assigned
+
+Net <FX2_TX2BUSY> does not have a driver.
+
+Output port <LOCKED> of the instance <DCM> is unconnected
+Output port <RXAEMPTY> of the instance <FX2_CNTL_IC.CNTL> is unconnected
+Output port <TXAFULL> of the instance <FX2_CNTL_IC.CNTL> is unconnected
+Output port <FX2_TX2DATA> of the instance <TST> is unconnected
+Output port <FX2_TX2ENA> of the instance <TST> is unconnected
+Output port <SIZER> of the instance <TXFIFO> is unconnected
+Output port <DOA> of the instance <RAM> is unconnected
+Output port <RL_MONI_eop> of the instance <RLCORE> is unconnected
+Output port <RL_MONI_attn> of the instance <RLCORE> is unconnected
+Output port <RL_MONI_lamp> of the instance <RLCORE> is unconnected
+Output port <MONI_rxerr> of the instance <SERPORT> is unconnected
+Output port <MONI_rxovr> of the instance <SERPORT> is unconnected
+Output port <MONI_abdone> of the instance <SERPORT> is unconnected
+Output port <SIZE> of the instance <TXFIFO> is unconnected or connected
+Output port <SIZE> of the instance <FIFO> is unconnected or connected
+Output port <DOB> of the instance <BRAM> is unconnected
+
+Signal <FX2_TX2DATA> is used but never assigned
+
+Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_atlys'
+
+Node <FX2_CNTL_IC.CNTL/R_MONI_[CS]_.*> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_sel> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_pf> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_pf> of sequential type is unconnected
+ode <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_sel> of sequential type is unconnected
+Node <IOB_FX2_FLAG/R_DI_3> of sequential type is unconnected
+Node <HIO/R_REGS_swieff_[3-7]> of sequential type is unconnected
+Node <HIO/R_REGS_btn_[0-4]> of sequential type is unconnected
+Node <HIO/R_REGS_swi_[3-7]> of sequential type is unconnected
+Node <HIO/R_REGS_btneff_[0-4]> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_size[rw]_\d> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS_monattn> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS_monlamp> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS_moneop> of sequential type is unconnected
+Node <TST/SERPORT/XONRX/R_REGS_rxovr> of sequential type is unconnected
+
+Input <RB_MREQ_init> is never used
+Input <RB_MREQ_din<15:10>> is never used
+Input <SWI<7:3>> is never used
+Input <SWI<0:0>> is never used
+Input <BTN<3:0>> is never used
+Input <FX2_MONI_fifo_ep4> is never used
+Input <FX2_MONI_fifo_ep6> is never used
+Input <FX2_MONI_fifo_ep8> is never used
+Input <FX2_MONI_flag_ep4_empty> is never used
+Input <FX2_MONI_flag_ep4_almost> is never used
+Input <FX2_MONI_flag_ep6_full> is never used
+Input <FX2_MONI_flag_ep6_almost> is never used
+Input <FX2_MONI_flag_ep8_full> is never used
+Input <FX2_MONI_flag_ep8_almost> is never used
+Input <FX2_MONI_slrd> is never used
+Input <FX2_MONI_slwr> is never used
+Input <FX2_MONI_pktend> is never used
+
+FF/Latch <R_MONI_[CS]_.*> has a constant value of 0
+FF/Latch <TX2ENA_PSTR/R_REGS_busy_1> has a constant value
+FF/Latch <TX2ENA_PSTR/R_REGS_busy_0> has a constant value
+
+of type RAMB16_S18 has been replaced by RAMB16BWER
+of type RAMB16_S36 has been replaced by RAMB16BWER
+of type RAMB16_S36_S36 has been replaced by RAMB16BWER
+
+FF/Latch <HIO/R_REGS_ledin_[2-6]> has a constant value of 0
+FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_rst.*> has a constant value
+
+The FF/Latch <R_REGS_rbre> .* is equivalent
+The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[01]> .* is equivalent
+
+#
+# ----------------------------------------------------------------------------
+[tra]
+
+#
+# ----------------------------------------------------------------------------
+[map]
+INFO:.*
+
+#
+# ----------------------------------------------------------------------------
+[par]
+The signal I_FX2_FLAG<3>_IBUF has no load
+There are 1 loadless signals in this design
+
+#
+# ----------------------------------------------------------------------------
+[bgn]
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.ucf_cpp
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.ucf_cpp
@@ -0,0 +1,24 @@
+## $Id: sys_tst_rlink_cuff_ic_atlys.ucf_cpp 472 2013-01-06 14:39:10Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2013-01-06   472   1.0    Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET =  IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns  AFTER "I_CLK100";
+
+## std board
+##
+#include "bplib/atlys/atlys_pins.ucf"
+##
+## Pmod A0 - RS232 
+##
+#include "bplib/atlys/atlys_pins_pma0_rs232.ucf"
+##
+## FX2 interface
+##
+#include "bplib/atlys/atlys_pins_fx2.ucf"
+#include "bplib/atlys/atlys_time_fx2_ic.ucf"
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.vbom
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.vbom
@@ -0,0 +1,8 @@
+# conf
+sys_conf = sys_conf.vhd
+# libs
+# components
+# design
+../sys_tst_rlink_cuff_atlys.vbom
+@ucf_cpp: sys_tst_rlink_cuff_ic_atlys.ucf
+@top: sys_tst_rlink_cuff_atlys
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom
@@ -0,0 +1,27 @@
+# this is the vbom for the 'generic' top level entity
+# to be referenced in the vbom's of the specific systems
+#   ./as/sys_tst_rlink_cuff_as_atlys
+#   ./ic/sys_tst_rlink_cuff_ic_atlys
+#   ./ic3/sys_tst_rlink_cuff_ic3_atlys
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../../../vlib/rbus/rblib.vhd
+../../../bplib/fx2lib/fx2lib.vhd
+${sys_conf}
+# components
+[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
+[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio_demu_rbus.vbom
+../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
+../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
+../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
+../tst_rlink_cuff.vbom
+# design
+sys_tst_rlink_cuff_atlys.vhd
+## no @ucf_cpp
--- a/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd
@@ -0,0 +1,346 @@
+-- $Id: sys_tst_rlink_cuff_atlys.vhd 472 2013-01-06 14:39:10Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name:    sys_tst_rlink_cuff_atlys - syn
+-- Description:    rlink tester design for atlys with fx2 interface
+--
+-- Dependencies:   vlib/xlib/dcm_sfs
+--                 vlib/genlib/clkdivce
+--                 bplib/bpgen/bp_rs232_2l4l_iob
+--                 bplib/bpgen/sn_humanio_rbus
+--                 bplib/fx2lib/fx2_2fifoctl_as   [sys_conf_fx2_type="as2"]
+--                 bplib/fx2lib/fx2_2fifoctl_ic   [sys_conf_fx2_type="ic2"]
+--                 bplib/fx2lib/fx2_3fifoctl_ic   [sys_conf_fx2_type="ic3"]
+--                 tst_rlink_cuff
+--
+-- Test bench:     -
+--
+-- Target Devices: generic
+-- Tool versions:  xst 13.3; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri ctl/MHz
+-- 2013-01-06   472 13.3    O76d xc6slx45     ???  ???? ??? ???? p ??.? ic2/100
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-06   472   1.0    Initial version; derived from sys_tst_rlink_cuff_n3
+--                           and sys_tst_fx2loop_atlys
+------------------------------------------------------------------------------
+-- Usage of Atlys Switches, Buttons, LEDs:
+--
+--    SWI(7:3)  no function (only connected to sn_humanio_rbus)
+--       (2)    0 -> int/ext RS242 port for rlink
+--              1 -> use USB interface for rlink
+--       (1)    1 enable XON
+--       (0)    0 -> main board RS232 port  - implemented in bp_rs232_2l4l_iob
+--              1 -> Pmod B/top RS232 port  /
+--
+--    LED(7)    SER_MONI.abact
+--       (6:2)  no function (only connected to sn_humanio_rbus)
+--       (0)    timer 0 busy 
+--       (1)    timer 1 busy 
+--
+--    DSP:      SER_MONI.clkdiv         (from auto bauder)
+--    for SWI(2)='0' (serport)
+--    DP(3)     not SER_MONI.txok       (shows tx back preasure)
+--      (2)     SER_MONI.txact          (shows tx activity)
+--      (1)     not SER_MONI.rxok       (shows rx back preasure)
+--      (0)     SER_MONI.rxact          (shows rx activity)
+--    for SWI(2)='1' (fx2)
+--    DP(3)     FX2_TX2BUSY             (shows tx2 back preasure)
+--      (2)     FX2_TX2ENA(stretched)   (shows tx2 activity)
+--      (1)     FX2_TXENA(streched)     (shows tx activity)
+--      (0)     FX2_RXVAL(stretched)    (shows rx activity)
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.rblib.all;
+use work.fx2lib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_rlink_cuff_atlys is      -- top level
+                                        -- implements atlys_fusp_cuff_aif
+  port (
+    I_CLK100 : in slbit;                -- 100 MHz clock
+    I_USB_RXD : in slbit;               -- USB UART receive data (board view)
+    O_USB_TXD : out slbit;              -- USB UART transmit data (board view)
+    I_HIO_SWI : in slv8;                -- atlys hio switches
+    I_HIO_BTN : in slv6;                -- atlys hio buttons
+    O_HIO_LED: out slv8;                -- atlys hio leds
+    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n
+    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n
+    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx
+    O_FUSP_TXD : out slbit;             -- fusp: rs232 tx
+    I_FX2_IFCLK : in slbit;             -- fx2: interface clock
+    O_FX2_FIFO : out slv2;              -- fx2: fifo address
+    I_FX2_FLAG : in slv4;               -- fx2: fifo flags
+    O_FX2_SLRD_N : out slbit;           -- fx2: read enable    (act.low)
+    O_FX2_SLWR_N : out slbit;           -- fx2: write enable   (act.low)
+    O_FX2_SLOE_N : out slbit;           -- fx2: output enable  (act.low)
+    O_FX2_PKTEND_N : out slbit;         -- fx2: packet end     (act.low)
+    IO_FX2_DATA : inout slv8            -- fx2: data lines
+  );
+end sys_tst_rlink_cuff_atlys;
+
+architecture syn of sys_tst_rlink_cuff_atlys is
+  
+  signal CLK :   slbit := '0';
+  signal RESET : slbit := '0';
+
+  signal CE_USEC :  slbit := '0';
+  signal CE_MSEC :  slbit := '0';
+  
+  signal RXSD  : slbit := '0';
+  signal TXSD  : slbit := '0';
+  signal CTS_N : slbit := '0';
+  signal RTS_N : slbit := '0';
+
+  signal SWI     : slv8  := (others=>'0');
+  signal BTN     : slv4  := (others=>'0');
+  signal LED     : slv8  := (others=>'0');  
+  signal DSP_DAT : slv16 := (others=>'0');
+  signal DSP_DP  : slv4  := (others=>'0');
+  
+  signal RB_MREQ : rb_mreq_type := rb_mreq_init;
+  signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
+
+  signal FX2_RXDATA   : slv8 := (others=>'0');
+  signal FX2_RXVAL    : slbit := '0';
+  signal FX2_RXHOLD   : slbit := '0';
+  signal FX2_RXAEMPTY : slbit := '0';
+  signal FX2_TXDATA   : slv8 := (others=>'0');
+  signal FX2_TXENA    : slbit := '0';
+  signal FX2_TXBUSY   : slbit := '0';
+  signal FX2_TXAFULL  : slbit := '0';
+  signal FX2_TX2DATA  : slv8 := (others=>'0');
+  signal FX2_TX2ENA   : slbit := '0';
+  signal FX2_TX2BUSY  : slbit := '0';
+  signal FX2_TX2AFULL : slbit := '0';
+  signal FX2_MONI  : fx2ctl_moni_type := fx2ctl_moni_init;
+
+  constant rbaddr_hio   : slv8 := "11000000"; -- 110000xx
+
+begin
+
+  assert (sys_conf_clksys mod 1000000) = 0
+    report "assert sys_conf_clksys on MHz grid"
+    severity failure;
+
+  DCM : dcm_sfs
+    generic map (
+      CLKFX_DIVIDE   => sys_conf_clkfx_divide,
+      CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
+      CLKIN_PERIOD   => 10.0)
+    port map (
+      CLKIN   => I_CLK100,
+      CLKFX   => CLK,
+      LOCKED  => open
+    );
+  
+  CLKDIV : clkdivce
+    generic map (
+      CDUWIDTH => 7,                    -- good for up to 127 MHz !
+      USECDIV  => sys_conf_clksys_mhz,
+      MSECDIV  => 1000)
+    port map (
+      CLK     => CLK,
+      CE_USEC => CE_USEC,
+      CE_MSEC => CE_MSEC
+    );
+
+  IOB_RS232 : bp_rs232_2l4l_iob
+    port map (
+      CLK      => CLK,
+      RESET    => '0',
+      SEL      => SWI(0),
+      RXD      => RXSD,
+      TXD      => TXSD,
+      CTS_N    => CTS_N,
+      RTS_N    => RTS_N,
+      I_RXD0   => I_USB_RXD,
+      O_TXD0   => O_USB_TXD,
+      I_RXD1   => I_FUSP_RXD,
+      O_TXD1   => O_FUSP_TXD,
+      I_CTS1_N => I_FUSP_CTS_N,
+      O_RTS1_N => O_FUSP_RTS_N
+    );
+
+  HIO : sn_humanio_demu_rbus
+    generic map (
+      DEBOUNCE => sys_conf_hio_debounce,
+      RB_ADDR  => rbaddr_hio)
+    port map (
+      CLK     => CLK,
+      RESET   => RESET,
+      CE_MSEC => CE_MSEC,
+      RB_MREQ => RB_MREQ,
+      RB_SRES => RB_SRES_HIO,
+      SWI     => SWI,                   
+      BTN     => BTN,                   
+      LED     => LED,                   
+      DSP_DAT => DSP_DAT,               
+      DSP_DP  => DSP_DP,
+      I_SWI   => I_HIO_SWI,                 
+      I_BTN   => I_HIO_BTN,
+      O_LED   => O_HIO_LED
+    );
+
+  FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
+    CNTL : fx2_2fifoctl_as
+      generic map (
+        RXFAWIDTH  => 5,
+        TXFAWIDTH  => 5,
+        CCWIDTH    => sys_conf_fx2_ccwidth,
+        RXAEMPTY_THRES => 1,
+        TXAFULL_THRES  => 1,
+        PETOWIDTH  => sys_conf_fx2_petowidth,
+        RDPWLDELAY => sys_conf_fx2_rdpwldelay,
+        RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
+        WRPWLDELAY => sys_conf_fx2_wrpwldelay,
+        WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
+        FLAGDELAY  => sys_conf_fx2_flagdelay)
+      port map (
+        CLK      => CLK,
+        CE_USEC  => CE_USEC,
+        RESET    => RESET,
+        RXDATA   => FX2_RXDATA,
+        RXVAL    => FX2_RXVAL,
+        RXHOLD   => FX2_RXHOLD,
+        RXAEMPTY => FX2_RXAEMPTY,
+        TXDATA   => FX2_TXDATA,
+        TXENA    => FX2_TXENA,
+        TXBUSY   => FX2_TXBUSY,
+        TXAFULL  => FX2_TXAFULL,
+        MONI           => FX2_MONI,
+        I_FX2_IFCLK    => I_FX2_IFCLK,
+        O_FX2_FIFO     => O_FX2_FIFO,
+        I_FX2_FLAG     => I_FX2_FLAG,
+        O_FX2_SLRD_N   => O_FX2_SLRD_N,
+        O_FX2_SLWR_N   => O_FX2_SLWR_N,
+        O_FX2_SLOE_N   => O_FX2_SLOE_N,
+        O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+        IO_FX2_DATA    => IO_FX2_DATA
+      );
+  end generate FX2_CNTL_AS;
+
+  FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
+    CNTL : fx2_2fifoctl_ic
+      generic map (
+        RXFAWIDTH  => 5,
+        TXFAWIDTH  => 5,
+        PETOWIDTH  => sys_conf_fx2_petowidth,
+        CCWIDTH    => sys_conf_fx2_ccwidth,
+        RXAEMPTY_THRES => 1,
+        TXAFULL_THRES  => 1)
+      port map (
+        CLK      => CLK,
+        RESET    => RESET,
+        RXDATA   => FX2_RXDATA,
+        RXVAL    => FX2_RXVAL,
+        RXHOLD   => FX2_RXHOLD,
+        RXAEMPTY => FX2_RXAEMPTY,
+        TXDATA   => FX2_TXDATA,
+        TXENA    => FX2_TXENA,
+        TXBUSY   => FX2_TXBUSY,
+        TXAFULL  => FX2_TXAFULL,
+        MONI           => FX2_MONI,
+        I_FX2_IFCLK    => I_FX2_IFCLK,
+        O_FX2_FIFO     => O_FX2_FIFO,
+        I_FX2_FLAG     => I_FX2_FLAG,
+        O_FX2_SLRD_N   => O_FX2_SLRD_N,
+        O_FX2_SLWR_N   => O_FX2_SLWR_N,
+        O_FX2_SLOE_N   => O_FX2_SLOE_N,
+        O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+        IO_FX2_DATA    => IO_FX2_DATA
+      );
+  end generate FX2_CNTL_IC;
+
+  FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
+    CNTL : fx2_3fifoctl_ic
+      generic map (
+        RXFAWIDTH  => 5,
+        TXFAWIDTH  => 5,
+        PETOWIDTH  => sys_conf_fx2_petowidth,
+        CCWIDTH    => sys_conf_fx2_ccwidth,
+        RXAEMPTY_THRES => 1,
+        TXAFULL_THRES  => 1,
+        TX2AFULL_THRES => 1)
+      port map (
+        CLK      => CLK,
+        RESET    => RESET,
+        RXDATA   => FX2_RXDATA,
+        RXVAL    => FX2_RXVAL,
+        RXHOLD   => FX2_RXHOLD,
+        RXAEMPTY => FX2_RXAEMPTY,
+        TXDATA   => FX2_TXDATA,
+        TXENA    => FX2_TXENA,
+        TXBUSY   => FX2_TXBUSY,
+        TXAFULL  => FX2_TXAFULL,
+        TX2DATA  => FX2_TX2DATA,
+        TX2ENA   => FX2_TX2ENA,
+        TX2BUSY  => FX2_TX2BUSY,
+        TX2AFULL => FX2_TX2AFULL,
+        MONI           => FX2_MONI,
+        I_FX2_IFCLK    => I_FX2_IFCLK,
+        O_FX2_FIFO     => O_FX2_FIFO,
+        I_FX2_FLAG     => I_FX2_FLAG,
+        O_FX2_SLRD_N   => O_FX2_SLRD_N,
+        O_FX2_SLWR_N   => O_FX2_SLWR_N,
+        O_FX2_SLOE_N   => O_FX2_SLOE_N,
+        O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+        IO_FX2_DATA    => IO_FX2_DATA
+      );
+  end generate FX2_CNTL_IC3;
+    
+  TST : entity work.tst_rlink_cuff
+    port map (
+      CLK         => CLK,
+      RESET       => '0',
+      CE_USEC     => CE_USEC,
+      CE_MSEC     => CE_MSEC,
+      RB_MREQ_TOP => RB_MREQ,
+      RB_SRES_TOP => RB_SRES_HIO,
+      SWI         => SWI,
+      BTN         => BTN(3 downto 0),
+      LED         => LED,
+      DSP_DAT     => DSP_DAT,
+      DSP_DP      => DSP_DP,
+      RXSD        => RXSD,
+      TXSD        => TXSD,
+      RTS_N       => RTS_N,
+      CTS_N       => CTS_N,
+      FX2_RXDATA  => FX2_RXDATA,
+      FX2_RXVAL   => FX2_RXVAL,
+      FX2_RXHOLD  => FX2_RXHOLD,
+      FX2_TXDATA  => FX2_TXDATA,
+      FX2_TXENA   => FX2_TXENA,
+      FX2_TXBUSY  => FX2_TXBUSY,
+      FX2_TX2DATA => FX2_TX2DATA,
+      FX2_TX2ENA  => FX2_TX2ENA,
+      FX2_TX2BUSY => FX2_TX2BUSY,
+      FX2_MONI    => FX2_MONI
+    );
+
+end syn;
+
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/.cvsignore
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/.cvsignore
@@ -0,0 +1,6 @@
+tb_tst_rlink_cuff_ic_n2
+tb_tst_rlink_cuff_ic_n2_[sft]sim
+rlink_cext_fifo_rx
+rlink_cext_fifo_tx
+rlink_cext_conf
+*.dep_ucf_cpp
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile
@@ -0,0 +1,30 @@
+# $Id: Makefile 467 2013-01-02 19:49:05Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2013-01-01   467   1.0    Initial version
+#
+EXE_all = tb_tst_rlink_cuff_ic_n2
+#
+ISE_PATH = xc3s1200e-fg320-4
+#
+.PHONY : all all_ssim all_tsim clean
+#
+all      : $(EXE_all)
+all_ssim : $(EXE_all:=_ssim)
+all_tsim : $(EXE_all:=_tsim)
+#
+clean : ise_clean ghdl_clean
+	rm -f sys_tst_rlink_cuff_ic_n2.ucf
+#
+#-----
+#
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+include $(wildcard *.o.dep_ghdl)
+#
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd
@@ -0,0 +1,60 @@
+-- $Id: sys_conf_sim.vhd 467 2013-01-02 19:49:05Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   sys_conf
+-- Description:    Definitions for sys_tst_rlink_cuff_ic_n2 (for simulation)
+--
+-- Dependencies:   -
+-- Tool versions:  xst 13.3; ghdl 0.29
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-01   467   1.0    Initial version
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+  constant sys_conf_clkfx_divide : positive   := 1;
+  constant sys_conf_clkfx_multiply : positive := 1;
+
+  constant sys_conf_ser2rri_cdinit : integer := 1-1;   -- 1 cycle/bit in sim
+
+  constant sys_conf_hio_debounce : boolean := false;   -- no debouncers
+
+  constant sys_conf_fx2_type : string := "ic2";
+
+  -- dummy values defs for generic parameters of as controller
+  constant sys_conf_fx2_rdpwldelay : positive := 1;
+  constant sys_conf_fx2_rdpwhdelay : positive := 1;
+  constant sys_conf_fx2_wrpwldelay : positive := 1;
+  constant sys_conf_fx2_wrpwhdelay : positive := 1;
+  constant sys_conf_fx2_flagdelay  : positive := 1;
+
+  -- pktend timer setting
+  --   petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
+  constant sys_conf_fx2_petowidth  : positive := 10;
+
+  constant sys_conf_fx2_ccwidth  : positive := 5;
+
+  -- derived constants
+  
+  constant sys_conf_clksys : integer :=
+    (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
+  constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+end package sys_conf;
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_tst_rlink_cuff_ic_n2.ucf_cpp
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_tst_rlink_cuff_ic_n2.ucf_cpp
@@ -0,0 +1 @@
+../sys_tst_rlink_cuff_ic_n2.ucf_cpp
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vbom
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vbom
@@ -0,0 +1,7 @@
+# configure tb_nexsy2_fusp with sys_tst_rlink_n2 target;
+# use vhdl configure file (tb_tst_rlink_cuff_ic_n2.vhd) to allow
+# that all configurations will co-exist in work library
+${nexys2_fusp_cuff_aif := ../sys_tst_rlink_cuff_ic_n2.vbom}
+sys_conf = sys_conf_sim.vhd
+../../../../../bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
+tb_tst_rlink_cuff_ic_n2.vhd
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vhd
@@ -0,0 +1,40 @@
+-- $Id: tb_tst_rlink_cuff_ic_n2.vhd 467 2013-01-02 19:49:05Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name:    tb_tst_rlink_cuff_ic_n2
+-- Description:    Configuration for tb_tst_rlink_cuff_ic_n2 for
+--                   tb_nexys2_fusp_cuff
+--
+-- Dependencies:   sys_tst_rlink_cuff_n2   (fx2_type = 'ic2')
+--
+-- To test:        sys_tst_rlink_cuff_n2   (fx2_type = 'ic2')
+--
+-- Verified:
+-- Date         Rev  Code  ghdl  ise          Target     Comment
+-- 2013-01-xx   xxx  -     0.29  12.1   M53d  xc3s1200e  u:???
+-- 
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-01   467   1.0    Initial version 
+------------------------------------------------------------------------------
+
+configuration tb_tst_rlink_cuff_ic_n2 of tb_nexys2_fusp_cuff is
+
+  for sim
+    for all : nexys2_fusp_cuff_aif
+      use entity work.sys_tst_rlink_cuff_n2;
+    end for;
+  end for;
+
+end tb_tst_rlink_cuff_ic_n2;
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2_ssim.vbom
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2_ssim.vbom
@@ -0,0 +1,6 @@
+# configure for _*sim case
+# Note: this tb uses sys_tst_rlink_n2.vbom in local directory
+#       (not in .. as usual) to allow a tb specific configure !!!
+nexys2_aif = sys_tst_rlink_cuff_ic_n2_ssim.vhd
+tb_tst_rlink_cuff_ic_n2.vbom
+@top:tb_tst_rlink_cuff_ic_n2
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tbw.dat
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tbw.dat
@@ -0,0 +1,6 @@
+# $Id: tbw.dat 467 2013-01-02 19:49:05Z mueller $
+#
+[tb_tst_rlink_cuff_ic_n2]
+rlink_cext_fifo_rx = <fifo>
+rlink_cext_fifo_tx = <fifo>
+rlink_cext_conf = <null>
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_rlink_cuff_ic3_n2.ucf
+*.dep_ucf_cpp
+*.svf
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile
@@ -0,0 +1,29 @@
+# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2012-12-29   466   1.0    Initial version
+#
+#
+VBOM_all  = $(wildcard *.vbom)
+BIT_all   = $(VBOM_all:.vbom=.bit)
+#
+ISE_BOARD = nexys2
+ISE_PATH  = xc3s1200e-fg320-4
+FX2_FILE  = nexys2_jtag_3fifo_ic.ihx
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+	rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd
@@ -0,0 +1,62 @@
+-- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $
+--
+-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   sys_conf
+-- Description:    Definitions for sys_tst_rlink_cuff_ic3_n2 (for synthesis)
+--
+-- Dependencies:   -
+-- Tool versions:  xst 13.3; ghdl 0.29
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2012-12-29   466   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+  constant sys_conf_clkfx_divide : positive   :=  1;
+  constant sys_conf_clkfx_multiply : positive :=  1;
+
+  constant sys_conf_ser2rri_defbaud : integer := 115200;   -- default 115k baud
+  constant sys_conf_hio_debounce : boolean := true;    -- instantiate debouncers
+
+  constant sys_conf_fx2_type : string := "ic3";
+
+  -- dummy values defs for generic parameters of as controller
+  constant sys_conf_fx2_rdpwldelay : positive := 1;
+  constant sys_conf_fx2_rdpwhdelay : positive := 1;
+  constant sys_conf_fx2_wrpwldelay : positive := 1;
+  constant sys_conf_fx2_wrpwhdelay : positive := 1;
+  constant sys_conf_fx2_flagdelay  : positive := 1;
+
+  -- pktend timer setting
+  --   petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
+  constant sys_conf_fx2_petowidth  : positive := 10;
+
+  constant sys_conf_fx2_ccwidth  : positive := 5;
+   
+  -- derived constants
+  
+  constant sys_conf_clksys : integer :=
+    (50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
+  constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+  constant sys_conf_ser2rri_cdinit : integer :=
+    (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
+
+end package sys_conf;
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset
@@ -0,0 +1,97 @@
+# $Id: sys_tst_rlink_cuff_ic3_n2.mfset 469 2013-01-05 12:29:44Z mueller $
+#
+# ----------------------------------------------------------------------------
+[xst]
+INFO:.*Mux is complete : default of case is discarded
+
+Unconnected output port 'SIZE' of component 'fifo_1c_dram'
+Unconnected output port 'LOCKED' of component 'dcm_sfs'
+Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
+Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
+Unconnected output port 'RL_MONI' of component 'rlink_core8'
+
+Input <I_MEM_WAIT> is never used
+Input <RB_MREQ.din<\d+:\d+>> is never used
+Input <RB_MREQ.init> is never used
+Input <BTN> is never used
+Input <SWI<7:3>> is never used
+Input <SWI<0>> is never used
+Input <FX2_MONI.pktend> is never used
+Input <FX2_MONI.slrd> is never used
+Input <FX2_MONI.slwr> is never used
+Input <FX2_MONI.flag_ep4_empty> is never used
+Input <FX2_MONI.flag_ep4_almost> is never used
+Input <FX2_MONI.flag_ep6_full> is never used
+Input <FX2_MONI.flag_ep6_almost> is never used
+Input <FX2_MONI.flag_ep8_full> is never used
+Input <FX2_MONI.flag_ep8_almost> is never used
+Input <FX2_MONI.fifo_ep4> is never used
+Input <FX2_MONI.fifo_ep6> is never used
+Input <FX2_MONI.fifo_ep8> is never used
+
+Output <FX2_TX2DATA> is never assigned
+
+Signal <L_DO<17:16>> is assigned but never used
+Signal <FIFO_SIZE> is assigned but never used
+Signal <RXFIFO_SIZE<2:0>> is assigned but never used
+Signal <RB_LAM_TEST<1:0>> is assigned but never used
+Signal <SER_MONI.rxovr> is assigned but never used
+Signal <SER_MONI.rxerr> is assigned but never used
+Signal <SER_MONI.abdone> is assigned but never used
+Signal <STAT<7:2>> is assigned but never used
+Signal <FX2_TXAFULL> is assigned but never used
+Signal <FX2_RXAEMPTY> is assigned but never used
+Signal <TXSIZE_FX2> is assigned but never used
+Signal <TX2SIZE_FX2> is assigned but never used
+Signal <FX2_TX2AFULL> is assigned but never used
+
+Signal <FX2_TX2ENA_L> is used but never assigned
+Signal <RESET> is used but never assigned
+
+FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
+
+FF/Latch <R_REGS.ucnt_6> has a constant value of 0
+FF/Latch <HIO/R_REGS.ledin_[2-6]> has a constant value of 0
+FF/Latch <FX2_CNTL_IC3.CNTL/(RX|TX|TX2)FIFO/R_REG[RW].rst[rw]> has a constant value of 0
+FF/Latch <FX2_CNTL_IC3.CNTL/(RX|TX|TX2)FIFO/R_REG[RW].rst[rw]_(c|s|sc|ss)> has a constant value of 0
+FF/Latch <FX2_CNTL_IC3.CNTL/TX2FIFO/GCW/GRAY_5.CNT/R_DATA_[0-4]> has a constant value
+FF/Latch <FX2_CNTL_IC3.CNTL/TX2FIFO/R_REGR.waddr_[cs]_[0-4]> has a constant value
+
+Node <HIO/R_REGS.swieff_[3-7]> of sequential type is unconnected
+Node <HIO/R_REGS.swi_[3-7]> of sequential type is unconnected
+Node <HIO/R_REGS.btn_[0-3]> of sequential type is unconnected
+Node <HIO/R_REGS.btneff_[0-3]> of sequential type is unconnected
+Node <TST/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS.moneop> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS.monlamp> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS.monattn> of sequential type is unconnected
+Node <FX2_CNTL_IC3.CNTL/R_MONI_S..*> of sequential type is unconnected
+Node <FX2_CNTL_IC3.CNTL/R_MONI_C..*> of sequential type is unconnected
+Node <FX2_CNTL_IC3.CNTL/R_REGS..*> of sequential type is unconnected
+
+Node <FX2_CNTL_IC3.CNTL/(RX|TX|TX2)FIFO/R_REG[RW].size[rw]_[0-4]> of sequential type is unconnected
+
+RAMs <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM0>, <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM1> are equivalent
+RAMs <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM0>, <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM0> are equivalent
+
+#
+# ----------------------------------------------------------------------------
+[tra]
+
+#
+# ----------------------------------------------------------------------------
+[map]
+The signal <I_MEM_WAIT_IBUF> is incomplete
+INFO:.*
+
+#
+# ----------------------------------------------------------------------------
+[par]
+The signal I_MEM_WAIT_IBUF has no load
+There are 1 loadless signals in this design
+This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied
+#
+# ----------------------------------------------------------------------------
+[bgn]
+Spartan-3 1200E and 1600E devices do not support bitstream
+The signal <I_MEM_WAIT_IBUF> is incomplete
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp
@@ -0,0 +1,22 @@
+## $Id: sys_tst_rlink_cuff_ic3_n2.ucf_cpp 466 2012-12-30 13:26:55Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2012-12-29   466   1.0    Initial version
+##
+
+NET "I_CLK50" TNM_NET = "I_CLK50";
+TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
+OFFSET =  IN 10 ns BEFORE "I_CLK50";
+OFFSET = OUT 20 ns  AFTER "I_CLK50";
+
+#include "bplib/nexys2/nexys2_pins.ucf"
+##
+## Pmod B0 - RS232 
+##
+#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
+##
+## Cypress FX2
+##
+#include "bplib/nexys2/nexys2_pins_fx2.ucf"
+#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom
@@ -0,0 +1,8 @@
+# conf
+sys_conf = sys_conf.vhd
+# libs
+# components
+# design
+../sys_tst_rlink_cuff_n2.vbom
+@ucf_cpp: sys_tst_rlink_cuff_ic3_n2.ucf
+@top: sys_tst_rlink_cuff_n2
--- a/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd
@@ -1,4 +1,4 @@
-- $Id: sys_tst_rlink_cuff_n2.vhd 467 2013-01-02 19:49:05Z mueller $
+-- $Id: sys_tst_rlink_cuff_n2.vhd 469 2013-01-05 12:29:44Z mueller $
 --
 -- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -32,6 +32,7 @@
 --
 -- Synthesized (xst):
 -- Date         Rev  ise         Target      flop lutl lutm slic t peri ctl/MHz
+-- 2013-01-04   469 13.3    O76d xc3s1200e-4  846  1798 160 1215 p 16.3 ic2/ 50
 -- 2012-12-29   466 13.3    O76d xc3s1200e-4  808  1739 160 1172 p 16.3 as2/ 50
 -- 2013-01-02   467 13.3    O76d xc3s1200e-4  843  1792 160 1209 p 15.2 ic2/ 50
 -- 2012-12-29   466 13.3    O76d xc3s1200e-4  863  1850 192 1266 p 13.6 ic3/ 50
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/.cvsignore
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/.cvsignore
@@ -0,0 +1,4 @@
+_impactbatch.log
+sys_tst_rlink_cuff_ic_n3.ucf
+*.dep_ucf_cpp
+*.svf
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile
@@ -0,0 +1,32 @@
+# $Id: Makefile 469 2013-01-05 12:29:44Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2013-01-04   469   1.0    Initial version
+#
+#
+VBOM_all  = $(wildcard *.vbom)
+BIT_all   = $(VBOM_all:.vbom=.bit)
+#
+ISE_BOARD = nexys3
+ISE_PATH  = xc6slx16-csg324-2
+FX2_FILE  = nexys3_jtag_2fifo_ic.ihx
+#
+XFLOWOPT_SYN = syn_s6_speed.opt
+XFLOWOPT_IMP = imp_s6_speed.opt
+#
+.PHONY : all clean
+#
+all : $(BIT_all)
+#
+clean : ise_clean
+	rm -f $(VBOM_all:.vbom=.ucf)
+#
+#----
+#
+include $(RETROBASE)/rtl/make/generic_xflow.mk
+include $(RETROBASE)/rtl/make/generic_ghdl.mk
+#
+include $(VBOM_all:.vbom=.dep_xst)
+include $(VBOM_all:.vbom=.dep_ghdl)
+#
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd
@@ -0,0 +1,62 @@
+-- $Id: sys_conf.vhd 469 2013-01-05 12:29:44Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   sys_conf
+-- Description:    Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis)
+--
+-- Dependencies:   -
+-- Tool versions:  xst 13.3; ghdl 0.29
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2013-01-04   469   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package sys_conf is
+
+  constant sys_conf_clkfx_divide : positive   :=  1;
+  constant sys_conf_clkfx_multiply : positive :=  1;
+
+  constant sys_conf_ser2rri_defbaud : integer := 115200;   -- default 115k baud
+  constant sys_conf_hio_debounce : boolean := true;    -- instantiate debouncers
+
+  constant sys_conf_fx2_type : string := "ic2";
+
+  -- dummy values defs for generic parameters of as controller
+  constant sys_conf_fx2_rdpwldelay : positive := 1;
+  constant sys_conf_fx2_rdpwhdelay : positive := 1;
+  constant sys_conf_fx2_wrpwldelay : positive := 1;
+  constant sys_conf_fx2_wrpwhdelay : positive := 1;
+  constant sys_conf_fx2_flagdelay  : positive := 1;
+
+  -- pktend timer setting
+  --   petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
+  constant sys_conf_fx2_petowidth  : positive := 10;
+
+  constant sys_conf_fx2_ccwidth  : positive := 5;
+   
+  -- derived constants
+  
+  constant sys_conf_clksys : integer :=
+    (100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
+  constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
+
+  constant sys_conf_ser2rri_cdinit : integer :=
+    (sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
+
+end package sys_conf;
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.mfset
@@ -0,0 +1,100 @@
+# $Id: sys_tst_rlink_cuff_ic_n3.mfset 472 2013-01-06 14:39:10Z mueller $
+#
+# ----------------------------------------------------------------------------
+[xst]
+Case statement is complete. others clause is never selected
+Using initial value '0' for reset since it is never assigned
+Using initial value '0' for fx2_tx2ena_l since it is never assigned
+
+Net <FX2_TX2BUSY> does not have a driver.
+
+Output port <LOCKED> of the instance <DCM> is unconnected
+Output port <RXAEMPTY> of the instance <FX2_CNTL_IC.CNTL> is unconnected
+Output port <TXAFULL> of the instance <FX2_CNTL_IC.CNTL> is unconnected
+Output port <FX2_TX2DATA> of the instance <TST> is unconnected
+Output port <FX2_TX2ENA> of the instance <TST> is unconnected
+Output port <SIZER> of the instance <TXFIFO> is unconnected
+Output port <DOA> of the instance <RAM> is unconnected
+Output port <RL_MONI_eop> of the instance <RLCORE> is unconnected
+Output port <RL_MONI_attn> of the instance <RLCORE> is unconnected
+Output port <RL_MONI_lamp> of the instance <RLCORE> is unconnected
+Output port <MONI_rxerr> of the instance <SERPORT> is unconnected
+Output port <MONI_rxovr> of the instance <SERPORT> is unconnected
+Output port <MONI_abdone> of the instance <SERPORT> is unconnected
+Output port <SIZE> of the instance <TXFIFO> is unconnected or connected
+Output port <SIZE> of the instance <FIFO> is unconnected or connected
+Output port <DOB> of the instance <BRAM> is unconnected
+
+Signal <FX2_TX2DATA> is used but never assigned
+
+Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_n3'
+
+Node <FX2_CNTL_IC.CNTL/R_MONI_[CS]_.*> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_sel> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_pf> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_pf> of sequential type is unconnected
+ode <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_sel> of sequential type is unconnected
+Node <IOB_FX2_FLAG/R_DI_3> of sequential type is unconnected
+Node <HIO/R_REGS_swieff_[3-7]> of sequential type is unconnected
+Node <HIO/R_REGS_btn_[0-4]> of sequential type is unconnected
+Node <HIO/R_REGS_swi_[3-7]> of sequential type is unconnected
+Node <HIO/R_REGS_btneff_[0-4]> of sequential type is unconnected
+Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_size[rw]_\d> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS_monattn> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS_monlamp> of sequential type is unconnected
+Node <TST/RLCORE/RL/R_REGS_moneop> of sequential type is unconnected
+Node <TST/SERPORT/XONRX/R_REGS_rxovr> of sequential type is unconnected
+
+Input <RB_MREQ_init> is never used
+Input <RB_MREQ_din<15:10>> is never used
+Input <I_MEM_WAIT> is never used
+Input <SWI<7:3>> is never used
+Input <SWI<0:0>> is never used
+Input <BTN<3:0>> is never used
+Input <FX2_MONI_fifo_ep4> is never used
+Input <FX2_MONI_fifo_ep6> is never used
+Input <FX2_MONI_fifo_ep8> is never used
+Input <FX2_MONI_flag_ep4_empty> is never used
+Input <FX2_MONI_flag_ep4_almost> is never used
+Input <FX2_MONI_flag_ep6_full> is never used
+Input <FX2_MONI_flag_ep6_almost> is never used
+Input <FX2_MONI_flag_ep8_full> is never used
+Input <FX2_MONI_flag_ep8_almost> is never used
+Input <FX2_MONI_slrd> is never used
+Input <FX2_MONI_slwr> is never used
+Input <FX2_MONI_pktend> is never used
+
+FF/Latch <R_MONI_[CS]_.*> has a constant value of 0
+FF/Latch <TX2ENA_PSTR/R_REGS_busy_1> has a constant value
+FF/Latch <TX2ENA_PSTR/R_REGS_busy_0> has a constant value
+
+of type RAMB16_S18 has been replaced by RAMB16BWER
+of type RAMB16_S36 has been replaced by RAMB16BWER
+of type RAMB16_S36_S36 has been replaced by RAMB16BWER
+
+FF/Latch <HIO/R_REGS_ledin_[2-6]> has a constant value of 0
+FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_rst.*> has a constant value
+
+The FF/Latch <R_REGS_rbre> .* is equivalent
+The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[01]> .* is equivalent
+The FF/Latch <HIO/HIO/DRV/R_REGS_cdiv_0> .* is the opposite
+
+#
+# ----------------------------------------------------------------------------
+[tra]
+
+#
+# ----------------------------------------------------------------------------
+[map]
+INFO:.*
+
+#
+# ----------------------------------------------------------------------------
+[par]
+The signal I_MEM_WAIT_IBUF has no load
+The signal I_FX2_FLAG<3>_IBUF has no load
+There are 2 loadless signals in this design
+
+#
+# ----------------------------------------------------------------------------
+[bgn]
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.ucf_cpp
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.ucf_cpp
@@ -0,0 +1,24 @@
+## $Id: sys_tst_rlink_cuff_ic_n3.ucf_cpp 469 2013-01-05 12:29:44Z mueller $
+##
+## Revision History: 
+## Date         Rev Version  Comment
+## 2013-01-04   469   1.0    Initial version
+##
+
+NET "I_CLK100" TNM_NET = "I_CLK100";
+TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
+OFFSET =  IN 10 ns BEFORE "I_CLK100";
+OFFSET = OUT 20 ns  AFTER "I_CLK100";
+
+## std board
+##
+#include "bplib/nexys3/nexys3_pins.ucf"
+##
+## Pmod B0 - RS232 
+##
+#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
+##
+## FX2 interface
+##
+#include "bplib/nexys3/nexys3_pins_fx2.ucf"
+#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.vbom
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.vbom
@@ -0,0 +1,8 @@
+# conf
+sys_conf = sys_conf.vhd
+# libs
+# components
+# design
+../sys_tst_rlink_cuff_n3.vbom
+@ucf_cpp: sys_tst_rlink_cuff_ic_n3.ucf
+@top: sys_tst_rlink_cuff_n3
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom
@@ -0,0 +1,30 @@
+# this is the vbom for the 'generic' top level entity
+# to be referenced in the vbom's of the specific systems
+#   ./as/sys_tst_rlink_cuff_as_n3
+#   ./ic/sys_tst_rlink_cuff_ic_n3
+#   ./ic3/sys_tst_rlink_cuff_ic3_n3
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/xlib/xlib.vhd
+../../../vlib/genlib/genlib.vhd
+../../../bplib/bpgen/bpgenlib.vbom
+../../../vlib/rbus/rblib.vhd
+../../../bplib/fx2lib/fx2lib.vhd
+../../../bplib/nxcramlib/nxcramlib.vhd
+${sys_conf}
+# components
+[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
+[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
+../../../vlib/genlib/clkdivce.vbom
+../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
+../../../bplib/bpgen/sn_humanio_rbus.vbom
+../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
+../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
+../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
+../tst_rlink_cuff.vbom
+../../../bplib/nxcramlib/nx_cram_dummy.vbom
+# design
+sys_tst_rlink_cuff_n3.vhd
+## no @ucf_cpp
+
--- a/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd
+++ b/rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd
@@ -0,0 +1,382 @@
+-- $Id: sys_tst_rlink_cuff_n3.vhd 469 2013-01-05 12:29:44Z mueller $
+--
+-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 2, or at your option any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name:    sys_tst_rlink_cuff_n3 - syn
+-- Description:    rlink tester design for nexys3 with fx2 interface
+--
+-- Dependencies:   vlib/xlib/dcm_sfs
+--                 vlib/genlib/clkdivce
+--                 bplib/bpgen/bp_rs232_2l4l_iob
+--                 bplib/bpgen/sn_humanio_rbus
+--                 bplib/fx2lib/fx2_2fifoctl_as   [sys_conf_fx2_type="as2"]
+--                 bplib/fx2lib/fx2_2fifoctl_ic   [sys_conf_fx2_type="ic2"]
+--                 bplib/fx2lib/fx2_3fifoctl_ic   [sys_conf_fx2_type="ic3"]
+--                 tst_rlink_cuff
+--                 bplib/nxcramlib/nx_cram_dummy
+--
+-- Test bench:     -
+--
+-- Target Devices: generic
+-- Tool versions:  xst 13.3; ghdl 0.29
+--
+-- Synthesized (xst):
+-- Date         Rev  ise         Target      flop lutl lutm slic t peri ctl/MHz
+-- 2013-01-04   469 13.3    O76d xc3s1200e-4  ???  ???? ??? ???? p ??.? ic2/ 50
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2012-12-29   466   1.0    Initial version; derived from sys_tst_rlink_cuff_n2
+--                           and sys_tst_fx2loop_n3
+------------------------------------------------------------------------------
+-- Usage of Nexys 3 Switches, Buttons, LEDs:
+--
+--    SWI(7:3)  no function (only connected to sn_humanio_rbus)
+--       (2)    0 -> int/ext RS242 port for rlink
+--              1 -> use USB interface for rlink
+--       (1)    1 enable XON
+--       (0)    0 -> main board RS232 port  - implemented in bp_rs232_2l4l_iob
+--              1 -> Pmod B/top RS232 port  /
+--
+--    LED(7)    SER_MONI.abact
+--       (6:2)  no function (only connected to sn_humanio_rbus)
+--       (0)    timer 0 busy 
+--       (1)    timer 1 busy 
+--
+--    DSP:      SER_MONI.clkdiv         (from auto bauder)
+--    for SWI(2)='0' (serport)
+--    DP(3)     not SER_MONI.txok       (shows tx back preasure)
+--      (2)     SER_MONI.txact          (shows tx activity)
+--      (1)     not SER_MONI.rxok       (shows rx back preasure)
+--      (0)     SER_MONI.rxact          (shows rx activity)
+--    for SWI(2)='1' (fx2)
+--    DP(3)     FX2_TX2BUSY             (shows tx2 back preasure)
+--      (2)     FX2_TX2ENA(stretched)   (shows tx2 activity)
+--      (1)     FX2_TXENA(streched)     (shows tx activity)
+--      (0)     FX2_RXVAL(stretched)    (shows rx activity)
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+use work.bpgenlib.all;
+use work.rblib.all;
+use work.fx2lib.all;
+use work.nxcramlib.all;
+use work.sys_conf.all;
+
+-- ----------------------------------------------------------------------------
+
+entity sys_tst_rlink_cuff_n3 is         -- top level
+                                        -- implements nexys3_fusp_cuff_aif
+  port (
+    I_CLK100 : in slbit;                -- 100 MHz clock
+    I_RXD : in slbit;                   -- receive data (board view)
+    O_TXD : out slbit;                  -- transmit data (board view)
+    I_SWI : in slv8;                    -- n3 switches
+    I_BTN : in slv5;                    -- n3 buttons
+    O_LED : out slv8;                   -- n3 leds
+    O_ANO_N : out slv4;                 -- 7 segment disp: anodes   (act.low)
+    O_SEG_N : out slv8;                 -- 7 segment disp: segments (act.low)
+    O_MEM_CE_N : out slbit;             -- cram: chip enable   (act.low)
+    O_MEM_BE_N : out slv2;              -- cram: byte enables  (act.low)
+    O_MEM_WE_N : out slbit;             -- cram: write enable  (act.low)
+    O_MEM_OE_N : out slbit;             -- cram: output enable (act.low)
+    O_MEM_ADV_N  : out slbit;           -- cram: address valid (act.low)
+    O_MEM_CLK : out slbit;              -- cram: clock
+    O_MEM_CRE : out slbit;              -- cram: command register enable
+    I_MEM_WAIT : in slbit;              -- cram: mem wait
+    O_MEM_ADDR  : out slv23;            -- cram: address lines
+    IO_MEM_DATA : inout slv16;          -- cram: data lines
+    O_PPCM_CE_N : out slbit;            -- ppcm: ...
+    O_PPCM_RST_N : out slbit;           -- ppcm: ...
+    O_FUSP_RTS_N : out slbit;           -- fusp: rs232 rts_n
+    I_FUSP_CTS_N : in slbit;            -- fusp: rs232 cts_n
+    I_FUSP_RXD : in slbit;              -- fusp: rs232 rx
+    O_FUSP_TXD : out slbit;             -- fusp: rs232 tx
+    I_FX2_IFCLK : in slbit;             -- fx2: interface clock
+    O_FX2_FIFO : out slv2;              -- fx2: fifo address
+    I_FX2_FLAG : in slv4;               -- fx2: fifo flags
+    O_FX2_SLRD_N : out slbit;           -- fx2: read enable    (act.low)
+    O_FX2_SLWR_N : out slbit;           -- fx2: write enable   (act.low)
+    O_FX2_SLOE_N : out slbit;           -- fx2: output enable  (act.low)
+    O_FX2_PKTEND_N : out slbit;         -- fx2: packet end     (act.low)
+    IO_FX2_DATA : inout slv8            -- fx2: data lines
+  );
+end sys_tst_rlink_cuff_n3;
+
+architecture syn of sys_tst_rlink_cuff_n3 is
+  
+  signal CLK :   slbit := '0';
+  signal RESET : slbit := '0';
+
+  signal CE_USEC :  slbit := '0';
+  signal CE_MSEC :  slbit := '0';
+  
+  signal RXSD  : slbit := '0';
+  signal TXSD  : slbit := '0';
+  signal CTS_N : slbit := '0';
+  signal RTS_N : slbit := '0';
+
+  signal SWI     : slv8  := (others=>'0');
+  signal BTN     : slv5  := (others=>'0');
+  signal LED     : slv8  := (others=>'0');  
+  signal DSP_DAT : slv16 := (others=>'0');
+  signal DSP_DP  : slv4  := (others=>'0');
+  
+  signal RB_MREQ : rb_mreq_type := rb_mreq_init;
+  signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
+
+  signal FX2_RXDATA   : slv8 := (others=>'0');
+  signal FX2_RXVAL    : slbit := '0';
+  signal FX2_RXHOLD   : slbit := '0';
+  signal FX2_RXAEMPTY : slbit := '0';
+  signal FX2_TXDATA   : slv8 := (others=>'0');
+  signal FX2_TXENA    : slbit := '0';
+  signal FX2_TXBUSY   : slbit := '0';
+  signal FX2_TXAFULL  : slbit := '0';
+  signal FX2_TX2DATA  : slv8 := (others=>'0');
+  signal FX2_TX2ENA   : slbit := '0';
+  signal FX2_TX2BUSY  : slbit := '0';
+  signal FX2_TX2AFULL : slbit := '0';
+  signal FX2_MONI  : fx2ctl_moni_type := fx2ctl_moni_init;
+
+  constant rbaddr_hio   : slv8 := "11000000"; -- 110000xx
+
+begin
+
+  assert (sys_conf_clksys mod 1000000) = 0
+    report "assert sys_conf_clksys on MHz grid"
+    severity failure;
+
+  DCM : dcm_sfs
+    generic map (
+      CLKFX_DIVIDE   => sys_conf_clkfx_divide,
+      CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
+      CLKIN_PERIOD   => 10.0)
+    port map (
+      CLKIN   => I_CLK100,
+      CLKFX   => CLK,
+      LOCKED  => open
+    );
+  
+  CLKDIV : clkdivce
+    generic map (
+      CDUWIDTH => 7,                    -- good for up to 127 MHz !
+      USECDIV  => sys_conf_clksys_mhz,
+      MSECDIV  => 1000)
+    port map (
+      CLK     => CLK,
+      CE_USEC => CE_USEC,
+      CE_MSEC => CE_MSEC
+    );
+
+  IOB_RS232 : bp_rs232_2l4l_iob
+    port map (
+      CLK      => CLK,
+      RESET    => '0',
+      SEL      => SWI(0),
+      RXD      => RXSD,
+      TXD      => TXSD,
+      CTS_N    => CTS_N,
+      RTS_N    => RTS_N,
+      I_RXD0   => I_RXD,
+      O_TXD0   => O_TXD,
+      I_RXD1   => I_FUSP_RXD,
+      O_TXD1   => O_FUSP_TXD,
+      I_CTS1_N => I_FUSP_CTS_N,
+      O_RTS1_N => O_FUSP_RTS_N
+    );
+
+  HIO : sn_humanio_rbus
+    generic map (
+      BWIDTH   => 5,
+      DEBOUNCE => sys_conf_hio_debounce,
+      RB_ADDR  => rbaddr_hio)
+    port map (
+      CLK     => CLK,
+      RESET   => RESET,
+      CE_MSEC => CE_MSEC,
+      RB_MREQ => RB_MREQ,
+      RB_SRES => RB_SRES_HIO,
+      SWI     => SWI,                   
+      BTN     => BTN,                   
+      LED     => LED,                   
+      DSP_DAT => DSP_DAT,               
+      DSP_DP  => DSP_DP,
+      I_SWI   => I_SWI,                 
+      I_BTN   => I_BTN,
+      O_LED   => O_LED,
+      O_ANO_N => O_ANO_N,
+      O_SEG_N => O_SEG_N
+    );
+
+  FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
+    CNTL : fx2_2fifoctl_as
+      generic map (
+        RXFAWIDTH  => 5,
+        TXFAWIDTH  => 5,
+        CCWIDTH    => sys_conf_fx2_ccwidth,
+        RXAEMPTY_THRES => 1,
+        TXAFULL_THRES  => 1,
+        PETOWIDTH  => sys_conf_fx2_petowidth,
+        RDPWLDELAY => sys_conf_fx2_rdpwldelay,
+        RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
+        WRPWLDELAY => sys_conf_fx2_wrpwldelay,
+        WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
+        FLAGDELAY  => sys_conf_fx2_flagdelay)
+      port map (
+        CLK      => CLK,
+        CE_USEC  => CE_USEC,
+        RESET    => RESET,
+        RXDATA   => FX2_RXDATA,
+        RXVAL    => FX2_RXVAL,
+        RXHOLD   => FX2_RXHOLD,
+        RXAEMPTY => FX2_RXAEMPTY,
+        TXDATA   => FX2_TXDATA,
+        TXENA    => FX2_TXENA,
+        TXBUSY   => FX2_TXBUSY,
+        TXAFULL  => FX2_TXAFULL,
+        MONI           => FX2_MONI,
+        I_FX2_IFCLK    => I_FX2_IFCLK,
+        O_FX2_FIFO     => O_FX2_FIFO,
+        I_FX2_FLAG     => I_FX2_FLAG,
+        O_FX2_SLRD_N   => O_FX2_SLRD_N,
+        O_FX2_SLWR_N   => O_FX2_SLWR_N,
+        O_FX2_SLOE_N   => O_FX2_SLOE_N,
+        O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+        IO_FX2_DATA    => IO_FX2_DATA
+      );
+  end generate FX2_CNTL_AS;
+
+  FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
+    CNTL : fx2_2fifoctl_ic
+      generic map (
+        RXFAWIDTH  => 5,
+        TXFAWIDTH  => 5,
+        PETOWIDTH  => sys_conf_fx2_petowidth,
+        CCWIDTH    => sys_conf_fx2_ccwidth,
+        RXAEMPTY_THRES => 1,
+        TXAFULL_THRES  => 1)
+      port map (
+        CLK      => CLK,
+        RESET    => RESET,
+        RXDATA   => FX2_RXDATA,
+        RXVAL    => FX2_RXVAL,
+        RXHOLD   => FX2_RXHOLD,
+        RXAEMPTY => FX2_RXAEMPTY,
+        TXDATA   => FX2_TXDATA,
+        TXENA    => FX2_TXENA,
+        TXBUSY   => FX2_TXBUSY,
+        TXAFULL  => FX2_TXAFULL,
+        MONI           => FX2_MONI,
+        I_FX2_IFCLK    => I_FX2_IFCLK,
+        O_FX2_FIFO     => O_FX2_FIFO,
+        I_FX2_FLAG     => I_FX2_FLAG,
+        O_FX2_SLRD_N   => O_FX2_SLRD_N,
+        O_FX2_SLWR_N   => O_FX2_SLWR_N,
+        O_FX2_SLOE_N   => O_FX2_SLOE_N,
+        O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+        IO_FX2_DATA    => IO_FX2_DATA
+      );
+  end generate FX2_CNTL_IC;
+
+  FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
+    CNTL : fx2_3fifoctl_ic
+      generic map (
+        RXFAWIDTH  => 5,
+        TXFAWIDTH  => 5,
+        PETOWIDTH  => sys_conf_fx2_petowidth,
+        CCWIDTH    => sys_conf_fx2_ccwidth,
+        RXAEMPTY_THRES => 1,
+        TXAFULL_THRES  => 1,
+        TX2AFULL_THRES => 1)
+      port map (
+        CLK      => CLK,
+        RESET    => RESET,
+        RXDATA   => FX2_RXDATA,
+        RXVAL    => FX2_RXVAL,
+        RXHOLD   => FX2_RXHOLD,
+        RXAEMPTY => FX2_RXAEMPTY,
+        TXDATA   => FX2_TXDATA,
+        TXENA    => FX2_TXENA,
+        TXBUSY   => FX2_TXBUSY,
+        TXAFULL  => FX2_TXAFULL,
+        TX2DATA  => FX2_TX2DATA,
+        TX2ENA   => FX2_TX2ENA,
+        TX2BUSY  => FX2_TX2BUSY,
+        TX2AFULL => FX2_TX2AFULL,
+        MONI           => FX2_MONI,
+        I_FX2_IFCLK    => I_FX2_IFCLK,
+        O_FX2_FIFO     => O_FX2_FIFO,
+        I_FX2_FLAG     => I_FX2_FLAG,
+        O_FX2_SLRD_N   => O_FX2_SLRD_N,
+        O_FX2_SLWR_N   => O_FX2_SLWR_N,
+        O_FX2_SLOE_N   => O_FX2_SLOE_N,
+        O_FX2_PKTEND_N => O_FX2_PKTEND_N,
+        IO_FX2_DATA    => IO_FX2_DATA
+      );
+  end generate FX2_CNTL_IC3;
+    
+  TST : entity work.tst_rlink_cuff
+    port map (
+      CLK         => CLK,
+      RESET       => '0',
+      CE_USEC     => CE_USEC,
+      CE_MSEC     => CE_MSEC,
+      RB_MREQ_TOP => RB_MREQ,
+      RB_SRES_TOP => RB_SRES_HIO,
+      SWI         => SWI,
+      BTN         => BTN(3 downto 0),
+      LED         => LED,
+      DSP_DAT     => DSP_DAT,
+      DSP_DP      => DSP_DP,
+      RXSD        => RXSD,
+      TXSD        => TXSD,
+      RTS_N       => RTS_N,
+      CTS_N       => CTS_N,
+      FX2_RXDATA  => FX2_RXDATA,
+      FX2_RXVAL   => FX2_RXVAL,
+      FX2_RXHOLD  => FX2_RXHOLD,
+      FX2_TXDATA  => FX2_TXDATA,
+      FX2_TXENA   => FX2_TXENA,
+      FX2_TXBUSY  => FX2_TXBUSY,
+      FX2_TX2DATA => FX2_TX2DATA,
+      FX2_TX2ENA  => FX2_TX2ENA,
+      FX2_TX2BUSY => FX2_TX2BUSY,
+      FX2_MONI    => FX2_MONI
+    );
+
+  SRAM_PROT : nx_cram_dummy            -- connect CRAM to protection dummy
+    port map (
+      O_MEM_CE_N  => O_MEM_CE_N,
+      O_MEM_BE_N  => O_MEM_BE_N,
+      O_MEM_WE_N  => O_MEM_WE_N,
+      O_MEM_OE_N  => O_MEM_OE_N,
+      O_MEM_ADV_N => O_MEM_ADV_N,
+      O_MEM_CLK   => O_MEM_CLK,
+      O_MEM_CRE   => O_MEM_CRE,
+      I_MEM_WAIT  => I_MEM_WAIT,
+      O_MEM_ADDR  => O_MEM_ADDR,
+      IO_MEM_DATA => IO_MEM_DATA
+    );
+
+  O_PPCM_CE_N  <= '1';                  -- keep parallel PCM memory disabled
+  O_PPCM_RST_N <= '1';                  --
+  
+end syn;
+
--- a/rtl/vlib/rlink/tb/tbcore_rlink.vhd
+++ b/rtl/vlib/rlink/tb/tbcore_rlink.vhd
@@ -1,6 +1,6 @@
-- $Id: tbcore_rlink.vhd 445 2011-12-26 21:19:26Z mueller $
+-- $Id: tbcore_rlink.vhd 469 2013-01-05 12:29:44Z mueller $
 --
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -23,6 +23,7 @@
 -- Tool versions:  xst 11.4, 13.1; ghdl 0.26-0.29
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2013-01-04   469   3.1.2  use 1ns wait for .sinit to allow simbus debugging
 -- 2011-12-25   445   3.1.1  add SB_ init drivers to avoid SB_VAL='U' at start
 -- 2011-12-23   444   3.1    redo clock handling, remove simclk, CLK now input
 -- 2011-11-19   427   3.0.1  now numeric_std clean
@@ -129,11 +130,11 @@ begin
            SB_ADDR <= iaddr;
            SB_DATA <= idata;
            SB_VAL  <= 'H';
-            wait for 0 ns;
+            wait for 1 ns;
            SB_VAL  <= 'L';
            SB_ADDR <= (others=>'L');
            SB_DATA <= (others=>'L');
-            wait for 0 ns;
+            wait for 1 ns;

          when others =>                -- bad command
            write(oline, string'("?? unknown command: "));
--- a/tools/bin/fx2load_wrapper
+++ b/tools/bin/fx2load_wrapper
@@ -1,7 +1,7 @@
 #!/usr/bin/perl -w
-# $Id: fx2load_wrapper 457 2012-02-12 22:34:20Z mueller $
+# $Id: fx2load_wrapper 470 2013-01-05 17:28:46Z mueller $
 #
-# Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 #
 # This program is free software; you may redistribute and/or modify it under
 # the terms of the GNU General Public License as published by the Free
@@ -206,6 +206,7 @@ sub print_help {
  print "usage: fx2load_wrapper [--board=b] [--file=f] <opts>\n";
  print "  --help           this message\n";
  print "  --dry_run        print command only\n";
+  print "  --force          reload even when proper firmware detected\n";
  print "  --cycfx2prog     use cycfx2prog instead of fxload\n";
  print "  --board=b        type of board (default nexys2)\n";
  print "  --file=f         ihx file to load (default 2fifo_as)\n";
--- a/tools/fx2/bin/nexys2_jtag.ihx
+++ b/tools/fx2/bin/nexys2_jtag.ihx
@@ -1,4 +1,4 @@
-:06000000020DAC02006BD2
+:06000000020DB102006BCD
 :03000B0002006B85
 :0300130002006B7D
 :03001B0002006B75
@@ -35,21 +35,21 @@
 :08016900006B0002006B0002B4
 :08017100006B0002006B0002AC
 :07017900006B0002006B00A7
-:030DB200020DBA75
-:030DCD00020DB55F
-:050DB5001203F180FEB5
+:030DB700020DBF6B
+:030DD200020DBA55
+:050DBA001203F180FEB0
 :06018000C200E4F508F5E1
 :0401860009F50AD29B
 :05018A0001750B00757A
-:06018F000C001205FB123A
-:0E01950005F875CB6375CAC0758E0075C80479
+:06018F000C001206001234
+:0E01950005FD75CB6375CAC0758E0075C80474
 :0701A300D2AFD2B0D2B122AD
 :0B01AA00AA82850C827583E0EAF00554
 :0501B5000C0509E4B592
 :0401BA000902050A27
 :0101BE00221E
 :0401BF0020000122F9
-:0E01C3001205F790E6A2E0FA30E103020257BF
+:0E01C3001205FC90E6A2E0FA30E103020257BA
 :0A01D100E509450A60687AC07BE783
 :0E01DB008B9D7AC07BE77B008A9E90E67C7449
 :0C01E90031F07460F0C3743E9509E49599
@@ -81,19 +81,19 @@
 :0B02C400FCEF3DFD30012C8E008F018F
 :0902CF008802890318B8FF011927
 :0E02D800EA4B60B390E67BE0F582C004C005FF
-:0E02E600C000C001120632D001D000D005D0F9
+:0E02E600C000C001120637D001D000D005D0F4
 :0302F4000480D8AB
 :0402F7008E028F03E1
 :0902FB008A068B071ABAFF011BE9
 :0E030400EE4F608790E67BE0F582C002C003FA
-:0E031200C004C00512066F1201AAD005D00467
+:0E031200C004C0051206741201AAD005D00462
 :06032000D003D00280D5DD
 :0D03260090E67BE0FA23235401FBB40100B4
 :0A0333009201EA30E707743F5AF523
 :03033D0008802213
-:0C03400030010F8A82C004C005120606BE
+:0C03400030010F8A82C004C00512060BB9
 :06034C00D005D004801072
-:0E0352008A82C004C0051206241201AAD0053A
+:0E0352008A82C004C0051206291201AAD00535
 :02036000D004C7
 :050362000CBC00010DC0
 :0303670002028F00
@@ -111,67 +111,67 @@
 :0903D200500790E6BEE0FA80023B
 :0203DB007A02A4
 :0903DD0090E68BEAF07582012222
-:0603E60030020312090FB2
+:0603E600300203120914AD
 :0503EC001201BF80F5C5
-:0903F100C2AF1201801206BE1217
-:0603FA000450120CDF129A
-:080400000879D2AF120788024F
-:0204080003E609
-:0A040A00AA82E50F54FEFBB50F02B5
-:0204140080293D
-:0A0416008A048C05E46210ED621107
-:0A042000EB2400F582E43418F583A4
-:0A042A00E0FB7C006210EC6211E5BB
-:060434001033C51133C5B1
-:05043A001192E0F51035
-:06043F00AB0F050FEB24DA
-:0A04450000F582E43418F583EAF0B4
-:01044F00228A
-:07045000750F007510AA757D
-:0C04570011AA75820012040A75820012BE
-:04046300040A7A000D
-:0C046700C3EA648094865017EA2408F56C
-:0C04730082E434E1F583E0F582C002125F
-:07047F00040AD0020A80E12B
-:020486007A00FA
-:0C048800C3EA648094825017EA2423F534
-:0C04940082E434E1F583E0F582C002123E
-:0704A000040AD0020A80E10A
-:0E04A70075821C12040A75820012040A7A0083
-:0C04B500C3EA648094825017EA2402F528
-:0C04C10082E434E1F583E0F582C0021211
-:0704CD00040AD0020A80E1DD
-:0C04D4007486250FFAF582C00212040A9B
-:0C04E00090E188E0F58212040AD002903E
-:0D04EC00E188E02AFAF582C00212040A90AD
-:0B04F900E1A6E0F58212040AD0029098
-:0A050400E1A6E02AF58212040A9035
-:0A050E00E1BEE0F58212040A7A0053
-:0E05180090E188E0FBC3EA64808BF063F08022
-:0B05260095F05017EA2488F582E434B9
-:0C053100E1F583E0F582C00212040AD05C
-:04053D00020A80D757
-:020541007A003E
-:0E05430090E1A6E0FBC3EA64808BF063F080D9
-:0B05510095F05017EA24A6F582E43470
-:0C055C00E1F583E0F582C00212040AD031
-:04056800020A80D72C
-:02056C007A0013
-:0E056E0090E1BEE0FBC3EA64808BF063F08096
-:0B057C0095F05017EA24BEF582E4342D
-:0C058700E1F583E0F582C00212040AD006
-:04059300020A80D701
-:020597007A00E8
-:0C059900C3EA648094845017EA240EF535
-:0C05A50082E434E1F583E0F582C002122C
-:0705B100040AD0020A80E1F8
-:0C05B8007482250F400875820012040AAE
-:0205C40080F2C3
-:0805C600AA1090187EEAF0AAC9
-:0705CE001190187FEAF022F2
-:0805D5007880E84400600C7915
-:0C05DD0001901800E4F0A3D8FCD9FAD07B
-:0E05E90083D082F6D8FDC082C08375820022C6
+:0E03F100C2AF90E609E4F01201801206C312BA
+:0603FF000455120CE4128B
+:08040500087ED2AF12078D0240
+:02040D0003E604
+:0A040F00AA82E50F54FEFBB50F02B0
+:02041900802938
+:0A041B008A048C05E46210ED621102
+:0A042500EB2400F582E43418F5839F
+:0A042F00E0FB7C006210EC6211E5B6
+:060439001033C51133C5AC
+:05043F001192E0F51030
+:06044400AB0F050FEB24D5
+:0A044A0000F582E43418F583EAF0AF
+:010454002285
+:07045500750F007510AA7578
+:0C045C0011AA75820012040F75820012B4
+:04046800040F7A0003
+:0C046C00C3EA648094865017EA2408F567
+:0C04780082E434E1F583E0F582C002125A
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--- a/tools/fx2/bin/nexys2_jtag_3fifo_ic.ihx
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 :00000001FF
--- a/tools/fx2/src/main.c
+++ b/tools/fx2/src/main.c
@@ -1,6 +1,6 @@
-/* $Id: main.c 447 2011-12-31 19:41:32Z mueller $ */
+/* $Id: main.c 472 2013-01-06 14:39:10Z mueller $ */
 /*
- * Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+ * Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 * Code was forked from ixo-jtag.svn.sourceforge.net on 2011-07-17
 *
 * - original copyright and licence disclaimer --------------------------------
@@ -25,6 +25,7 @@
 * Revision History:
 * 
 * Date         Rev Version  Comment
+ * 2013-01-05   472   1.1.1  BUGFIX: explicitly set FIFOPINPOLAR=0
 * 2011-07-23   397   1.1    factor out usb_fifo_init() code
 * 2011-07-17   394   1.0    Initial version (from ixo-jtag/usb_jtag Rev 204)
 *
@@ -349,6 +350,12 @@ extern void usb_fifo_init(void);
 void main(void)
 {
  EA = 0; // disable all interrupts
+ 
+  // Digilent nexys3 and atlys boards change FIFOPINPOLAR such that
+  // EE and FF are active high. In nexys2 boards they are active low
+  // All config regs should be set (even when power on defaults are
+  // use, but this one especially....
+  FIFOPINPOLAR = 0;

  usb_jtag_init();
  usb_fifo_init();
--- a/tools/src/librlink/RlinkPacketBuf.cpp
+++ b/tools/src/librlink/RlinkPacketBuf.cpp
@@ -1,6 +1,6 @@
-// $Id: RlinkPacketBuf.cpp 375 2011-04-02 07:56:47Z mueller $
+// $Id: RlinkPacketBuf.cpp 469 2013-01-05 12:29:44Z mueller $
 //
-// Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+// Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 //
 // This program is free software; you may redistribute and/or modify it under
 // the terms of the GNU General Public License as published by the Free
@@ -13,13 +13,14 @@
 // 
 // Revision History: 
 // Date         Rev Version  Comment
+// 2013-01-04   469   1.0.1  SndOob(): Add filler 0 to ensure escape state
 // 2011-04-02   375   1.0    Initial version
 // 2011-03-05   366   0.1    First draft
 // ---------------------------------------------------------------------------

 /*!
  \file
-  \version $Id: RlinkPacketBuf.cpp 375 2011-04-02 07:56:47Z mueller $
+  \version $Id: RlinkPacketBuf.cpp 469 2013-01-05 12:29:44Z mueller $
  \brief   Implemenation of class RlinkPacketBuf.
 */

@@ -271,6 +272,9 @@ bool RlinkPacketBuf::SndOob(RlinkPort* port, uint16_t addr, uint16_t data,
  fRawBuf.push_back((uint8_t)addr);                 // ADDR 
  fRawBuf.push_back((uint8_t)(data & 0x00ff));      // DL
  fRawBuf.push_back((uint8_t)((data>>8) & 0x00ff)); // DH
+  // write a filler char (just 0) to ensure that the 8b->9b stage in the
+  // receiver (byte2cdata) is always out if the escape state...
+  fRawBuf.push_back(0);                             // filler

  return SndRaw(port, emsg);
 }
--- a/tools/tcl/rbbram/perf.tcl
+++ b/tools/tcl/rbbram/perf.tcl
@@ -1,6 +1,6 @@
-# $Id: perf.tcl 465 2012-12-27 21:29:38Z mueller $
+# $Id: perf.tcl 469 2013-01-05 12:29:44Z mueller $
 #
-# Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 #
 # This program is free software; you may redistribute and/or modify it under
 # the terms of the GNU General Public License as published by the Free
@@ -13,7 +13,8 @@
 #
 #  Revision History:
 # Date         Rev Version  Comment
-# 2012-12-27   495   1.0.1  adopt format, cover small ms and large kb 
+# 2013-01-04   469   1.0.2  perf_blk: add optional 2nd arg: trace
+# 2012-12-27   465   1.0.1  adopt format, cover small ms and large kb 
 # 2011-04-17   376   1.0    Initial version
 #

@@ -23,7 +24,7 @@ namespace eval rbbram {
  #
  # perf_blk: determine wblk/rblk write performance
  # 
-  proc perf_blk {{tmax 1000}} {
+  proc perf_blk {{tmax 1000} {trace 0}} {
    if {$tmax < 1} { error "-E: perf_blk: tmax argument must be >= 1" }

    set amax [regget rbbram::CNTL(addr) -1]
@@ -47,6 +48,7 @@ namespace eval rbbram {
      set pval {}

      # single wblk
+      if {$trace} { puts "1 wblk for $nblk" }
      set tbeg [clock clicks -milliseconds]
      set addr 0x0000
      for {set i 1} {1} {incr i} {
@@ -60,6 +62,7 @@ namespace eval rbbram {
      lappend pval 1 $i $trun

      # double wblk
+      if {$trace} { puts "2 wblk for $nblk" }
      set tbeg [clock clicks -milliseconds]
      set addr 0x0000
      for {set i 1} {1} {incr i} {
@@ -74,6 +77,7 @@ namespace eval rbbram {
      lappend pval 2 $i $trun

      # quad wblk
+      if {$trace} { puts "4 wblk for $nblk" }
      set tbeg [clock clicks -milliseconds]
      set addr 0x0000
      for {set i 1} {1} {incr i} {
@@ -90,6 +94,7 @@ namespace eval rbbram {
      lappend pval 4 $i $trun

      # single rblk
+      if {$trace} { puts "1 rblk for $nblk" }
      set tbeg [clock clicks -milliseconds]
      set addr 0x0000
      for {set i 1} {1} {incr i} {
@@ -103,6 +108,7 @@ namespace eval rbbram {
      lappend pval 1 $i $trun

      # double rblk
+      if {$trace} { puts "2 rblk for $nblk" }
      set tbeg [clock clicks -milliseconds]
      set addr 0x0000
      for {set i 1} {1} {incr i} {
@@ -117,6 +123,7 @@ namespace eval rbbram {
      lappend pval 2 $i $trun

      # quad rblk
+      if {$trace} { puts "4 rblk for $nblk" }
      set tbeg [clock clicks -milliseconds]
      set addr 0x0000
      for {set i 1} {1} {incr i} {
--- a/tools/tcl/tst_rlink/test_all.tcl
+++ b/tools/tcl/tst_rlink/test_all.tcl
@@ -1,4 +1,4 @@
-# $Id: test_all.tcl 376 2011-04-17 12:24:07Z mueller $
+# $Id: test_all.tcl 469 2013-01-05 12:29:44Z mueller $
 #
 # Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 #
@@ -13,6 +13,7 @@
 #
 #  Revision History:
 # Date         Rev Version  Comment
+# 2013-01-04   469   1.0.2  move rbemon tests from test_all to test_all_emon
 # 2011-04-17   376   1.0.1  add rbemon::test_rbtest_sim  (if in sum mode)
 # 2011-04-02   375   1.0    Initial version
 # 2011-03-26   373   0.1    First draft
@@ -33,13 +34,24 @@ namespace eval tst_rlink {
    incr errcnt [rbtest::test_all 0x7 0xfffc]
    incr errcnt [rbmoni::test_regs]
    incr errcnt [rbmoni::test_rbtest]
-    incr errcnt [rbemon::test_regs]
-    if {[rlink::issim]} {
-      incr errcnt [rbemon::test_rbtest_sim]
-    }

    puts "tst_rlink::test_all errcnt = $errcnt --> [rutil::errcnt2txt $errcnt]"

+    return $errcnt
+  }
+  #
+  # Driver for emon based tst_rlink tests
+  #
+  proc test_all_emon {} {
+    #
+    set errcnt 0
+    incr errcnt [rbemon::test_regs]
+    if {[rlink::issim]} {
+      incr errcnt [rbemon::test_rbtest_sim]
+    }
+
+    puts "tst_rlink::test_all_emon errcnt = $errcnt --> [rutil::errcnt2txt $errcnt]"
+
    return $errcnt
  }
 }