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Code Issues Releases Wiki Activity

- interim release w11a_V0.561 (untagged)

Browse Source 
- Added simple simulation model of Cypress FX2 and test benches for
  functional verifcation of FX2 controller
- Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys
- Added test systems for rlink over USB verification for Nexys3 & Atlys
This commit is contained in:
Walter F.J. Mueller
2013-01-06 16:19:26 +00:00
parent cbd8ce3468
commit 29d2dc5bef
67 changed files with 6004 additions and 3227 deletions
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6
Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
# $Id: Makefile 472 2013-01-06 14:39:10Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -19,6 +19,9 @@ SYN_all += rtl/sys_gen/tst_rlink/nexys2
SYN_all += rtl/sys_gen/tst_rlink/nexys3
SYN_all += rtl/sys_gen/tst_rlink/s3board
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
SYN_all += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
SYN_all += rtl/sys_gen/tst_rlink_cuff/atlys/ic
SYN_all += rtl/sys_gen/tst_serloop/nexys2
SYN_all += rtl/sys_gen/tst_serloop/nexys3
SYN_all += rtl/sys_gen/tst_serloop/s3board
@@ -34,6 +37,7 @@ SIM_all += rtl/bplib/nxcramlib/tb
SIM_all += rtl/sys_gen/tst_rlink/nexys2/tb
SIM_all += rtl/sys_gen/tst_rlink/nexys3/tb
SIM_all += rtl/sys_gen/tst_rlink/s3board/tb
SIM_all += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
SIM_all += rtl/sys_gen/tst_serloop/nexys2/tb
SIM_all += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_all += rtl/sys_gen/tst_serloop/s3board/tb