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Code Issues Releases Wiki Activity

- interim release w11a_V0.561 (untagged)

Browse Source 
- Added simple simulation model of Cypress FX2 and test benches for
  functional verifcation of FX2 controller
- Bugfixes in FX2 firmware and controller, works now also on Nexys3 & Atlys
- Added test systems for rlink over USB verification for Nexys3 & Atlys
This commit is contained in:
Walter F.J. Mueller
2013-01-06 16:19:26 +00:00
parent cbd8ce3468
commit 29d2dc5bef
67 changed files with 6004 additions and 3227 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
rtl/sys_gen/tst_fx2loop/Makefile
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# $Id: Makefile 461 2012-04-09 21:17:54Z mueller $
# $Id: Makefile 470 2013-01-05 17:28:46Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-01-05 470 1.2 fix LDLIBS (must come after objs)
# 2012-02-26 458 1.1 add tst_fx2loop_si
# 2011-12-26 445 1.0 Initial version
#
@@ -15,16 +16,19 @@ ISE_PATH = xc3s1200e-fg320-4
all : tst_fx2loop tst_fx2loop_si
#
clean : ise_clean
rm -f tst_fx2loop
rm -f tst_fx2loop_si
#
realclean :
rm -f tst_fx2loop tst_fx2loop_si
#
CFLAGS = -Wall -O2 -g -lusb-1.0
CFLAGS = -Wall -O2 -g
LDLIBS = -lusb-1.0
#
tst_fx2loop : tst_fx2loop.c
${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c
${CC} ${CFLAGS} -o tst_fx2loop tst_fx2loop.c ${LDLIBS}
tst_fx2loop_si : tst_fx2loop_si.c
${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c
${CC} ${CFLAGS} -o tst_fx2loop_si tst_fx2loop_si.c ${LDLIBS}
#
#----
#

4
rtl/sys_gen/tst_rlink_cuff/atlys/ic/.cvsignore Normal file
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_impactbatch.log
sys_tst_rlink_cuff_ic_atlys.ucf
*.dep_ucf_cpp
*.svf

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rtl/sys_gen/tst_rlink_cuff/atlys/ic/Makefile Normal file
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# $Id: Makefile 472 2013-01-06 14:39:10Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-01-06 472 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = atlys
ISE_PATH = xc6slx45-csg324-2
FX2_FILE = nexys3_jtag_2fifo_ic.ihx
#
XFLOWOPT_SYN = syn_s6_speed.opt
XFLOWOPT_IMP = imp_s6_speed.opt
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

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rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_conf.vhd Normal file
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-- $Id: sys_conf.vhd 472 2013-01-06 14:39:10Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_atlys (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-06 472 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

97
rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.mfset Normal file
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# $Id: sys_tst_rlink_cuff_ic_atlys.mfset 472 2013-01-06 14:39:10Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
Case statement is complete. others clause is never selected
Using initial value '0' for reset since it is never assigned
Using initial value '0' for fx2_tx2ena_l since it is never assigned
Net <FX2_TX2BUSY> does not have a driver.
Output port <LOCKED> of the instance <DCM> is unconnected
Output port <RXAEMPTY> of the instance <FX2_CNTL_IC.CNTL> is unconnected
Output port <TXAFULL> of the instance <FX2_CNTL_IC.CNTL> is unconnected
Output port <FX2_TX2DATA> of the instance <TST> is unconnected
Output port <FX2_TX2ENA> of the instance <TST> is unconnected
Output port <SIZER> of the instance <TXFIFO> is unconnected
Output port <DOA> of the instance <RAM> is unconnected
Output port <RL_MONI_eop> of the instance <RLCORE> is unconnected
Output port <RL_MONI_attn> of the instance <RLCORE> is unconnected
Output port <RL_MONI_lamp> of the instance <RLCORE> is unconnected
Output port <MONI_rxerr> of the instance <SERPORT> is unconnected
Output port <MONI_rxovr> of the instance <SERPORT> is unconnected
Output port <MONI_abdone> of the instance <SERPORT> is unconnected
Output port <SIZE> of the instance <TXFIFO> is unconnected or connected
Output port <SIZE> of the instance <FIFO> is unconnected or connected
Output port <DOB> of the instance <BRAM> is unconnected
Signal <FX2_TX2DATA> is used but never assigned
Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_atlys'
Node <FX2_CNTL_IC.CNTL/R_MONI_[CS]_.*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_sel> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_pf> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_pf> of sequential type is unconnected
ode <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_sel> of sequential type is unconnected
Node <IOB_FX2_FLAG/R_DI_3> of sequential type is unconnected
Node <HIO/R_REGS_swieff_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS_btn_[0-4]> of sequential type is unconnected
Node <HIO/R_REGS_swi_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS_btneff_[0-4]> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_size[rw]_\d> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_monattn> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_monlamp> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_moneop> of sequential type is unconnected
Node <TST/SERPORT/XONRX/R_REGS_rxovr> of sequential type is unconnected
Input <RB_MREQ_init> is never used
Input <RB_MREQ_din<15:10>> is never used
Input <SWI<7:3>> is never used
Input <SWI<0:0>> is never used
Input <BTN<3:0>> is never used
Input <FX2_MONI_fifo_ep4> is never used
Input <FX2_MONI_fifo_ep6> is never used
Input <FX2_MONI_fifo_ep8> is never used
Input <FX2_MONI_flag_ep4_empty> is never used
Input <FX2_MONI_flag_ep4_almost> is never used
Input <FX2_MONI_flag_ep6_full> is never used
Input <FX2_MONI_flag_ep6_almost> is never used
Input <FX2_MONI_flag_ep8_full> is never used
Input <FX2_MONI_flag_ep8_almost> is never used
Input <FX2_MONI_slrd> is never used
Input <FX2_MONI_slwr> is never used
Input <FX2_MONI_pktend> is never used
FF/Latch <R_MONI_[CS]_.*> has a constant value of 0
FF/Latch <TX2ENA_PSTR/R_REGS_busy_1> has a constant value
FF/Latch <TX2ENA_PSTR/R_REGS_busy_0> has a constant value
of type RAMB16_S18 has been replaced by RAMB16BWER
of type RAMB16_S36 has been replaced by RAMB16BWER
of type RAMB16_S36_S36 has been replaced by RAMB16BWER
FF/Latch <HIO/R_REGS_ledin_[2-6]> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_rst.*> has a constant value
The FF/Latch <R_REGS_rbre> .* is equivalent
The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[01]> .* is equivalent
#
# ----------------------------------------------------------------------------
[tra]
#
# ----------------------------------------------------------------------------
[map]
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
The signal I_FX2_FLAG<3>_IBUF has no load
There are 1 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]

24
rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.ucf_cpp Normal file
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## $Id: sys_tst_rlink_cuff_ic_atlys.ucf_cpp 472 2013-01-06 14:39:10Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-01-06 472 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## std board
##
#include "bplib/atlys/atlys_pins.ucf"
##
## Pmod A0 - RS232
##
#include "bplib/atlys/atlys_pins_pma0_rs232.ucf"
##
## FX2 interface
##
#include "bplib/atlys/atlys_pins_fx2.ucf"
#include "bplib/atlys/atlys_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_rlink_cuff/atlys/ic/sys_tst_rlink_cuff_ic_atlys.vbom Normal file
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# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_rlink_cuff_atlys.vbom
@ucf_cpp: sys_tst_rlink_cuff_ic_atlys.ucf
@top: sys_tst_rlink_cuff_atlys

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rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vbom Normal file
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# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./as/sys_tst_rlink_cuff_as_atlys
# ./ic/sys_tst_rlink_cuff_ic_atlys
# ./ic3/sys_tst_rlink_cuff_ic3_atlys
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../vlib/rbus/rblib.vhd
../../../bplib/fx2lib/fx2lib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_demu_rbus.vbom
../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../tst_rlink_cuff.vbom
# design
sys_tst_rlink_cuff_atlys.vhd
## no @ucf_cpp

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rtl/sys_gen/tst_rlink_cuff/atlys/sys_tst_rlink_cuff_atlys.vhd Normal file
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-- $Id: sys_tst_rlink_cuff_atlys.vhd 472 2013-01-06 14:39:10Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_atlys - syn
-- Description: rlink tester design for atlys with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-01-06 472 13.3 O76d xc6slx45 ??? ???? ??? ???? p ??.? ic2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-06 472 1.0 Initial version; derived from sys_tst_rlink_cuff_n3
-- and sys_tst_fx2loop_atlys
------------------------------------------------------------------------------
-- Usage of Atlys Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_atlys is -- top level
-- implements atlys_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_USB_RXD : in slbit; -- USB UART receive data (board view)
O_USB_TXD : out slbit; -- USB UART transmit data (board view)
I_HIO_SWI : in slv8; -- atlys hio switches
I_HIO_BTN : in slv6; -- atlys hio buttons
O_HIO_LED: out slv8; -- atlys hio leds
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_atlys;
architecture syn of sys_tst_rlink_cuff_atlys is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_USB_RXD,
O_TXD0 => O_USB_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_demu_rbus
generic map (
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_HIO_SWI,
I_BTN => I_HIO_BTN,
O_LED => O_HIO_LED
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
end syn;

6
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/.cvsignore Normal file
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tb_tst_rlink_cuff_ic_n2
tb_tst_rlink_cuff_ic_n2_[sft]sim
rlink_cext_fifo_rx
rlink_cext_fifo_tx
rlink_cext_conf
*.dep_ucf_cpp

30
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/Makefile Normal file
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# $Id: Makefile 467 2013-01-02 19:49:05Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-01-01 467 1.0 Initial version
#
EXE_all = tb_tst_rlink_cuff_ic_n2
#
ISE_PATH = xc3s1200e-fg320-4
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean
rm -f sys_tst_rlink_cuff_ic_n2.ucf
#
#-----
#
include $(RETROBASE)/rtl/make/generic_ghdl.mk
include $(RETROBASE)/rtl/make/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
#

60
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_conf_sim.vhd Normal file
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-- $Id: sys_conf_sim.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n2 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

1
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/sys_tst_rlink_cuff_ic_n2.ucf_cpp Symbolic link
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../sys_tst_rlink_cuff_ic_n2.ucf_cpp

7
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vbom Normal file
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# configure tb_nexsy2_fusp with sys_tst_rlink_n2 target;
# use vhdl configure file (tb_tst_rlink_cuff_ic_n2.vhd) to allow
# that all configurations will co-exist in work library
${nexys2_fusp_cuff_aif := ../sys_tst_rlink_cuff_ic_n2.vbom}
sys_conf = sys_conf_sim.vhd
../../../../../bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
tb_tst_rlink_cuff_ic_n2.vhd

40
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2.vhd Normal file
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-- $Id: tb_tst_rlink_cuff_ic_n2.vhd 467 2013-01-02 19:49:05Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_cuff_ic_n2
-- Description: Configuration for tb_tst_rlink_cuff_ic_n2 for
-- tb_nexys2_fusp_cuff
--
-- Dependencies: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2')
--
-- To test: sys_tst_rlink_cuff_n2 (fx2_type = 'ic2')
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2013-01-xx xxx - 0.29 12.1 M53d xc3s1200e u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_cuff_ic_n2 of tb_nexys2_fusp_cuff is
for sim
for all : nexys2_fusp_cuff_aif
use entity work.sys_tst_rlink_cuff_n2;
end for;
end for;
end tb_tst_rlink_cuff_ic_n2;

6
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tb_tst_rlink_cuff_ic_n2_ssim.vbom Normal file
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@@ -0,0 +1,6 @@
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n2.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
nexys2_aif = sys_tst_rlink_cuff_ic_n2_ssim.vhd
tb_tst_rlink_cuff_ic_n2.vbom
@top:tb_tst_rlink_cuff_ic_n2

6
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb/tbw.dat Normal file
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@@ -0,0 +1,6 @@
# $Id: tbw.dat 467 2013-01-02 19:49:05Z mueller $
#
[tb_tst_rlink_cuff_ic_n2]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>

4
rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/.cvsignore Normal file
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@@ -0,0 +1,4 @@
_impactbatch.log
sys_tst_rlink_cuff_ic3_n2.ucf
*.dep_ucf_cpp
*.svf

29
rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/Makefile Normal file
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@@ -0,0 +1,29 @@
# $Id: Makefile 466 2012-12-30 13:26:55Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-12-29 466 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys2
ISE_PATH = xc3s1200e-fg320-4
FX2_FILE = nexys2_jtag_3fifo_ic.ihx
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

62
rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_conf.vhd Normal file
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@@ -0,0 +1,62 @@
-- $Id: sys_conf.vhd 466 2012-12-30 13:26:55Z mueller $
--
-- Copyright 2012- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic3_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic3";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

97
rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.mfset Normal file
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# $Id: sys_tst_rlink_cuff_ic3_n2.mfset 469 2013-01-05 12:29:44Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
Unconnected output port 'RL_MONI' of component 'rlink_core8'
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
Input <RB_MREQ.init> is never used
Input <BTN> is never used
Input <SWI<7:3>> is never used
Input <SWI<0>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <FX2_MONI.flag_ep4_empty> is never used
Input <FX2_MONI.flag_ep4_almost> is never used
Input <FX2_MONI.flag_ep6_full> is never used
Input <FX2_MONI.flag_ep6_almost> is never used
Input <FX2_MONI.flag_ep8_full> is never used
Input <FX2_MONI.flag_ep8_almost> is never used
Input <FX2_MONI.fifo_ep4> is never used
Input <FX2_MONI.fifo_ep6> is never used
Input <FX2_MONI.fifo_ep8> is never used
Output <FX2_TX2DATA> is never assigned
Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <RB_LAM_TEST<1:0>> is assigned but never used
Signal <SER_MONI.rxovr> is assigned but never used
Signal <SER_MONI.rxerr> is assigned but never used
Signal <SER_MONI.abdone> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <FX2_TXAFULL> is assigned but never used
Signal <FX2_RXAEMPTY> is assigned but never used
Signal <TXSIZE_FX2> is assigned but never used
Signal <TX2SIZE_FX2> is assigned but never used
Signal <FX2_TX2AFULL> is assigned but never used
Signal <FX2_TX2ENA_L> is used but never assigned
Signal <RESET> is used but never assigned
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <R_REGS.ucnt_6> has a constant value of 0
FF/Latch <HIO/R_REGS.ledin_[2-6]> has a constant value of 0
FF/Latch <FX2_CNTL_IC3.CNTL/(RX|TX|TX2)FIFO/R_REG[RW].rst[rw]> has a constant value of 0
FF/Latch <FX2_CNTL_IC3.CNTL/(RX|TX|TX2)FIFO/R_REG[RW].rst[rw]_(c|s|sc|ss)> has a constant value of 0
FF/Latch <FX2_CNTL_IC3.CNTL/TX2FIFO/GCW/GRAY_5.CNT/R_DATA_[0-4]> has a constant value
FF/Latch <FX2_CNTL_IC3.CNTL/TX2FIFO/R_REGR.waddr_[cs]_[0-4]> has a constant value
Node <HIO/R_REGS.swieff_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.swi_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-3]> of sequential type is unconnected
Node <HIO/R_REGS.btneff_[0-3]> of sequential type is unconnected
Node <TST/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.moneop> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monlamp> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monattn> of sequential type is unconnected
Node <FX2_CNTL_IC3.CNTL/R_MONI_S..*> of sequential type is unconnected
Node <FX2_CNTL_IC3.CNTL/R_MONI_C..*> of sequential type is unconnected
Node <FX2_CNTL_IC3.CNTL/R_REGS..*> of sequential type is unconnected
Node <FX2_CNTL_IC3.CNTL/(RX|TX|TX2)FIFO/R_REG[RW].size[rw]_[0-4]> of sequential type is unconnected
RAMs <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM0>, <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM1> are equivalent
RAMs <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM0>, <FX2_CNTL_IC3.CNTL/TX2FIFO/RAM/AW_5.GL\[\d\].MEM0> are equivalent
#
# ----------------------------------------------------------------------------
[tra]
#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete

22
rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.ucf_cpp Normal file
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@@ -0,0 +1,22 @@
## $Id: sys_tst_rlink_cuff_ic3_n2.ucf_cpp 466 2012-12-30 13:26:55Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2012-12-29 466 1.0 Initial version
##
NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
#include "bplib/nexys2/nexys2_pins.ucf"
##
## Pmod B0 - RS232
##
#include "bplib/nexys2/nexys2_pins_pmb0_rs232.ucf"
##
## Cypress FX2
##
#include "bplib/nexys2/nexys2_pins_fx2.ucf"
#include "bplib/nexys2/nexys2_time_fx2_ic.ucf"

8
rtl/sys_gen/tst_rlink_cuff/nexys2/ic3/sys_tst_rlink_cuff_ic3_n2.vbom Normal file
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@@ -0,0 +1,8 @@
# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_rlink_cuff_n2.vbom
@ucf_cpp: sys_tst_rlink_cuff_ic3_n2.ucf
@top: sys_tst_rlink_cuff_n2

3
rtl/sys_gen/tst_rlink_cuff/nexys2/sys_tst_rlink_cuff_n2.vhd
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@@ -1,4 +1,4 @@
-- $Id: sys_tst_rlink_cuff_n2.vhd 467 2013-01-02 19:49:05Z mueller $
-- $Id: sys_tst_rlink_cuff_n2.vhd 469 2013-01-05 12:29:44Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,6 +32,7 @@
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-01-04 469 13.3 O76d xc3s1200e-4 846 1798 160 1215 p 16.3 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 808 1739 160 1172 p 16.3 as2/ 50
-- 2013-01-02 467 13.3 O76d xc3s1200e-4 843 1792 160 1209 p 15.2 ic2/ 50
-- 2012-12-29 466 13.3 O76d xc3s1200e-4 863 1850 192 1266 p 13.6 ic3/ 50

4
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/.cvsignore Normal file
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@@ -0,0 +1,4 @@
_impactbatch.log
sys_tst_rlink_cuff_ic_n3.ucf
*.dep_ucf_cpp
*.svf

32
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/Makefile Normal file
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@@ -0,0 +1,32 @@
# $Id: Makefile 469 2013-01-05 12:29:44Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-01-04 469 1.0 Initial version
#
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
ISE_BOARD = nexys3
ISE_PATH = xc6slx16-csg324-2
FX2_FILE = nexys3_jtag_2fifo_ic.ihx
#
XFLOWOPT_SYN = syn_s6_speed.opt
XFLOWOPT_IMP = imp_s6_speed.opt
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include $(RETROBASE)/rtl/make/generic_xflow.mk
include $(RETROBASE)/rtl/make/generic_ghdl.mk
#
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
#

62
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd Normal file
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@@ -0,0 +1,62 @@
-- $Id: sys_conf.vhd 469 2013-01-05 12:29:44Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_fx2_type : string := "ic2";
-- dummy values defs for generic parameters of as controller
constant sys_conf_fx2_rdpwldelay : positive := 1;
constant sys_conf_fx2_rdpwhdelay : positive := 1;
constant sys_conf_fx2_wrpwldelay : positive := 1;
constant sys_conf_fx2_wrpwhdelay : positive := 1;
constant sys_conf_fx2_flagdelay : positive := 1;
-- pktend timer setting
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

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# $Id: sys_tst_rlink_cuff_ic_n3.mfset 472 2013-01-06 14:39:10Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
Case statement is complete. others clause is never selected
Using initial value '0' for reset since it is never assigned
Using initial value '0' for fx2_tx2ena_l since it is never assigned
Net <FX2_TX2BUSY> does not have a driver.
Output port <LOCKED> of the instance <DCM> is unconnected
Output port <RXAEMPTY> of the instance <FX2_CNTL_IC.CNTL> is unconnected
Output port <TXAFULL> of the instance <FX2_CNTL_IC.CNTL> is unconnected
Output port <FX2_TX2DATA> of the instance <TST> is unconnected
Output port <FX2_TX2ENA> of the instance <TST> is unconnected
Output port <SIZER> of the instance <TXFIFO> is unconnected
Output port <DOA> of the instance <RAM> is unconnected
Output port <RL_MONI_eop> of the instance <RLCORE> is unconnected
Output port <RL_MONI_attn> of the instance <RLCORE> is unconnected
Output port <RL_MONI_lamp> of the instance <RLCORE> is unconnected
Output port <MONI_rxerr> of the instance <SERPORT> is unconnected
Output port <MONI_rxovr> of the instance <SERPORT> is unconnected
Output port <MONI_abdone> of the instance <SERPORT> is unconnected
Output port <SIZE> of the instance <TXFIFO> is unconnected or connected
Output port <SIZE> of the instance <FIFO> is unconnected or connected
Output port <DOB> of the instance <BRAM> is unconnected
Signal <FX2_TX2DATA> is used but never assigned
Signal 'FX2_TX2BUSY', unconnected in block 'sys_tst_rlink_cuff_n3'
Node <FX2_CNTL_IC.CNTL/R_MONI_[CS]_.*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_sel> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_pf> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_pf> of sequential type is unconnected
ode <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_sel> of sequential type is unconnected
Node <IOB_FX2_FLAG/R_DI_3> of sequential type is unconnected
Node <HIO/R_REGS_swieff_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS_btn_[0-4]> of sequential type is unconnected
Node <HIO/R_REGS_swi_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS_btneff_[0-4]> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_size[rw]_\d> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_monattn> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_monlamp> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_moneop> of sequential type is unconnected
Node <TST/SERPORT/XONRX/R_REGS_rxovr> of sequential type is unconnected
Input <RB_MREQ_init> is never used
Input <RB_MREQ_din<15:10>> is never used
Input <I_MEM_WAIT> is never used
Input <SWI<7:3>> is never used
Input <SWI<0:0>> is never used
Input <BTN<3:0>> is never used
Input <FX2_MONI_fifo_ep4> is never used
Input <FX2_MONI_fifo_ep6> is never used
Input <FX2_MONI_fifo_ep8> is never used
Input <FX2_MONI_flag_ep4_empty> is never used
Input <FX2_MONI_flag_ep4_almost> is never used
Input <FX2_MONI_flag_ep6_full> is never used
Input <FX2_MONI_flag_ep6_almost> is never used
Input <FX2_MONI_flag_ep8_full> is never used
Input <FX2_MONI_flag_ep8_almost> is never used
Input <FX2_MONI_slrd> is never used
Input <FX2_MONI_slwr> is never used
Input <FX2_MONI_pktend> is never used
FF/Latch <R_MONI_[CS]_.*> has a constant value of 0
FF/Latch <TX2ENA_PSTR/R_REGS_busy_1> has a constant value
FF/Latch <TX2ENA_PSTR/R_REGS_busy_0> has a constant value
of type RAMB16_S18 has been replaced by RAMB16BWER
of type RAMB16_S36 has been replaced by RAMB16BWER
of type RAMB16_S36_S36 has been replaced by RAMB16BWER
FF/Latch <HIO/R_REGS_ledin_[2-6]> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_rst.*> has a constant value
The FF/Latch <R_REGS_rbre> .* is equivalent
The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[01]> .* is equivalent
The FF/Latch <HIO/HIO/DRV/R_REGS_cdiv_0> .* is the opposite
#
# ----------------------------------------------------------------------------
[tra]
#
# ----------------------------------------------------------------------------
[map]
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
The signal I_FX2_FLAG<3>_IBUF has no load
There are 2 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]

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## $Id: sys_tst_rlink_cuff_ic_n3.ucf_cpp 469 2013-01-05 12:29:44Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-01-04 469 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## Pmod B0 - RS232
##
#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
##
## FX2 interface
##
#include "bplib/nexys3/nexys3_pins_fx2.ucf"
#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"

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# conf
sys_conf = sys_conf.vhd
# libs
# components
# design
../sys_tst_rlink_cuff_n3.vbom
@ucf_cpp: sys_tst_rlink_cuff_ic_n3.ucf
@top: sys_tst_rlink_cuff_n3

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# this is the vbom for the 'generic' top level entity
# to be referenced in the vbom's of the specific systems
# ./as/sys_tst_rlink_cuff_as_n3
# ./ic/sys_tst_rlink_cuff_ic_n3
# ./ic3/sys_tst_rlink_cuff_ic3_n3
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../bplib/bpgen/bpgenlib.vbom
../../../vlib/rbus/rblib.vhd
../../../bplib/fx2lib/fx2lib.vhd
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
../../../bplib/fx2lib/fx2_2fifoctl_as.vbom
../../../bplib/fx2lib/fx2_2fifoctl_ic.vbom
../../../bplib/fx2lib/fx2_3fifoctl_ic.vbom
../tst_rlink_cuff.vbom
../../../bplib/nxcramlib/nx_cram_dummy.vbom
# design
sys_tst_rlink_cuff_n3.vhd
## no @ucf_cpp

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-- $Id: sys_tst_rlink_cuff_n3.vhd 469 2013-01-05 12:29:44Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_rlink_cuff_n3 - syn
-- Description: rlink tester design for nexys3 with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- tst_rlink_cuff
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-01-04 469 13.3 O76d xc3s1200e-4 ??? ???? ??? ???? p ??.? ic2/ 50
--
-- Revision History:
-- Date Rev Version Comment
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_rlink_cuff_n2
-- and sys_tst_fx2loop_n3
------------------------------------------------------------------------------
-- Usage of Nexys 3 Switches, Buttons, LEDs:
--
-- SWI(7:3) no function (only connected to sn_humanio_rbus)
-- (2) 0 -> int/ext RS242 port for rlink
-- 1 -> use USB interface for rlink
-- (1) 1 enable XON
-- (0) 0 -> main board RS232 port - implemented in bp_rs232_2l4l_iob
-- 1 -> Pmod B/top RS232 port /
--
-- LED(7) SER_MONI.abact
-- (6:2) no function (only connected to sn_humanio_rbus)
-- (0) timer 0 busy
-- (1) timer 1 busy
--
-- DSP: SER_MONI.clkdiv (from auto bauder)
-- for SWI(2)='0' (serport)
-- DP(3) not SER_MONI.txok (shows tx back preasure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back preasure)
-- (0) SER_MONI.rxact (shows rx activity)
-- for SWI(2)='1' (fx2)
-- DP(3) FX2_TX2BUSY (shows tx2 back preasure)
-- (2) FX2_TX2ENA(stretched) (shows tx2 activity)
-- (1) FX2_TXENA(streched) (shows tx activity)
-- (0) FX2_RXVAL(stretched) (shows rx activity)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.rblib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_rlink_cuff_n3 is -- top level
-- implements nexys3_fusp_cuff_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_rlink_cuff_n3;
architecture syn of sys_tst_rlink_cuff_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal RXSD : slbit := '0';
signal TXSD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '0';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
constant rbaddr_hio : slv8 := "11000000"; -- 110000xx
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 7, -- good for up to 127 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLK,
RESET => '0',
SEL => SWI(0),
RXD => RXSD,
TXD => TXSD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
HIO : sn_humanio_rbus
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce,
RB_ADDR => rbaddr_hio)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_HIO,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
TST : entity work.tst_rlink_cuff
port map (
CLK => CLK,
RESET => '0',
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RB_MREQ_TOP => RB_MREQ,
RB_SRES_TOP => RB_SRES_HIO,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
RXSD => RXSD,
TXSD => TXSD,
RTS_N => RTS_N,
CTS_N => CTS_N,
FX2_RXDATA => FX2_RXDATA,
FX2_RXVAL => FX2_RXVAL,
FX2_RXHOLD => FX2_RXHOLD,
FX2_TXDATA => FX2_TXDATA,
FX2_TXENA => FX2_TXENA,
FX2_TXBUSY => FX2_TXBUSY,
FX2_TX2DATA => FX2_TX2DATA,
FX2_TX2ENA => FX2_TX2ENA,
FX2_TX2BUSY => FX2_TX2BUSY,
FX2_MONI => FX2_MONI
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
end syn;