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add MIG support for Nexys4 DDR

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wfjm
2019-01-12 09:48:18 +01:00
parent dd7cdfeceb
commit 3a8da10b96
17 changed files with 1056 additions and 11 deletions
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7
doc/CHANGELOG.md
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@@ -21,9 +21,10 @@ software or firmware builds or that the documentation is consistent.
The full set of tests is only run for tagged releases.
### Summary
- add support DDR memory via Vivado MIG cores
- arty board support
- add w11a, tst_sram and tst_mig systems
- add support for DDR memory via Vivado MIG cores for
- Digilent Arty
- Digilent Nexys4 DDR
- add a low level MIG interface test design
### New features
- new systems

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rtl/bplib/nexys4d/mig_a.prj Normal file
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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>migui_nexys4d</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>ON</LowPower_En>
<XADC_En>Disabled</XADC_En>
<TargetFPGA>xc7a100t-csg324/-1</TargetFPGA>
<Version>4.0</Version>
<SystemClock>No Buffer</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR2_SDRAM/Components/MT47H64M16HR-25E</MemoryDevice>
<TimePeriod>3333</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>150.015</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>1200</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Strict</Ordering>
<BankMachineCnt>2</BankMachineCnt>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M4" SLEW="" name="ddr2_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R2" SLEW="" name="ddr2_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K5" SLEW="" name="ddr2_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N6" SLEW="" name="ddr2_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P4" SLEW="" name="ddr2_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M6" SLEW="" name="ddr2_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T1" SLEW="" name="ddr2_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L3" SLEW="" name="ddr2_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P5" SLEW="" name="ddr2_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M2" SLEW="" name="ddr2_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N1" SLEW="" name="ddr2_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L4" SLEW="" name="ddr2_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N5" SLEW="" name="ddr2_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P2" SLEW="" name="ddr2_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="P3" SLEW="" name="ddr2_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R1" SLEW="" name="ddr2_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="L1" SLEW="" name="ddr2_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L5" SLEW="" name="ddr2_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="L6" SLEW="" name="ddr2_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M1" SLEW="" name="ddr2_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="K6" SLEW="" name="ddr2_cs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T6" SLEW="" name="ddr2_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U1" SLEW="" name="ddr2_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R7" SLEW="" name="ddr2_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V5" SLEW="" name="ddr2_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U4" SLEW="" name="ddr2_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V4" SLEW="" name="ddr2_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T4" SLEW="" name="ddr2_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V1" SLEW="" name="ddr2_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T3" SLEW="" name="ddr2_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V6" SLEW="" name="ddr2_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R8" SLEW="" name="ddr2_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U7" SLEW="" name="ddr2_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="V7" SLEW="" name="ddr2_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R6" SLEW="" name="ddr2_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U6" SLEW="" name="ddr2_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="R5" SLEW="" name="ddr2_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="T5" SLEW="" name="ddr2_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="U3" SLEW="" name="ddr2_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V9" SLEW="" name="ddr2_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="V2" SLEW="" name="ddr2_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U9" SLEW="" name="ddr2_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL18_II" PADName="U2" SLEW="" name="ddr2_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="M3" SLEW="" name="ddr2_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N4" SLEW="" name="ddr2_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL18_II" PADName="N2" SLEW="" name="ddr2_we_n" IN_TERM="" />
</PinSelection>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="10" trefi="7.8" tfaw="45" trtp="7.5" trfc="127.5" trp="12.5" tras="40" trcd="15" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8</mrBurstLength>
<mrBurstType name="Burst Type" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >5</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="PD Mode" >Fast exit</mrPdMode>
<mrWriteRecovery name="Write Recovery" >5</mrWriteRecovery>
<emrDllEnable name="DLL Enable" >Enable-Normal</emrDllEnable>
<emrOutputDriveStrength name="Output Drive Strength" >Fullstrength</emrOutputDriveStrength>
<emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
<emrCKSelection name="Memory Clock Selection" >1</emrCKSelection>
<emrRTT name="RTT (nominal) - ODT" >50ohms</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="OCD Operation" >OCD Exit</emrOCD>
<emrDQS name="DQS# Enable" >Enable</emrDQS>
<emrRDQS name="RDQS Enable" >Disable</emrRDQS>
<emrOutputs name="Outputs" >Enable</emrOutputs>
<PortInterface>NATIVE</PortInterface>
</Controller>
</Project>

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rtl/bplib/nexys4d/mig_nexys4d.tcl Normal file
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# $Id: mig_nexys4d.tcl 1099 2018-12-31 09:07:36Z mueller $
#
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2018-12-30 1099 1.0 Initial version (cloned from arty)
#
# defined tested MIG versions with project files
set tdsc_list { "4.0" "mig_a.prj" \
"4.1" "mig_a.prj" \
"4.2" "mig_a.prj" }
# determine available MIG version (only latest supported !!)
set vlnv [get_ipdefs "xilinx.com:ip:mig_7series:*"]
set vers [lindex [split $vlnv ":"] 3]
# filter out matching MIG version
set mprj {}
foreach {tver tprj} $tdsc_list {
lappend tver_list $tver
if {$vers eq $tver} { set mprj $tprj }
}
puts [format "## tested MIG versions: %s" [join $tver_list " "]]
puts [format "## available MIG version: %s" $vers]
if {$mprj ne ""} {
puts [format "## selected MIG version: %s with %s" $vers $mprj]
} else {
error "mig_nexys4d: no tested MIG version found"
}
create_ip -vlnv "xilinx.com:ip:mig_7series:$vers" -module_name migui_nexys4d
set ip_dir [get_property IP_DIR [ get_ips ips migui_nexys4d]]
##puts "ip_dir: $ip_dir"
puts "## migui: copy $mprj to IP_DIR"
file copy $mprj "$ip_dir/$mprj"
puts "## migui: set_property"
set_property -dict [list \
CONFIG.XML_INPUT_FILE $mprj \
CONFIG.RESET_BOARD_INTERFACE {Custom} \
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
CONFIG.BOARD_MIG_PARAM {Custom} \
] \
[get_ips migui_nexys4d]
puts "## migui: generate_target"
generate_target {instantiation_template} \
[get_files "$ip_dir/migui_nexys4d.xci"]
puts "## migui: export_ip_user_files"
export_ip_user_files -of_objects \
[get_files "$ip_dir/migui_nexys4d.xci"] \
-no_script -sync -force -quiet

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rtl/bplib/nexys4d/miglib_nexys4d.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../mig/miglib.vbom
miglib_nexys4d.vhd

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rtl/bplib/nexys4d/miglib_nexys4d.vhd Normal file
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-- $Id: miglib_nexys4d.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: miglib_nexys4d
-- Description: MIG interface components - for nexys4d
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.miglib.all;
package miglib_nexys4d is
constant mig_bawidth : positive := 4; -- byte addr width
constant mig_mawidth : positive := 27; -- mem addr width
constant mig_mwidth : positive := 2**mig_bawidth; -- mask width ( 16)
constant mig_dwidth : positive := 8*mig_mwidth; -- data width (128)
component sramif_mig_nexys4d is -- SRAM to DDR via MIG for nexys4d
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- die temperature
MONI : out sramif2migui_moni_type;-- monitor signals
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end component;
component migui_nexys4d is -- MIG generated for nexys4d
port (
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0); -- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh reques
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI calibration done
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end component;
end package miglib_nexys4d;

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rtl/bplib/nexys4d/migui_nexys4d_gsim.vbom Normal file
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# libs
../../vlib/slvtypes.vhd
../mig/miglib.vbom
miglib_nexys4d.vbom
# components
../mig/migui_core_gsim.vbom
# design
migui_nexys4d_gsim.vhd

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rtl/bplib/nexys4d/migui_nexys4d_gsim.vhd Normal file
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-- $Id: migui_nexys4d_gsim.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: migui_nexys4d - sim
-- Description: MIG generated for nexys4d - simple simulator
--
-- Dependencies: bplib/mig/migui_core_gsim
-- Test bench: tb_tst_sram_nexys4d
-- Target Devices: arty board
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version (cloned from arty)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.miglib.all;
use work.miglib_nexys4d.all;
entity migui_nexys4d is -- MIG generated for nexys4d
port (
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1; -- dram: on-die termination
APP_ADDR : in slv(mig_mawidth-1 downto 0); -- MIGUI address
APP_CMD : in slv3; -- MIGUI command
APP_EN : in slbit; -- MIGUI command enable
APP_WDF_DATA : in slv(mig_dwidth-1 downto 0);-- MIGUI write data
APP_WDF_END : in slbit; -- MIGUI write end
APP_WDF_MASK : in slv(mig_mwidth-1 downto 0); -- MIGUI write mask
APP_WDF_WREN : in slbit; -- MIGUI data write enable
APP_RD_DATA : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
APP_RD_DATA_END : out slbit; -- MIGUI read end
APP_RD_DATA_VALID : out slbit; -- MIGUI read valid
APP_RDY : out slbit; -- MIGUI ready for cmd
APP_WDF_RDY : out slbit; -- MIGUI ready for data write
APP_SR_REQ : in slbit; -- MIGUI reserved (tie to 0)
APP_REF_REQ : in slbit; -- MIGUI refresh request
APP_ZQ_REQ : in slbit; -- MIGUI ZQ calibrate request
APP_SR_ACTIVE : out slbit; -- MIGUI reserved (ignore)
APP_REF_ACK : out slbit; -- MIGUI refresh acknowledge
APP_ZQ_ACK : out slbit; -- MIGUI ZQ calibrate acknowledge
UI_CLK : out slbit; -- MIGUI clock
UI_CLK_SYNC_RST : out slbit; -- MIGUI reset
INIT_CALIB_COMPLETE : out slbit; -- MIGUI inital calibration complete
SYS_CLK_I : in slbit; -- MIGUI system clock
CLK_REF_I : in slbit; -- MIGUI reference clock
DEVICE_TEMP_I : in slv12; -- MIGUI xadc temperature
SYS_RST : in slbit -- MIGUI system reset
);
end migui_nexys4d;
architecture sim of migui_nexys4d is
begin
MIG_SIM : migui_core_gsim
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth,
SAWIDTH => 24,
CLKMUI_MUL => 7,
CLKMUI_DIV => 14)
port map (
SYS_CLK => SYS_CLK_I,
SYS_RST => SYS_RST,
UI_CLK => UI_CLK,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK
);
DDR2_DQ <= (others=>'Z');
DDR2_DQS_P <= (others=>'Z');
DDR2_DQS_N <= (others=>'Z');
DDR2_ADDR <= (others=>'0');
DDR2_BA <= (others=>'0');
DDR2_RAS_N <= '1';
DDR2_CAS_N <= '1';
DDR2_WE_N <= '1';
DDR2_CK_P <= (others=>'0');
DDR2_CK_N <= (others=>'1');
DDR2_CKE <= (others=>'0');
DDR2_CS_N <= (others=>'1');
DDR2_DM <= (others=>'0');
DDR2_ODT <= (others=>'0');
APP_SR_ACTIVE <= '0';
end sim;

11
rtl/bplib/nexys4d/nexys4d_pins.xdc
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@@ -1,7 +1,7 @@
# -*- tcl -*-
# $Id: nexys4d_pins.xdc 838 2017-01-04 20:57:57Z mueller $
# $Id: nexys4d_pins.xdc 1099 2018-12-31 09:07:36Z mueller $
#
# Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Nexys 4DDR core functionality
@@ -14,6 +14,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2018-12-30 1099 1.1 BUFFIX: Fix faulty IO voltage for I_SWI[8,9]
# 2017-01-04 838 1.0 Initial version
#
@@ -38,7 +39,7 @@ set_property DRIVE 12 [get_ports {O_TXD O_RTS_N}]
set_property SLEW SLOW [get_ports {O_TXD O_RTS_N}]
#
# switches -- in bank 14+15 -------------------------------------------------
# switches -- in bank 14+15+34 -------------------------------------------------
set_property PACKAGE_PIN j15 [get_ports {I_SWI[0]}]
set_property PACKAGE_PIN l16 [get_ports {I_SWI[1]}]
set_property PACKAGE_PIN m13 [get_ports {I_SWI[2]}]
@@ -56,7 +57,9 @@ set_property PACKAGE_PIN u12 [get_ports {I_SWI[13]}]
set_property PACKAGE_PIN u11 [get_ports {I_SWI[14]}]
set_property PACKAGE_PIN v10 [get_ports {I_SWI[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}]; # bank 14+15
set_property IOSTANDARD LVCMOS18 [get_ports {I_SWI[8]}]; # bank 34
set_property IOSTANDARD LVCMOS18 [get_ports {I_SWI[9]}]; # bank 34
#
# buttons -- in bank 14+15 --------------------------------------------------

38
rtl/bplib/nexys4d/nexys4dlib.vhd
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@@ -1,4 +1,4 @@
-- $Id: nexys4dlib.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: nexys4dlib.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,10 +16,11 @@
-- Description: Nexys 4DDR components
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Tool versions: viv 2016.2-2017.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.1 add nexys4d_dram_aif
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
@@ -48,4 +49,37 @@ component nexys4d_aif is -- NEXYS 4D, abstract iface, base
);
end component;
component nexys4d_dram_aif is -- NEXYS 4D, abstract iface, base+dram
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end component;
end package nexys4dlib;

13
rtl/bplib/nexys4d/sramif_mig_nexys4d.vbom Normal file
View File

@@ -0,0 +1,13 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/cdclib/cdclib.vhd
../mig/miglib.vbom
miglib_nexys4d.vbom
# components
../mig/sramif2migui_core.vbom
../../vlib/cdclib/cdc_pulse.vbom
../../vlib/cdclib/cdc_value.vbom
@tcl:mig_nexys4d.tcl
[ghdl,vsim]migui_nexys4d_gsim.vbom
# design
sramif_mig_nexys4d.vhd

212
rtl/bplib/nexys4d/sramif_mig_nexys4d.vhd Normal file
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@@ -0,0 +1,212 @@
-- $Id: sramif_mig_nexys4d.vhd 1101 2019-01-02 21:22:37Z mueller $
--
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sramif_mig_nexys4d - syn
-- Description: SRAM to DDR via MIG for nexys4d
--
-- Dependencies: bplib/mig/sramif2migui_core
-- cdclib/cdc_pulse
-- cdclib/cdc_value
-- migui_nexys4d (generated core)
-- Test bench: tb_tst_sram_nexys4d
-- Target Devices: nexys4 DDRboard
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-01-02 1101 1.0.1 Initial version
-- 2018-12-30 1099 1.0 First draft (cloned from arty)
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.miglib.all;
use work.miglib_nexys4d.all;
entity sramif_mig_nexys4d is -- SRAM to DDR via MIG for nexyx4d
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv20; -- address (32 bit word address)
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
CLKMIG : in slbit; -- sys clock for mig core
CLKREF : in slbit; -- ref clock for mig core
TEMP : in slv12; -- xadc die temp for mig core
MONI : out sramif2migui_moni_type;-- monitor signals
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end sramif_mig_nexys4d;
architecture syn of sramif_mig_nexys4d is
signal MIG_BUSY : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_EN : slbit := '0';
signal APP_CMD : slv3 := (others=>'0');
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_WDF_RDY : slbit := '0';
signal APP_WDF_WREN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal UI_CLK_SYNC_RST : slbit := '0';
signal INIT_CALIB_COMPLETE : slbit := '0';
signal SYS_RST : slbit := '0';
signal SYS_RST_BUSY : slbit := '0';
signal CLKMUI : slbit := '0';
signal TEMP_MUI : slv12 := (others=>'0'); -- xadc die temp; on CLKMUI
begin
SR2MIG: sramif2migui_core -- SRAM to MIG iface -----------------
generic map (
BAWIDTH => mig_bawidth,
MAWIDTH => mig_mawidth)
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => MIG_BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
MONI => MONI,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
APP_RDY => APP_RDY,
APP_EN => APP_EN,
APP_CMD => APP_CMD,
APP_ADDR => APP_ADDR,
APP_WDF_RDY => APP_WDF_RDY,
APP_WDF_WREN => APP_WDF_WREN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_END => APP_WDF_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END
);
CDC_SYSRST: cdc_pulse
generic map (
POUT_SINGLE => false,
BUSY_WACK => true)
port map (
CLKM => CLK,
RESET => '0',
CLKS => CLKMIG,
PIN => RESET,
BUSY => SYS_RST_BUSY,
POUT => SYS_RST
);
CDC_TEMP: cdc_value
generic map (
DWIDTH => TEMP'length)
port map (
CLKI => CLK,
CLKO => CLKMUI,
DI => TEMP,
DO => TEMP_MUI,
UPDT => open
);
MIG_CTL: migui_nexys4d
port map (
DDR2_DQ => DDR2_DQ,
DDR2_DQS_P => DDR2_DQS_P,
DDR2_DQS_N => DDR2_DQS_N,
DDR2_ADDR => DDR2_ADDR,
DDR2_BA => DDR2_BA,
DDR2_RAS_N => DDR2_RAS_N,
DDR2_CAS_N => DDR2_CAS_N,
DDR2_WE_N => DDR2_WE_N,
DDR2_CK_P => DDR2_CK_P,
DDR2_CK_N => DDR2_CK_N,
DDR2_CKE => DDR2_CKE,
DDR2_CS_N => DDR2_CS_N,
DDR2_DM => DDR2_DM,
DDR2_ODT => DDR2_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => '0',
APP_REF_REQ => '0',
APP_ZQ_REQ => '0',
APP_SR_ACTIVE => open,
APP_REF_ACK => open,
APP_ZQ_ACK => open,
UI_CLK => CLKMUI,
UI_CLK_SYNC_RST => UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => TEMP_MUI,
SYS_RST => SYS_RST
);
BUSY <= MIG_BUSY or SYS_RST_BUSY;
end syn;

1
rtl/bplib/nexys4d/tb/.gitignore vendored
View File

@@ -1 +1,2 @@
tb_nexys4d_dummy
tb_nexys4d_dram_dummy

4
rtl/bplib/nexys4d/tb/Makefile
View File

@@ -1,10 +1,10 @@
# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $
# $Id: Makefile 1099 2018-12-31 09:07:36Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2017-01-04 838 1.0 Initial version
#
EXE_all = tb_nexys4d_dummy
EXE_all = tb_nexys4d_dummy tb_nexys4d_dram_dummy
#
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk
#

4
rtl/bplib/nexys4d/tb/nexys4d_dram_dummy.vbom Normal file
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@@ -0,0 +1,4 @@
# libs
../../../vlib/slvtypes.vhd
# design
nexys4d_dram_dummy.vhd

96
rtl/bplib/nexys4d/tb/nexys4d_dram_dummy.vhd Normal file
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@@ -0,0 +1,96 @@
-- $Id: nexys4d_dram_dummy.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys4d_dram_dummy - syn
-- Description: nexys4d target (base; serport loopback, dram project)
--
-- Dependencies: -
-- To test: tb_nexys4d_dram
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nexys4d_dram_dummy is -- NEXYS 4DDR dummy (base+dram)
-- implements nexys4d_dram_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end nexys4d_dram_dummy;
architecture syn of nexys4d_dram_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
DDR2_DQ <= (others=>'Z');
DDR2_DQS_P <= (others=>'Z');
DDR2_DQS_N <= (others=>'Z');
DDR2_ADDR <= (others=>'0');
DDR2_BA <= (others=>'0');
DDR2_RAS_N <= '1';
DDR2_CAS_N <= '1';
DDR2_WE_N <= '1';
DDR2_CK_P <= (others=>'0');
DDR2_CK_N <= (others=>'1');
DDR2_CKE <= (others=>'0');
DDR2_CS_N <= (others=>'1');
DDR2_DM <= (others=>'0');
DDR2_ODT <= (others=>'0');
end syn;

23
rtl/bplib/nexys4d/tb/tb_nexys4d_dram.vbom Normal file
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@@ -0,0 +1,23 @@
# Not meant for direct top level usage. Used with
# tb_nexys4d_dram_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4dlib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/sfs_gsim_core.vbom
tb_nexys4d_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
${nexys4d_dram_aif := nexys4d_dram_dummy.vbom} -UUT
# design
tb_nexys4d_dram.vhd
@top:tb_nexys4d_dram

212
rtl/bplib/nexys4d/tb/tb_nexys4d_dram.vhd Normal file
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@@ -0,0 +1,212 @@
-- $Id: tb_nexys4d_dram.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d_dram - sim
-- Description: Test bench for nexys4d (base+dram)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/sfs_gsim_core
-- tb_nexys4d_core
-- serport/tb/serport_master_tb
-- nexys4d_dram_aif [UUT]
--
-- To test: generic, any nexys4d_dram_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2-2018.2; ghdl 0.33-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4dlib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4d_dram is
end tb_nexys4d_dram;
architecture sim of tb_nexys4d_dram is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal IO_DDR2_DQ : slv16 := (others=>'Z');
signal IO_DDR2_DQS_P : slv2 := (others=>'Z');
signal IO_DDR2_DQS_N : slv2 := (others=>'Z');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : sfs_gsim_core
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4d_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4d_dram_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
DDR2_DQ => IO_DDR2_DQ,
DDR2_DQS_P => IO_DDR2_DQS_P,
DDR2_DQS_N => IO_DDR2_DQS_N,
DDR2_ADDR => open,
DDR2_BA => open,
DDR2_RAS_N => open,
DDR2_CAS_N => open,
DDR2_WE_N => open,
DDR2_CK_P => open,
DDR2_CK_N => open,
DDR2_CKE => open,
DDR2_CS_N => open,
DDR2_DM => open,
DDR2_ODT => open
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;