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- interim release w11a_V0.532 (untagged)

Browse Source 
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
This commit is contained in:
Walter F.J. Mueller
2011-11-20 12:31:43 +00:00
parent e15295649e
commit 3f455d5236
166 changed files with 2672 additions and 1029 deletions
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61
rtl/bplib/atlys/atlys_pins.ucf Normal file
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@@ -0,0 +1,61 @@
## $Id: atlys_pins.ucf 414 2011-10-11 19:38:12Z mueller $
##
## Pin locks for Atlys core functionality
## - USB UART
## - human I/O (switches, buttons, leds)
##
## Revision History:
## Date Rev Version Comment
## 2011-10-10 413 1.0.2 new BTN sequence: clockwise(U-R-D-L) - mid - reset
## 2011-08-05 403 1.0.1 Fix IOSTANDARD typos; rename _GPIO_ to _HIO_
## 2011-08-04 402 1.0 Initial version
##
## Notes:
## - Bank 0+1 are 3V3; Bank 2 switchable 3V3 or 2V5; Bank 3 is 1V8 (DDR mem)
## - default is DRIVE=12 | SLEW=SLOW
## - pin names from Digilent master AtlysGeneralUCF.zip are given as comments
##
## clocks --------------------------------------------------------------------
## AtlysGeneralUCF: clk
##
NET "I_CLK100" LOC = "l15" | IOSTANDARD=LVCMOS25;
##
## USB UART interface --------------------------------------------------------
## AtlysGeneralUCF: UartRx, UartTx (crossed!)
##
NET "I_USB_RXD" LOC = "a16" | IOSTANDARD=LVCMOS33;
NET "O_USB_TXD" LOC = "b16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
##
## SWIs ----------------------------------------------------------------------
## AtlysGeneralUCF: sw<0:7>
##
NET "I_HIO_SWI<0>" LOC = "a10" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<1>" LOC = "d14" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<2>" LOC = "c14" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<3>" LOC = "p15" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<4>" LOC = "p12" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<5>" LOC = "r5" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<6>" LOC = "t5" | IOSTANDARD=LVCMOS33;
NET "I_HIO_SWI<7>" LOC = "e4" | IOSTANDARD=LVCMOS33;
##
## BTNs ----------------------------------------------------------------------
## AtlysGeneralUCF: btn<0:5>; clockwise(U-R-D-L) - middle - reset
##
NET "I_HIO_BTN<0>" LOC = "n4" | IOSTANDARD=LVCMOS18; # BTNU
NET "I_HIO_BTN<1>" LOC = "f6" | IOSTANDARD=LVCMOS18; # BTNR
NET "I_HIO_BTN<2>" LOC = "p3" | IOSTANDARD=LVCMOS18; # BTND
NET "I_HIO_BTN<3>" LOC = "p4" | IOSTANDARD=LVCMOS18; # BTNL
NET "I_HIO_BTN<4>" LOC = "f5" | IOSTANDARD=LVCMOS18; # BTNC
NET "I_HIO_BTN<5>" LOC = "t15" | IOSTANDARD=LVCMOS18; # RESET (act.low!!)
##
## LEDs ----------------------------------------------------------------------
## AtlysGeneralUCF: Led<0:7>
##
NET "O_HIO_LED<0>" LOC = "u18" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<1>" LOC = "m14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<2>" LOC = "n14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<3>" LOC = "l14" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<4>" LOC = "m13" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<5>" LOC = "d4" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<6>" LOC = "p16" | IOSTANDARD=LVCMOS33;
NET "O_HIO_LED<7>" LOC = "n12" | IOSTANDARD=LVCMOS33;

23
rtl/bplib/atlys/atlys_pins_pma0_rs232.ucf Normal file
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@@ -0,0 +1,23 @@
## $Id: atlys_pins_pma0_rs232.ucf 403 2011-08-06 17:36:22Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-08-06 403 1.0 Initial version
##
## Pmod connector A top / usage RS232 for FTDI USB serport -------------------
##
## front view (towards PCB edge):
##
## P-6 P-1
## | |
## +-------------------------+
## | VCC GND TXD RXD CTS RTS |
## | VCC GND ... ... ... ... |
## =============================
## < HDMI connector>
##
##
NET "O_FUSP_RTS_N" LOC = "t3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
NET "I_FUSP_CTS_N" LOC = "r3" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "I_FUSP_RXD" LOC = "p6" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "O_FUSP_TXD" LOC = "n5" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;

25
rtl/bplib/atlys/atlys_pins_pmod.ucf Normal file
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@@ -0,0 +1,25 @@
## $Id: atlys_pins_pmod.ucf 403 2011-08-06 17:36:22Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-08-06 403 1.0 Initial version
##
## Pmod connectors -----------------------------------------------------------
##
## front view (towards PCB edge):
##
## +-------------------------+
## | VCC GND P-4 P-3 P-2 P-1 |
## | VCC GND P10 P-9 P-8 P-7 |
## =============================
## < HDMI connector>
##
## Pmod A (top: 0-3; bot: 4-7; all 8 shared with HDMI Type D connector...)
NET "IO_PMODA<0>" LOC = "t3" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<1>" LOC = "r3" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<2>" LOC = "p6" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<3>" LOC = "n5" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<4>" LOC = "v9" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<5>" LOC = "t9" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<6>" LOC = "v4" | IOSTANDARD=LVCMOS33;
NET "IO_PMODA<7>" LOC = "t4" | IOSTANDARD=LVCMOS33;

7
rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_rs232_2l4l_iob.vhd 406 2011-08-14 21:06:44Z mueller $
-- $Id: bp_rs232_2l4l_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -36,7 +36,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.bpgenlib.all;
@@ -123,7 +122,7 @@ begin
DORELAY : if RELAY generate
proc_regs_pipe: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
RR_RXD0 <= '1';
RR_TXD0 <= '1';
@@ -155,7 +154,7 @@ begin
proc_regs_mux: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_RXD <= '1';
R_CTS_N <= '0';

3
rtl/bplib/bpgen/bp_rs232_2line_iob.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_rs232_2line_iob.vhd 387 2011-07-03 17:24:52Z mueller $
-- $Id: bp_rs232_2line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,7 +32,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

3
rtl/bplib/bpgen/bp_rs232_4line_iob.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_rs232_4line_iob.vhd 391 2011-07-09 17:25:02Z mueller $
-- $Id: bp_rs232_4line_iob.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,7 +32,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

3
rtl/bplib/bpgen/bp_swibtnled.vhd
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@@ -1,4 +1,4 @@
-- $Id: bp_swibtnled.vhd 403 2011-08-06 17:36:22Z mueller $
-- $Id: bp_swibtnled.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,7 +32,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

28
rtl/bplib/bpgen/bpgenlib.vhd
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@@ -1,4 +1,4 @@
-- $Id: bpgenlib.vhd 404 2011-08-07 22:00:25Z mueller $
-- $Id: bpgenlib.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,8 @@
-- Tool versions: 12.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-16 426 1.0.6 now numeric_std clean
-- 2011-10-10 413 1.0.5 add sn_humanio_demu
-- 2011-08-07 404 1.0.4 add RELAY generic for bp_rs232_2l4l_iob
-- 2011-08-06 403 1.0.3 add RESET port for bp_rs232_2l4l_iob
-- 2011-07-09 391 1.0.2 move in bp_rs232_2l4l_iob from s3boardlib
@@ -28,7 +30,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
@@ -104,7 +106,7 @@ component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -153,11 +155,29 @@ component sn_humanio is -- human i/o handling: swi,btn,led,dsp
);
end component;
component sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset

23
rtl/bplib/bpgen/sn_4x7segctl.vhd
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@@ -1,4 +1,4 @@
-- $Id: sn_4x7segctl.vhd 400 2011-07-31 09:02:16Z mueller $
-- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,9 +18,10 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
@@ -32,7 +33,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -51,12 +52,12 @@ end sn_4x7segctl;
architecture syn of sn_4x7segctl is
type regs_type is record
cdiv : std_logic_vector(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
end record regs_type;
constant regs_init : regs_type := (
conv_std_logic_vector(0,CDWIDTH),
slv(to_unsigned(0,CDWIDTH)),
(others=>'0')
);
@@ -93,7 +94,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
@@ -113,9 +114,9 @@ begin
r := R_REGS;
n := R_REGS;
n.cdiv := unsigned(r.cdiv) - 1;
n.cdiv := slv(unsigned(r.cdiv) - 1);
if unsigned(r.cdiv) = 0 then
n.dcnt := unsigned(r.dcnt) + 1;
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
chex := "0000";
@@ -142,13 +143,13 @@ begin
cano := "1111";
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(conv_integer(unsigned(r.dcnt))) := '0';
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(conv_integer(unsigned(chex))));
SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex))));
end process proc_next;

1
rtl/bplib/bpgen/sn_humanio.vbom
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@@ -2,7 +2,6 @@
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
bpgenlib.vbom
## sys_conf : sys_conf.vhd
# components
../../vlib/xlib/iob_reg_o_gen.vbom
bp_swibtnled.vbom

6
rtl/bplib/bpgen/sn_humanio.vhd
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@@ -1,4 +1,4 @@
-- $Id: sn_humanio.vhd 403 2011-08-06 17:36:22Z mueller $
-- $Id: sn_humanio.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,10 +22,11 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-09-17 409 13.1 O40d xc3s1000-4 49 86 0 53 s 5.3 ns
-- 2011-07-02 387 12.1 M53d xc3s1000-4 48 87 0 53 s 5.1 ns
-- 2010-04-10 275 11.4 L68 xc3s1000-4 48 87 0 53 s 5.2 ns
--
@@ -42,7 +43,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;
use work.xlib.all;

7
rtl/bplib/bpgen/sn_humanio_demu.vbom Normal file
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@@ -0,0 +1,7 @@
# libs
../../vlib/slvtypes.vhd
bpgenlib.vbom
# components
bp_swibtnled.vbom
# design
sn_humanio_demu.vhd

195
rtl/bplib/bpgen/sn_humanio_demu.vhd Normal file
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@@ -0,0 +1,195 @@
-- $Id: sn_humanio_demu.vhd 414 2011-10-11 19:38:12Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_humanio_demu - syn
-- Description: All BTN, SWI, LED handling for atlys
--
-- Dependencies: bpgen/bp_swibtnled
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-10-10 413 13.1 O40d xc3s1000-4 67 66 0 55 s 6.1 ns
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-11 414 1.0.1 take care of RESET BTN being active low
-- 2011-10-10 413 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity sn_humanio_demu is -- human i/o handling: swi,btn,led only
generic (
DEBOUNCE : boolean := true); -- instantiate debouncer for SWI,BTN
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end sn_humanio_demu;
architecture syn of sn_humanio_demu is
constant c_mode_led : slv2 := "00";
constant c_mode_dp : slv2 := "01";
constant c_mode_datl : slv2 := "10";
constant c_mode_dath : slv2 := "11";
type regs_type is record
mode : slv2; -- current mode
cnt : slv9; -- msec counter
up_1 : slbit; -- btn up last cycle
dn_1 : slbit; -- btn dn last cycle
led : slv8; -- led state
end record regs_type;
constant regs_init : regs_type := (
c_mode_led, -- mode
(others=>'0'), -- cnt
'0','0', -- up_1, dn_1
(others=>'0') -- led
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal BTN_HW : slv6 := (others=>'0');
signal LED_HW : slv8 := (others=>'0');
begin
HIO : bp_swibtnled
generic map (
SWIDTH => 8,
BWIDTH => 6,
LWIDTH => 8,
DEBOUNCE => DEBOUNCE)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN_HW,
LED => LED_HW,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, LED, DSP_DAT, DSP_DP, BTN_HW)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ibtn : slv4 := (others=>'0');
variable iup : slbit := '0';
variable idn : slbit := '0';
variable ipuls : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
ibtn(0) := not BTN_HW(5); -- RESET button is act. low !
ibtn(1) := BTN_HW(1);
ibtn(2) := BTN_HW(4);
ibtn(3) := BTN_HW(3);
iup := BTN_HW(0);
idn := BTN_HW(2);
ipuls := '0';
n.up_1 := iup;
n.dn_1 := idn;
if iup='0' and idn='0' then
n.cnt := (others=>'0');
else
if CE_MSEC = '1' then
n.cnt := slv(unsigned(r.cnt) + 1);
if r.cnt = "111111111" then
ipuls := '1';
end if;
end if;
end if;
if iup='1' or idn='1' then
n.led := (others=>'0');
case r.mode is
when c_mode_led => n.led(0) := '1';
when c_mode_dp => n.led(1) := '1';
when c_mode_datl => n.led(2) := '1';
when c_mode_dath => n.led(3) := '1';
when others => null;
end case;
if iup='1' and (r.up_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) + 1);
elsif idn='1' and (r.dn_1='0' or ipuls='1') then
n.mode := slv(unsigned(r.mode) - 1);
end if;
else
case r.mode is
when c_mode_led => n.led := LED;
when c_mode_dp => n.led := "0000" & DSP_DP;
when c_mode_datl => n.led := DSP_DAT( 7 downto 0);
when c_mode_dath => n.led := DSP_DAT(15 downto 8);
when others => null;
end case;
end if;
N_REGS <= n;
BTN <= ibtn;
LED_HW <= r.led;
end process proc_next;
end syn;

11
rtl/bplib/bpgen/sn_humanio_rbus.vhd
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@@ -1,4 +1,4 @@
-- $Id: sn_humanio_rbus.vhd 406 2011-08-14 21:06:44Z mueller $
-- $Id: sn_humanio_rbus.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.2.1 now numeric_std clean
-- 2011-08-14 406 1.2 common register layout with bp_swibtnled_rbus
-- 2011-08-07 404 1.3 add pipeline regs ledin,(swi,btn,led,dp,dat)eff
-- 2011-07-08 390 1.2 renamed from s3_humanio_rbus, add BWIDTH generic
@@ -65,7 +66,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
@@ -77,7 +78,7 @@ entity sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := conv_std_logic_vector(2#10000000#,8));
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
@@ -183,7 +184,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else

21
rtl/bplib/issi/is61lv25616al.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: is61lv25616al.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: is61lv25616al.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -21,9 +21,10 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2008-05-12 145 1.0.1 BUGFIX: Output now 'Z' if byte enables deasserted
-- 2007-12-14 101 1.0 Initial version (written on warsaw airport)
------------------------------------------------------------------------------
@@ -42,7 +43,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -108,7 +109,7 @@ end sim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -152,14 +153,14 @@ begin
variable ram : ram_type := (others=>datzero);
begin
if WE_EFF'event and WE_EFF='0' then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(conv_integer(unsigned(ADDR))) := to_x01(DATA);
if falling_edge(WE_EFF) then -- end of write cycle
-- note: to_x01 used below to prevent
-- that 'z' a written into mem.
ram(to_integer(unsigned(ADDR))) := to_x01(DATA);
end if;
if CE='1' and OE='1' and BE='1' and WE='0' then -- output driver
DATA <= ram(conv_integer(unsigned(ADDR)));
DATA <= ram(to_integer(unsigned(ADDR)));
else
DATA <= (others=>'Z');
end if;

21
rtl/bplib/micron/mt45w8mw16b.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: mt45w8mw16b.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: mt45w8mw16b.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,9 +23,10 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.3.2 now numeric_std clean
-- 2010-06-03 299 1.3.1 improved timing model (WE cycle, robust T_apa)
-- 2010-06-03 298 1.3 add timing model again
-- 2010-05-28 295 1.2 drop timing (was incorrect), pure functional now
@@ -56,7 +57,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
@@ -170,7 +171,7 @@ begin
end if;
addr_last := L_ADDR;
end if;
if OE'event and OE='1' then
if rising_edge(OE) then
DOUT_VAL_OE <= '0', '1' after T_oe;
end if;
end process proc_dout_val;
@@ -203,14 +204,14 @@ begin
-- end of write cycle
-- note: to_x01 used below to prevent that 'z' a written into mem.
if WE_L_EFF'event and WE_L_EFF='0' then
ram(conv_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
if falling_edge(WE_L_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte0) := to_x01(DATA(f_byte0));
end if;
if WE_U_EFF'event and WE_U_EFF='0' then
ram(conv_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
if falling_edge(WE_U_EFF) then
ram(to_integer(unsigned(L_ADDR)))(f_byte1) := to_x01(DATA(f_byte1));
end if;
DOUT <= ram(conv_integer(unsigned(L_ADDR)));
DOUT <= ram(to_integer(unsigned(L_ADDR)));
end process proc_cram;

3
rtl/bplib/nexys2/n2_cram_dummy.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: n2_cram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: n2_cram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -27,7 +27,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;

23
rtl/bplib/nexys2/n2_cram_memctl_as.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: n2_cram_memctl_as.vhd 340 2010-11-27 13:00:57Z mueller $
-- $Id: n2_cram_memctl_as.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -21,7 +21,7 @@
-- Test bench: tb/tb_n2_cram_memctl
-- fw_gen/tst_sram/nexys2/tb/tb_tst_sram_n2
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.5 now numeric_std clean
-- 2010-11-22 339 1.0.4 cntdly now 3 bit; add assert for DELAY generics
-- 2010-06-03 299 1.0.3 add "KEEP" for data iob; MEM_OE='1' on first read
-- cycle;
@@ -111,7 +112,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
@@ -304,7 +305,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
@@ -391,7 +392,7 @@ begin
idata_oe := '0';
if unsigned(r.cntdly) /= 0 then
n.cntdly := unsigned(r.cntdly) - 1;
n.cntdly := slv(unsigned(r.cntdly) - 1);
end if;
case r.state is
@@ -406,7 +407,7 @@ begin
iactr := '1'; -- signal mem read
imem_ce := '1'; -- ce CRAM next cycle
imem_oe := '1'; -- oe CRAM next cycle
n.cntdly:= conv_std_logic_vector(READ0DELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(READ0DELAY-1, n.cntdly'length));
n.state := s_rdwait0; -- next: wait
when s_rdwait0 => -- s_rdwait0: read wait low word
@@ -426,7 +427,7 @@ begin
idata_cei := '1'; -- latch input data
iaddr0_ce := '1'; -- latch address 0 bit
iaddr0 := '1'; -- now go for high word
n.cntdly:= conv_std_logic_vector(READ1DELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(READ1DELAY-1, n.cntdly'length));
n.state := s_rdwait1; -- next: wait high word
when s_rdwait1 => -- s_rdwait1: read wait high word
@@ -461,7 +462,7 @@ begin
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.state := s_wrwait0; -- next: wait
when s_wrwait0 => -- s_rdput0: write wait 1st word
@@ -504,7 +505,7 @@ begin
idata_oe := '1'; -- oe FPGA next cycle
imem_ce := '1'; -- ce CRAM next cycle
imem_we := '1'; -- we CRAM in half cycle
n.cntdly:= conv_std_logic_vector(WRITEDELAY-1, n.cntdly'length);
n.cntdly:= slv(to_unsigned(WRITEDELAY-1, n.cntdly'length));
n.state := s_wrwait1; -- next: wait
when s_wrwait1 => -- s_wrwait1: write wait 2nd word
@@ -540,7 +541,7 @@ begin
if unsigned(r.cntce) >= 127 then -- if max ce count expired
n.fidle := '1'; -- set forced idle flag
else -- if max ce count not yet reached
n.cntce := unsigned(r.cntce) + 1; -- increment counter
n.cntce := slv(unsigned(r.cntce) + 1); -- increment counter
end if;
end if;

13
rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_core.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tb_nexys2_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,15 +20,16 @@
-- To test: generic, any nexys2 target
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.1 now numeric_std clean
-- 2010-05-23 294 1.0 Initial version (derived from tb_s3board_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -59,8 +60,8 @@ architecture sim of tb_nexys2_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8);
constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8);
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin

13
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: tb_nexys2_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,10 +23,11 @@
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1; ghdl 0.26-0.29
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
@@ -35,7 +36,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -100,7 +101,7 @@ architecture sim of tb_nexys2_fusp is
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 20 ns;
constant clockosc_offset : time := 200 ns;
@@ -215,7 +216,7 @@ begin
begin
loop
wait until CLKSYS'event and CLKSYS='1';
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then

3
rtl/bplib/s3board/s3_sram_dummy.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: s3_sram_dummy.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: s3_sram_dummy.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,7 +28,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;

11
rtl/bplib/s3board/s3_sram_memctl.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: s3_sram_memctl.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: s3_sram_memctl.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -21,7 +21,7 @@
-- Test bench: tb/tb_s3_sram_memctl
-- fw_gen/tst_sram/s3board/tb/tb_tst_sram_s3
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.6 now numeric_std clean
-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
-- 2010-05-16 291 1.0.4 rename memctl_s3sram -> s3_sram_memctl
-- 2008-02-17 117 1.0.3 use req,we rather req_r,req_w interface
@@ -76,7 +77,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
@@ -213,7 +214,7 @@ begin
proc_regs: process (CLK)
begin
if CLK'event and CLK='1' then
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else

3
rtl/bplib/s3board/s3boardlib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: s3boardlib.vhd 391 2011-07-09 17:25:02Z mueller $
-- $Id: s3boardlib.vhd 426 2011-11-18 18:14:08Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -41,7 +41,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.slvtypes.all;

13
rtl/bplib/s3board/tb/tb_s3board_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_s3board_core.vhd 314 2010-07-09 17:38:41Z mueller $
-- $Id: tb_s3board_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,16 +20,17 @@
-- To test: generic, any s3board target
--
-- Target Devices: generic
-- Tool versions: xst 11.4; ghdl 0.26
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 1.0.2 now numeric_std clean
-- 2010-05-02 287 1.0.1 add sbaddr_(swi|btn) defs, now sbus addr 16,17
-- 2010-04-24 282 1.0 Initial version (from vlib/s3board/tb/tb_s3board)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -55,8 +56,8 @@ architecture sim of tb_s3board_core is
signal R_SWI : slv8 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := conv_std_logic_vector( 16,8);
constant sbaddr_btn: slv8 := conv_std_logic_vector( 17,8);
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin

13
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_s3board_fusp.vhd 351 2010-12-30 21:50:54Z mueller $
-- $Id: tb_s3board_fusp.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -23,9 +23,10 @@
-- To test: generic, any s3board_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-21 292 1.0.3 rename _PM1_ -> _FUSP_
@@ -36,7 +37,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
@@ -95,7 +96,7 @@ architecture sim of tb_s3board_fusp is
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := conv_std_logic_vector( 8,8);
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
@@ -198,7 +199,7 @@ begin
begin
loop
wait until CLK'event and CLK='1';
wait until rising_edge(CLK);
wait for c2out_time;
if RXERR = '1' then