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- added RH70/RP/RM big disk support

Browse Source 
- many cleanups
This commit is contained in:
Walter F.J. Mueller
2015-05-14 17:00:36 +00:00
parent e91847f8db
commit 4a032e9436
247 changed files with 11301 additions and 3449 deletions
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2
rtl/bplib/basys3/tb/tb_basys3.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_basys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
${basys3_aif := basys3_dummy.vbom}
# design
tb_basys3.vhd

48
rtl/bplib/basys3/tb/tb_basys3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_basys3.vhd 648 2015-02-20 20:16:21Z mueller $
-- $Id: tb_basys3.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_basys3_core
-- serport/serport_uart_rxtx
-- serport/serport_master
-- basys3_aif [UUT]
--
-- To test: generic, any basys3_aif target
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.1 use serport_master instead of serport_uart_rxtx
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
@@ -78,6 +79,10 @@ architecture sim of tb_basys3 is
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
@@ -138,22 +143,26 @@ begin
O_SEG_N => O_SEG_N
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => O_TXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => I_RXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
@@ -172,4 +181,13 @@ begin
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;

10
rtl/bplib/fx2rlink/fx2rlinklib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: fx2rlinklib.vhd 610 2014-12-09 22:44:43Z mueller $
-- $Id: fx2rlinklib.vhd 672 2015-05-02 21:58:28Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,6 +20,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-11 666 1.2 rlink_sp1c_fx2: drop ENAESC
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-04-20 509 1.0 Initial version
------------------------------------------------------------------------------
@@ -53,7 +54,9 @@ component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
@@ -61,7 +64,6 @@ component rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)

3
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vbom
View File

@@ -1,9 +1,12 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
../../vlib/rbus/rbdlib.vhd
../../vlib/rlink/rlinklib.vbom
../../vlib/serport/serportlib.vbom
../fx2lib/fx2lib.vhd
../../vlib/rbus/rbd_rbmon.vbom
../../vlib/rbus/rb_sres_or_2.vbom
# components
../../vlib/rlink/rlink_core8.vbom
../../vlib/serport/serport_1clock.vbom

69
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rlink_sp1c_fx2.vhd 610 2014-12-09 22:44:43Z mueller $
-- $Id: rlink_sp1c_fx2.vhd 672 2015-05-02 21:58:28Z mueller $
--
-- Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -19,18 +19,23 @@
-- serport/serport_1clock
-- rlinklib/rlink_rlbmux
-- fx2lib/fx2_2fifoctl_ic
-- rbus/rbd_rbmon
-- rbus/rb_sres_or_2
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 13.1-14.7; viv 2014.4; ghdl 0.29-0.31
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ifa ofa
-- 2015-05-02 672 14.7 131013 xc6slx16-2 618 875 90 340 s 7.2 - -
-- 2013-04-20 509 13.3 O76d xc3s1200e-4 441 903 128 637 s 8.7 - -
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-05-02 672 1.3 add rbd_rbmon (optional via generics)
-- 2015-04-11 666 1.2 drop ENAESC, rearrange XON handling
-- 2014-08-28 588 1.1 use new rlink v4 iface generics and 4 bit STAT
-- 2013-04-20 509 1.0 Initial version (derived from rlink_sp1c)
------------------------------------------------------------------------------
@@ -41,6 +46,7 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.serportlib.all;
use work.fx2lib.all;
@@ -58,7 +64,9 @@ entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
ENAPIN_RLBMON: integer := -1; -- SB_CNTL for rlbmon (-1=none)
ENAPIN_RBMON : integer := -1; -- SB_CNTL for rbmon (-1=none)
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15); -- clk divider initial/reset setting
CDINIT : natural := 15; -- clk divider initial/reset setting
RBMON_AWIDTH : natural := 0; -- rbmon: buffer size, (0=none)
RBMON_RBADDR : slv16 := slv(to_unsigned(16#ffe8#,16))); -- rbmon: base addr
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- 1 usec clock enable
@@ -66,7 +74,6 @@ entity rlink_sp1c_fx2 is -- rlink_core8+serport_1clk+fx2_ic combo
CE_INT : in slbit := '0'; -- rri ato time unit clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
ENAFX2 : in slbit; -- enable fx2 usage
RXSD : in slbit; -- receive serial data (board view)
TXSD : out slbit; -- transmit serial data (board view)
@@ -117,9 +124,13 @@ architecture syn of rlink_sp1c_fx2 is
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal RB_MREQ_M : rb_mreq_type := rb_mreq_init;
signal RB_SRES_M : rb_sres_type := rb_sres_init;
signal RB_SRES_RBMON : rb_sres_type := rb_sres_init;
begin
CORE : rlink_core8
CORE : rlink_core8 -- rlink master ----------------------
generic map (
BTOWIDTH => BTOWIDTH,
RTAWIDTH => RTAWIDTH,
@@ -131,6 +142,8 @@ begin
CLK => CLK,
CE_INT => CE_INT,
RESET => RESET,
ESCXON => ENAXON,
ESCFILL => '0', -- not used in FX2 enabled boards
RLB_DI => RLB_DI,
RLB_ENA => RLB_ENA,
RLB_BUSY => RLB_BUSY,
@@ -138,13 +151,13 @@ begin
RLB_VAL => RLB_VAL,
RLB_HOLD => RLB_HOLD,
RL_MONI => RL_MONI,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_M,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT
);
SERPORT : serport_1clock
SERPORT : serport_1clock -- serport interface -----------------
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT,
@@ -155,7 +168,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => RESET,
ENAXON => ENAXON,
ENAESC => ENAESC,
ENAESC => '0', -- escaping now in rlink_core8
RXDATA => SER_RXDATA,
RXVAL => SER_RXVAL,
RXHOLD => SER_RXHOLD,
@@ -169,7 +182,7 @@ begin
TXCTS_N => CTS_N
);
RLBMUX : rlink_rlbmux
RLBMUX : rlink_rlbmux -- rlink control mux -----------------
port map (
SEL => ENAFX2,
RLB_DI => RLB_DI,
@@ -192,7 +205,12 @@ begin
P1_TXBUSY => FX2_TXBUSY
);
FX2CNTL : fx2_2fifoctl_ic
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
FX2CNTL : fx2_2fifoctl_ic -- FX2 interface ---------------------
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
@@ -222,9 +240,28 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
RLB_MONI.rxval <= RLB_VAL;
RLB_MONI.rxhold <= RLB_HOLD;
RLB_MONI.txena <= RLB_ENA;
RLB_MONI.txbusy <= RLB_BUSY;
RBMON : if RBMON_AWIDTH > 0 generate -- rbus monitor --------------
begin
I0 : rbd_rbmon
generic map (
RB_ADDR => RBMON_RBADDR,
AWIDTH => RBMON_AWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ_M,
RB_SRES => RB_SRES_RBMON,
RB_SRES_SUM => RB_SRES_M
);
end generate RBMON;
RB_SRES_OR : rb_sres_or_2 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES,
RB_SRES_2 => RB_SRES_RBMON,
RB_SRES_OR => RB_SRES_M
);
RB_MREQ <= RB_MREQ_M; -- setup output signals
end syn;

2
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
${nexys2_fusp_aif := nexys2_fusp_dummy.vbom}
# design
tb_nexys2_fusp.vhd

47
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_fusp.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nexys2_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys2_core
-- serport/serport_uart_rxtx
-- serport/serport_master
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
@@ -110,7 +111,8 @@ architecture sim of tb_nexys2_fusp is
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
@@ -197,29 +199,33 @@ begin
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
@@ -255,7 +261,8 @@ begin
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;

2
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom}
# design

41
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nexys2_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink_dcm
-- tb_nexys2_core
-- serport/serport_uart_rxtx
-- serport/serport_master
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_cuff_aif [UUT]
--
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-01-03 469 1.1 add fx2 model and data path
-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
@@ -126,6 +127,7 @@ architecture sim of tb_nexys2_fusp_cuff is
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
@@ -221,22 +223,26 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXACT => UART_RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXOK => '1',
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
FX2 : entity work.fx2_2fifo_core
@@ -321,7 +327,8 @@ begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_FX2 <= to_x01(SB_DATA(1));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
end if;
end if;
end process proc_simbus;

2
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}
# design
tb_nexys3_fusp.vhd

47
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys3_fusp.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nexys3_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- serport/serport_master
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
@@ -106,7 +107,8 @@ architecture sim of tb_nexys3_fusp is
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
@@ -198,29 +200,33 @@ begin
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
@@ -256,7 +262,8 @@ begin
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;

2
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom}
# design

42
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys3_fusp_cuff.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nexys3_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
-- serport/serport_master
-- fx2lib/tb/fx2_2fifo_core
-- nexys3_fusp_cuff_aif [UUT]
--
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
-- tb_nexys2_fusp_cuff)
@@ -75,7 +76,6 @@ architecture sim of tb_nexys3_fusp_cuff is
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_RXERR : slbit := '0';
signal UART_RXACT : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
@@ -128,6 +128,7 @@ architecture sim of tb_nexys3_fusp_cuff is
signal RTS_N : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
signal R_PORTSEL_FX2 : slbit := '0'; -- if 1 use fx2
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
@@ -228,22 +229,26 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXACT => UART_RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
CLK => CLKCOM,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => UART_RXERR,
RXOK => '1',
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
FX2 : entity work.fx2_2fifo_core
@@ -328,7 +333,8 @@ begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_FX2 <= to_x01(SB_DATA(1));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
R_PORTSEL_FX2 <= to_x01(SB_DATA(2));
end if;
end if;
end process proc_simbus;

2
rtl/bplib/nexys4/tb/tb_nexys4.vbom
View File

@@ -18,7 +18,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_nexys4_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
${nexys4_aif := nexys4_dummy.vbom}
# design
tb_nexys4.vhd

48
rtl/bplib/nexys4/tb/tb_nexys4.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys4.vhd 643 2015-02-07 17:41:53Z mueller $
-- $Id: tb_nexys4.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_nexys4_core
-- serport/serport_uart_rxtx
-- serport/serport_master
-- nexys4_aif [UUT]
--
-- To test: generic, any nexys4_aif target
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
@@ -86,6 +87,10 @@ architecture sim of tb_nexys4 is
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
@@ -152,22 +157,26 @@ begin
O_SEG_N => O_SEG_N
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => O_TXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => I_RXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
@@ -186,4 +195,13 @@ begin
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;

2
rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom
View File

@@ -19,7 +19,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
tb_nexys4_core.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
${nexys4_cram_aif := nexys4_cram_dummy.vbom}
# design
tb_nexys4_cram.vhd

39
rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys4_cram.vhd 643 2015-02-07 17:41:53Z mueller $
-- $Id: tb_nexys4_cram.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -20,7 +20,7 @@
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- tb_nexys4_core
-- serport/serport_uart_rxtx
-- serport/serport_master
-- nexys4_cram_aif [UUT]
-- vlib/parts/micron/mt45w8mw16b
--
@@ -31,6 +31,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
-- 2013-09-21 534 1.0 Initial version (derived from tb_nexys3)
@@ -96,6 +97,10 @@ architecture sim of tb_nexys4_cram is
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
@@ -187,22 +192,26 @@ begin
DATA => IO_MEM_DATA
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => O_TXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => I_RXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process

2
rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
View File

@@ -15,7 +15,7 @@
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
tb_s3board_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../vlib/serport/serport_master.vbom
${s3board_fusp_aif := s3board_fusp_dummy.vbom}
# design
tb_s3board_fusp.vhd

47
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_s3board_fusp.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_s3board_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,7 +20,7 @@
-- rlink/tb/tbcore_rlink
-- tb_s3board_core
-- s3board_fusp_aif [UUT]
-- serport/serport_uart_rxtx
-- serport/serport_master
--
-- To test: generic, any s3board_fusp_aif target
--
@@ -28,6 +28,7 @@
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-30 351 3.0 use rlink/tb now
@@ -100,7 +101,8 @@ architecture sim of tb_s3board_fusp is
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
signal R_PORTSEL_SER : slbit := '0'; -- if 1 use alternate serport
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
@@ -167,29 +169,33 @@ begin
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
SERMSTR : serport_master
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
CLK => CLK,
RESET => UART_RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => UART_RXD,
TXSD => UART_TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
proc_port_mux: process (R_PORTSEL_SER, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
if R_PORTSEL_SER = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
@@ -225,7 +231,8 @@ begin
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
R_PORTSEL_SER <= to_x01(SB_DATA(0));
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;