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- upgraded CRAM controller, now with 'page mode' support

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- new test bench driver tbrun, give automatized test bench execution
This commit is contained in:
Walter F.J. Mueller
2016-10-15 07:42:21 +00:00
parent 2b5cfb7d96
commit 5983b0bb2a
402 changed files with 18795 additions and 1204 deletions
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37
rtl/vlib/comlib/Makefile Normal file
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# $Id: Makefile 749 2016-03-20 22:09:03Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-03-20 749 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
DCP_all = $(VBOM_all:.vbom=_syn.dcp)
#
# reference board for test synthesis is Artix-7 based Nexys4
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
#
.PHONY : catch all
#
catch :
@echo "no default target defined, use"
@echo " make all"
@echo " make <module>_syn.dcp"
@exit 1
#
all : $(DCP_all)
#
clean : viv_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#