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- upgraded CRAM controller, now with 'page mode' support

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- new test bench driver tbrun, give automatized test bench execution
This commit is contained in:
Walter F.J. Mueller
2016-10-15 07:42:21 +00:00
parent 2b5cfb7d96
commit 5983b0bb2a
402 changed files with 18795 additions and 1204 deletions
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5
rtl/vlib/simlib/simbididly.vbom Normal file
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@@ -0,0 +1,5 @@
# libs
../slvtypes.vhd
# components
# design
simbididly.vhd

124
rtl/vlib/simlib/simbididly.vhd Normal file
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@@ -0,0 +1,124 @@
-- $Id: simbididly.vhd 793 2016-07-23 19:38:55Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: simbididly - sim
-- Description: Bi-directional bus delay for test benches
--
-- Dependencies: -
-- Test bench: tb_simbididly
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.0.1 ensure non-zero DELAY
-- 2016-07-17 789 1.0 Initial version (use separate driver regs now)
-- 2016-07-16 787 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B (>0ns!)
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end entity simbididly;
architecture sim of simbididly is
type state_type is (
s_idle, -- s_idle: both ports high-z
s_a2b, -- s_a2b: A drives, B listens
s_b2a -- s_b2a: B drives, A listens
);
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_STATE : state_type := s_idle;
signal R_A : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_B : slv(DWIDTH-1 downto 0) := (others=>'Z');
begin
process
variable istate : state_type := s_idle;
begin
-- the delay model can enter into a delta cycle oszillation mode
-- when DELAY is 0 ns. So ensure the delay is non-zero
assert DELAY > 0 ns report "DELAY > 0 ns" severity failure;
while true loop
-- if idle check whether A or B port starts to drive bus
-- Note: both signal R_STATE and variable istate is updated
-- istate is needed to control the driver section below in the
-- same delta cycle based on the most recent state state
istate := R_STATE;
if now > 0 ns then -- to avoid startup problems
if R_STATE = s_idle then
if A /= all_z then
R_STATE <= s_a2b;
istate := s_a2b;
elsif B /= all_z then
R_STATE <= s_b2a;
istate := s_b2a;
end if;
end if;
end if;
case istate is
when s_a2b =>
R_B <= transport A after DELAY;
if A = all_z then R_STATE <= s_idle after DELAY; end if;
when s_b2a =>
R_A <= transport B after DELAY;
if B = all_z then R_STATE <= s_idle after DELAY; end if;
when others => null;
end case;
-- Note: the driver clash check is done by comparing an internal signal
-- with the external signal. If they differ this indicates a clash.
-- Just checking for 'x' gives false alarms when the bus is driven
-- with 'x', which can for example come from a memory model before
-- valid data is available.
if now > 0 ns then -- to avoid startup problems
case istate is
when s_a2b =>
assert B = R_B report "driver clash B port" severity error;
when s_b2a =>
assert A = R_A report "driver clash A port" severity error;
when others => null;
end case;
end if;
wait on A,B;
end loop;
end process;
A <= R_A;
B <= R_B;
end sim;

25
rtl/vlib/simlib/simbus.vhd
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@@ -1,6 +1,6 @@
-- $Id: simbus.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: simbus.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,10 +16,11 @@
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 remove global clock cycle signal
-- 2016-09-02 805 2.1 rename SB_CLKSTOP > SB_SIMSTOP; init with 'L'
-- 2011-12-23 444 2.0 remove global clock cycle signal SB_CLKCYCLE
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
@@ -32,15 +33,15 @@ use work.slvtypes.all;
package simbus is
signal SB_CLKSTOP : slbit := '0'; -- global clock stop
signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
signal SB_SIMSTOP : slbit := 'L'; -- global simulation stop
signal SB_CNTL : slv16 := (others=>'L'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := '0'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
signal SB_VAL : slbit := 'L'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'L'); -- init bcast address
signal SB_DATA : slv16 := (others=>'L'); -- init bcast data
-- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
-- strong ('0','1') drivers. Therefore always remove strenght before
-- using, e.g. with to_x01()
-- Note: SB_SIMSTOP, SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak
-- ('L','H') and strong ('0','1') drivers. Therefore always remove
-- strenght before using, e.g. with to_x01()
end package simbus;

15
rtl/vlib/simlib/simclk.vhd
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@@ -1,6 +1,6 @@
-- $Id: simclk.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: simclk.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,10 +18,11 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Tool versions: xst 8.2-14.7; viv 2016.2; ghdl 0.18-0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.0.1 CLK_STOP now optional port
-- 2011-12-23 444 2.0 remove CLK_CYCLE output port
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-03-24 129 1.0.2 CLK_CYCLE now 31 bits
@@ -35,11 +36,11 @@ use work.slvtypes.all;
entity simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
PERIOD : Delay_length := 20 ns; -- clock period
OFFSET : Delay_length := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit -- clock stop trigger
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end entity simclk;
@@ -47,7 +48,7 @@ architecture sim of simclk is
begin
proc_clk: process
constant clock_halfperiod : time := PERIOD/2;
constant clock_halfperiod : Delay_length := PERIOD/2;
begin
CLK <= '0';

4
rtl/vlib/simlib/simclkcnt.vhd
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@@ -1,4 +1,4 @@
-- $Id: simclkcnt.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: simclkcnt.vhd 787 2016-07-16 14:40:41Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,7 +18,7 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; ghdl 0.29-0.31
-- Tool versions: xst 12.1-14.7; viv 2016.2; ghdl 0.29-0.33
--
-- Revision History:
-- Date Rev Version Comment

32
rtl/vlib/simlib/simlib.vhd
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@@ -1,4 +1,4 @@
-- $Id: simlib.vhd 774 2016-06-12 17:08:47Z mueller $
-- $Id: simlib.vhd 805 2016-09-03 08:09:52Z mueller $
--
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -22,6 +22,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 2.1.4 simclk(v): CLK_STOP,CLK_HOLD now optional ports
-- 2016-07-16 787 2.1.3 add simbididly component
-- 2016-06-12 774 2.1.2 add writetimens()
-- 2014-10-25 599 2.1.1 add wait_* procedures; writeoptint: no dat clear
-- 2014-10-18 597 2.1 add simfifo_*, writetrace procedures
@@ -240,9 +242,9 @@ procedure writetrace( -- debug trace - slv
dat : in slv); -- value
type clock_dsc is record -- clock descriptor
period : time; -- clock period
hold : time; -- hold time = clock yo stim time
setup : time; -- setup time = moni to clock time
period : Delay_length; -- clock period
hold : Delay_length; -- hold time = clock yo stim time
setup : Delay_length; -- setup time = moni to clock time
end record;
procedure wait_nextstim( -- wait for next stim time
@@ -294,11 +296,11 @@ procedure simfifo_dump( -- dump simfifo
component simclk is -- test bench clock generator
generic (
PERIOD : time := 20 ns; -- clock period
OFFSET : time := 200 ns); -- clock offset (first up transition)
PERIOD : Delay_length := 20 ns; -- clock period
OFFSET : Delay_length := 200 ns); -- clock offset (first up transition)
port (
CLK : out slbit; -- clock
CLK_STOP : in slbit -- clock stop trigger
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end component;
@@ -306,9 +308,9 @@ component simclkv is -- test bench clock generator
-- with variable periods
port (
CLK : out slbit; -- clock
CLK_PERIOD : in time; -- clock period
CLK_HOLD : in slbit; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit -- clock stop trigger
CLK_PERIOD : in Delay_length; -- clock period
CLK_HOLD : in slbit := '0'; -- if 1, hold clocks in 0 state
CLK_STOP : in slbit := '0' -- clock stop trigger
);
end component;
@@ -319,6 +321,16 @@ component simclkcnt is -- test bench system clock cycle counter
);
end component;
component simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end component;
end package simlib;
-- ----------------------------------------------------------------------------