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mirror of https://github.com/wfjm/w11.git synced 2026-04-15 01:13:44 +00:00

more and improved E11 support

This commit is contained in:
wfjm
2023-03-22 08:45:29 +01:00
parent 5990a8fe0a
commit 5d8c065ee4
12 changed files with 132 additions and 56 deletions

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@@ -53,7 +53,7 @@ The full set of tests is only run for tagged releases.
- tools/bin/asm-11
- BUGFIX: fix directly nested .if behavior
- tools/tcode
- BUGFIX: use mmr0 page mode for PSW PM if ico=1
- cpu_mmu.mac: BUGFIX: use mmr0 page mode for PSW PM if ico=1
- src/librtools
- RtimerFd.cpp: BUGFIX: SetRelative(): correct is-positive check

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@@ -1,9 +1,12 @@
; $Id: cpu_details.mac 1374 2023-02-18 10:30:46Z mueller $
; $Id: cpu_details.mac 1384 2023-03-22 07:35:32Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2023-03-21 1384 1.1.2 remove e11 exemptions for A2.3, A2.5-9,
; A3.2 part 2+3; A3.3, A4.4 part 3+4;
; A4.4 part 5: skip on e11 (SPL in u mode handling)
; 2023-02-17 1374 1.1.1 use pushm,popm
; 2023-01-27 1359 1.1 use .mcall and mlib; use rt?jmp, hta??? macros
; 2023-01-11 1349 1.0 Initial version
@@ -280,9 +283,7 @@ ta0202: mov #1000$,vhustp ; continuation address
; will return a non-existent memory abort even in a maximum memory
; configuration.
;
ta0203: cmpb systyp,#sy.e11 ; e11 V7.3 return wrong CPUERR value
beq 9999$
push kipar6 ; save kipar6
ta0203: push kipar6 ; save kipar6
mov #177400,kipar6
mov #m3.e22,mmr3 ; 22-bit mode
mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
@@ -315,9 +316,7 @@ ta0204: mov #1000$,vhustp ; continuation address
; Test cp.ysv: yellow stack trap
; Since stack is still usable after the trap, the vhugen handler can be used.
;
ta0205: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt trap, runs on hold
beq 9999$
mov #1000$,vhustp ; continuation address
ta0205: mov #1000$,vhustp ; continuation address
mov #400,sp
clr -(sp) ; should trap (not abort)
halt ; not executed, handler continues at 1000$
@@ -331,9 +330,7 @@ ta0205: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt trap, runs on hold
; Test A2.6 -- CPUERR cp.rsv +++++++++++++++++++++++++++++++++++++++++
; Test cp.rsv: red stack trap - simple low stack case
;
ta0206: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt abort, runs on hold
beq 9999$
mov #1000$,v..iit ; setup direct iit handler
ta0206: mov #1000$,v..iit ; setup direct iit handler
mov #340,sp
clr -(sp) ; should abort (not trap)
halt
@@ -348,9 +345,7 @@ ta0206: cmpb systyp,#sy.e11 ; e11 V7.3 doesnt abort, runs on hold
; Test A2.7 -- CPUERR cp.odd + stack error +++++++++++++++++++++++++++
; Test cp.odd: fatal stack error after odd stack
;
ta0207: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to odd stack, abort after halt
beq 9999$
cmpb systyp,#sy.sih ; SimH uses J11 semantics
ta0207: cmpb systyp,#sy.sih ; SimH uses J11 behavior
bne 100$
mov #<cp.rsv+cp.odd>,1010$+2 ; and sets rsv for all stack errors
;
@@ -370,9 +365,7 @@ ta0207: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to odd stack, abort after halt
; Test cp.nxm: fatal stack error after non-existent memory abort
; Setup like in A2.3, put stack at p6base+4
;
ta0208: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
beq 9999$
cmpb systyp,#sy.sih ; SimH uses J11 semantics
ta0208: cmpb systyp,#sy.sih ; SimH uses J11 behavior
bne 100$
mov #<cp.rsv+cp.nxm>,1010$+2 ; and sets rsv for all stack errors
;
@@ -399,9 +392,7 @@ ta0208: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
; Test cp.ito: fatal stack error after unibus timeout
; Setup like in A2.4, put stack at 160004
;
ta0209: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
beq 9999$
cmpb systyp,#sy.sih ; SimH uses J11 semantics
ta0209: cmpb systyp,#sy.sih ; SimH uses J11 behavior
bne 100$
mov #<cp.rsv+cp.ito>,1010$+2 ; and sets rsv for all stack errors
;
@@ -421,7 +412,7 @@ ta0209: cmpb systyp,#sy.e11 ; e11 V7.3 pushes to bad stack, abort after halt
; Test cp.rsv: fatal stack error after mmu abort
; Set kernel I page 6 to non-resident
;
ta0210: cmpb systyp,#sy.sih ; SimH uses J11 semantics
ta0210: cmpb systyp,#sy.sih ; SimH uses J11 behavior
bne 100$
mov #cp.rsv,1010$+2 ; and sets rsv for all stack errors
;
@@ -566,10 +557,7 @@ ta0302:
;
; part 2: check that red zone does not have yellow islands -----------
;
2000$: cmpb systyp,#sy.e11 ; on e11 ?
beq 3000$ ; if yes skip, e11 still buggy here
;
mov #2300$,r0 ; ptr to values
2000$: mov #2300$,r0 ; ptr to values
mov #<2310$-2300$>/2,r1 ; # of values
vecset v..iit,2200$ ; set up iit handler
mov #1400,cp.slr ; set yellow limit to 1776
@@ -594,9 +582,10 @@ ta0302:
;
; part 3: check red zone PSW protection ------------------------------
; push to 177776 should also cause a red stack abort
; w11 and e11 implement this, SimH doesnt
;
3000$: tstb systyp ; only done in w11
ble 9999$
3000$: cmpb systyp,#sy.sih ; skip on SimH
beq 9999$
;
mov #1400,cp.slr ; set STKLIM
mov #1300,sp ; SP deep in red zone
@@ -624,10 +613,10 @@ ta0302:
; Notes:
; - dstw (mov,clr,..) and dstr (add,bis,...) flows write to stack -> test both
; - inspired by eqkce0 test 041 that verifies do/dont trap instruction cases
; - SimH and e11 currently do not support full 11/70 mode semantics
; - SimH currently does not support full 11/70 mode behaviour
;
ta0303: tstb systyp ; skip if not on w11
bge 100$
ta0303: cmpb systyp,#sy.sih ; skip on SimH
bne 100$
jmp 9999$
;
100$: mov #1400,cp.slr ; set yellow limit to 1776
@@ -825,7 +814,7 @@ ta0304: vecset v..iit,1000$,cp.pr7 ; set up iit handler, lockout interrupts
; Skipped on SimH that has different vector flow stack limit check logic.
; See also cpu_mmu tests C2.5,C2.6, they check vector push abort by mmu.
;
ta0305: cmpb systyp,#sy.sih ; skip in SimH (different stklim logic)
ta0305: cmpb systyp,#sy.sih ; skip on SimH (different stklim logic)
beq 9999$
;
vecset v..iit,200$,cp.pr5!cp0z0c ; set up iit handler, PR5+0Z0C as sig
@@ -1243,9 +1232,6 @@ ta0404: vecset v..bpt,vhtbpt,cp.pr7 ; BPT handler, PR7 (lockout PIRQ)
; that enabled the PIRQ interrupt.
;
3000$: mov #1,vhtbp0 ; ask BPT to lower priority
cmpb systyp,#sy.e11 ; skip on e11 (different service order)
beq 4000$
;
3001$: mov #3200$,r5
mov #3300$,vhtend
rttjmp #cp.t,#3100$
@@ -1272,12 +1258,9 @@ ta0404: vecset v..bpt,vhtbpt,cp.pr7 ; BPT handler, PR7 (lockout PIRQ)
; part 4: traced WAIT and tbit --------------------------------------
; Checks that traced WAIT does not produce tbit trap.
; Checks that SPL does not produce a tbit trap.
; Skipped on SimH which implements J11 semantics for SPL, WAIT, precedence.
; Skipped on SimH which implements J11 behavior for SPL, WAIT, precedence.
;
4000$:
cmpb systyp,#sy.sih ; skip on SimH
beq 5000$
cmpb systyp,#sy.e11 ; skip on e11 (for precedence)
4000$: cmpb systyp,#sy.sih ; skip on SimH
beq 5000$
;
4001$: mov #4200$,r5
@@ -1300,8 +1283,12 @@ ta0404: vecset v..bpt,vhtbpt,cp.pr7 ; BPT handler, PR7 (lockout PIRQ)
;
; part 5: WAIT and SPL in user mode ---------------------------------
; Checks that WAIT and SPL in user mode are traced (are nop)
; Checks that SPL in user mode is traced in w11 (unlike on 11/70)
; Skipped on e11 which implements 11/70 SPL behavior
;
5000$: mov #5200$,r5
5000$: cmpb systyp,#sy.e11 ; skip on e11
beq 6000$
mov #5200$,r5
mov #5300$,vhtend
rttjmp #cp.cmu+cp.t,#5100$ ; user mode, enable tbit
;

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@@ -37,5 +37,5 @@ Requires [patch](ekbbf0_patch_w11a.tcl). Still one diagnostic
### SimH remarks (tested with V3.12-3 RC2)
Requires [patch](ekbbf0_patch_1170.scmd).
### E11 remarks
_to come_
### E11 remarks (tested with V7.4 ALPHA 03/21/23)
Runs without patch.

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@@ -0,0 +1,16 @@
; $Id: ekbbf0_run.ecmd 1382 2023-03-18 21:02:11Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; e11 starter for ekbbf0 - PDP 11/70 cpu diagnostic part 2
;
@setup_w11a_basic.ecmd
;
mount pr: to_lda/ekbbf0.lda
boot/halt pr:
;
; Note: SW 03 up, thus test 042 executed (as for SimH)
set switch 004171
;
pc=200
go

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@@ -28,5 +28,5 @@ Requires [patch](ekbee1_patch_w11a.tcl).
### SimH remarks (tested with V3.12-3 RC2)
Requires [patch](ekbee1_patch_1170.scmd).
### E11 remarks
_to come_
### E11 remarks (tested with V7.4 ALPHA 03/21/23)
Requires [patch](ekbee1_patch_1170.ecmd).

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@@ -0,0 +1,30 @@
; $Id: ekbee1_patch_1170.ecmd 1383 2023-03-20 08:19:14Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Patch set ekbee1 for e11 -- e11 -- e11 -- e11 -- e11 -- e11 -- e11
;
; AP: patch test 50: 22-bit mapping carry propagation ------------------------
; The test does an access to 17000000, the first word of the UNIBUS
; window. It expects CPUERR 020 because UBMAP is disabled in MMR3.
; e11 supports UWIN, but is configured with NOUWIN and a memory hole to
; behave like w11 and Simh. So access aborts with nxm instead of timeout.
; Patch the testing instruction to it expects nxm in CPUERR
;
dep 052212 000040
;
; AP: patch test 122: KT BEND ------------------------------------------------
; Tests MMU vs NXM,ODD,RED behavior
; The 1st part tests NXM vs MMU. On a KB11-C handles NXM earlier then MMU (!)
; On a KB11-E MMU takes precedence (as one expects and SimH, e11, and w11 do).
; Patch the test such that is checks KB11-E behavior (beq 20$ -> nop)
;
dep 076224 000240
;
; HP: skip test 071: MMR2 pattern test ---------------------------------------
; this test tries all PC's in user mode --> skip to ease setting breakpoints
;
;; dep 057532 000137
;; dep 057534 057766
;
; break 077244

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@@ -1,6 +1,6 @@
; $Id: ekbee1_patch_1170.scmd 1336 2022-12-23 19:31:01Z mueller $
; $Id: ekbee1_patch_1170.scmd 1382 2023-03-18 21:02:11Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Patch set ekbee1 for SimH -- tested with SimH V3.12-3
;
@@ -38,7 +38,7 @@ dep 052212 000040
; AP: patch test 57: ACF = 5 -------------------------------------------------
; Tests 055, 056, and 057 verify trap response and check mmr0(6:1) which
; isn't frozen for traps. The instruction is 'mov mmr0,pmmr0' with the
; scr page 7 (IO page) and dst page 1 (where variables are). The test from
; src page 7 (IO page) and dst page 1 (where variables are). The test from
; expects for mmr0 011003, the destination page. With SimH one gets 011011,
; the last explicit update of MMR0. SimH only updates MMR0 when relevant
; and not on every access as a real 11/70 or w11 does.
@@ -83,7 +83,7 @@ dep 076300 000240
;
; The 2nd part tests RED vs MMU. On a 11/70 the MMR0 abort bits are not set
; in case of a stack in a non-resident page with an address below STKLIM.
; Simh, e11, and w11 do set the MMR0 abort bit, and take a fatal stack error.
; Simh and w11 do set the MMR0 abort bit, and take a fatal stack error.
; Patch test to change instruction under test 'clr (sp) -> clr -(sp)' so that
; the condition is really tested.
;

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@@ -1,6 +1,6 @@
# $Id: ekbee1_patch_w11a.tcl 1330 2022-12-16 17:52:40Z mueller $
# $Id: ekbee1_patch_w11a.tcl 1381 2023-03-12 12:16:45Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Patch set ekbee1 for w11a -- w11a -- w11a -- w11a -- w11a -- w11a
#
@@ -38,7 +38,7 @@ dep 052212 000040
# AP: patch test 57: ACF = 5 -------------------------------------------------
# Tests 055, 056, and 057 verify trap response and check mmr0(6:1) which
# isn't frozen for traps. The instruction is 'mov mmr0,pmmr0' with the
# scr page 7 (IO page) and dst page 1 (where variables are). The test
# src page 7 (IO page) and dst page 1 (where variables are). The test
# expects for mmr0 011003, the destination page. On w11 one gets 011017,
# the source page. Simply different flows. Certainly not an error.
# Patch the locations to avoid the diagnostic message.

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@@ -0,0 +1,23 @@
; $Id: ekbee1_run.ecmd 1318 2022-11-21 09:27:32Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; e11 starter for ekbee1 - 11/70 memory management
;
@setup_w11a_basic.ecmd
;
; set memory size to 3808 kB (from 3840 kB)
; that gives a 32 kB gap between top of memory and begin of UNIBUS window
; and enables the 1st section of test 122 to run (MMU vs NXM)
;
set memory 3808
;
mount pr: to_lda/ekbee1.lda
boot/halt pr:
;
set switch 004000
;
@ekbee1_patch_1170.ecmd
;
pc=200
go

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@@ -38,10 +38,10 @@ END PASS # 1 TOTAL ERRORS SINCE LAST REPORT 0
```
### w11 remarks
Runs without patches
Runs without patches.
### SimH remarks (tested with V3.12-3 RC2)
Requires [patch](eqkce1_patch_1170.scmd).
### E11 remarks
_to come_
### E11 remarks (tested with V7.4 ALPHA 03/21/23)
Runs without patches.

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@@ -0,0 +1,15 @@
; $Id: eqkce1_run.ecmd 1318 2022-11-21 09:27:32Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; e11 starter for eqkce1 - 11/70 instruction exerciser
;
@setup_w11a_basic.ecmd
;
mount pr: to_lda/eqkce1.lda
boot/halt pr:
;
set switch 014370
;
pc=200
go

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@@ -1,16 +1,21 @@
; $Id: setup_w11a_basic.ecmd 1314 2022-11-09 10:55:29Z mueller $
; $Id: setup_w11a_basic.ecmd 1382 2023-03-18 21:02:11Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; minimal configuration for xxdp tests. No devices except console
; set nouwin to disable UNIBUS window (17000000-17757777) to UNIBUS map
; set memory to 3840kB
; this way e11 behaves like w11 and SimH, which simplifies testing
;
; expects e11 V7.4 or a pre-release
;
set cpu 70
set cpu nouwin
set memory 3840
set cpu nofpp
;
set cpu mmumaint
;
set idle delay=1
; set ^E as break character (like in SimH)
set break 005