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add tcode/cpu_details.mac
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# $Id: cpu_all.dat 1257 2022-07-16 21:49:08Z mueller $
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# $Id: cpu_all.dat 1260 2022-07-21 06:07:00Z mueller $
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#
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## steering file for all cpu tests
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#
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cpu_basics.mac
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cpu_eis.mac
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cpu_details.mac
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cpu_badinst_nofpp.mac
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cpu_selftest.mac
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136
tools/tcode/cpu_details.mac
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136
tools/tcode/cpu_details.mac
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; $Id: cpu_details.mac 1259 2022-07-18 17:39:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-07-18 1259 1.0 Initial version
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;
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; Test CPU details
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; Section A: CPUERR
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; Section B: PIRQ
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; Section C: stress tests
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; Section D: 11/70 specifics
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;
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.include |lib/tcode_std_base.mac|
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;
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; Section B: PIRQ ============================================================
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;
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; Test B1: PIRQ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies operation of PIRQ register
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;
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; Test B1.1 -- PIRQ + spl ++++++++++++++++++++++++++++++++++++++++++++
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; This test will exercise all 7 pirq interrupt levels:
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; set 1+3 -> handle 3, set 7
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; -> handle 7, set 6+4
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; -> handle 6
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; -> handle 4, set 5+2
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; -> handle 5
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; -> handle 2
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; -> handle 1
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;
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; some useful definitions
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pi.r00=bit08 ; pir 0 bit
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pi.r01=bit09 ; pir 1 bit
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pi.r02=bit10 ; pir 2 bit
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pi.r03=bit11 ; pir 3 bit
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pi.r04=bit12 ; pir 4 bit
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pi.r05=bit13 ; pir 5 bit
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pi.r06=bit14 ; pir 6 bit
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pi.r07=bit15 ; pir 7 bit
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pi.n00=0. ; lsb for no pir pending
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pi.n01=1*042 ; lsb for pir 1 next
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pi.n02=2*042 ; lsb for pir 2 next
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pi.n03=3*042 ; lsb for pir 3 next
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pi.n04=4*042 ; lsb for pir 4 next
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pi.n05=5*042 ; lsb for pir 5 next
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pi.n06=6*042 ; lsb for pir 6 next
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pi.n07=7*042 ; lsb for pir 7 next
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;
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tb0101: mov #1000$,v..pir ; setup handler
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mov #cp.pr7,v..pir+2 ; which runs at pr7
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mov #cp.pir,r3 ; ptr to PIRQ
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mov #cp.psw,r4 ; ptr to PSW
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mov #1200$,r5 ; ptr to check data
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clr 1300$ ; clear nesting counter
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;
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spl 7 ; lockout interrupts
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bisb #bit01,1(r3) ; set PIRQ 1
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cmp (r3),#<pi.r01+pi.n01> ; check set 1
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beq .+4
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halt
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bisb #bit03,1(r3) ; set PIRQ 3
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cmp (r3),#<pi.r01+pi.r03+pi.n03> ; check set 1+3
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beq .+4
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halt
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spl 2
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nop ; allow interrupts to happen
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spl 0
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nop ; allow interrupts to happen
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tst (r3) ; PIRQ should clear now
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beq .+4
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halt
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mov #v..pir+2,v..pir; restore pirq vector catcher
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clr v..pir+2
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jmp 9999$
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;
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; PIRQ interrupt handler
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; - it starts at pr7 from the vector
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; - quickly lowers the priority to what is currently processed
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; - new pirq bits are set at lowered priority
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; - that leads to nested interrupts (tracked by a level counter)
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;
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1000$: inc 1300$ ; up level counter
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mov (r3),r0 ; get PIRQ value
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cmp 1300$,(r5)+ ; check nesting level
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beq .+4
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halt
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cmp r0,(r5)+ ; check pirq value
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beq .+4
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halt
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movb r0,(r4) ; PSW=PIRQ (sets priority)
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bic #177761,r0 ; mask out index bits
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mov r0,r1 ; r0 is word index (pri*2)
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asr r1 ; r1 is byte index (pri*1)
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mov #pi.r00,r2
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ash r1,r2 ; r2 = pi.r00 <<(pri)
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bic r2,(r3) ; clear current level in pirq
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bis 1100$(r0),(r3) ; trigger new pirqs
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nop ; allow nestec interrupts to happem
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nop ; "
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dec 1300$ ; down level counter
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rti
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;
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; table with new pirqs triggered at a level
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1100$: .word 0 ; new pirq @ level 0
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.word 0 ; new pirq @ level 1
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.word 0 ; new pirq @ level 2
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.word pi.r07 ; new pirq @ level 3 -> 7
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.word pi.r05+pi.r02 ; new pirq @ level 4 -> 5+2
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.word 0 ; new pirq @ level 5
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.word 0 ; new pirq @ level 6
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.word pi.r06+pi.r04 ; new pirq @ level 7 -> 6+4
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;
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; table with expected values of pirq register in interrupt sequence
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1200$: .word 1,pi.r01+pi.r03+pi.n03 ; set 1+3 -> handle 3, set 7
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.word 2,pi.r01+pi.r07+pi.n07 ; set 1+7 -> handle 7, set 6+4
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.word 2,pi.r01+pi.r04+pi.r06+pi.n06 ; set 1+4+6 -> handle 6
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.word 2,pi.r01+pi.r04+pi.n04 ; set 1+4 -> handle 4, set 5+2
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.word 3,pi.r01+pi.r02+pi.r05+pi.n05 ; set 1+2+5 -> handle 5
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.word 1,pi.r01+pi.r02+pi.n02 ; set 1+2 -> handle 2
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.word 1,pi.r01+pi.n01 ; set 1 -> handle 1
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; nesting level counter
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1300$: .word 0
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;
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9999$: iot ; end of test B1.1
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;
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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cmp tstno,#1. ; all tests done ?
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beq .+4
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halt
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;
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jmp loop
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;
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.end start
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