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add tools/tests, start with divtst [skip ci]

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1
doc/CHANGELOG.md
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@@ -38,6 +38,7 @@ The full set of tests is only run for tagged releases.
### New features
- new verification codes
- tools/tcode: fast cpu verification codes
- tools/tests: test programs
### Changes
- tools changes
- ci.yml: define TBW_GHDL_OPTS and suppress IEEE package warnings at t=0ms

1
tools/README.md
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@@ -17,5 +17,6 @@ This directory tree contains **many tools** and is organized in
| [sys](sys) | udev rules for USB device handling |
| [tbench](tbench) | w11 test bench |
| [tcode](tcode) | w11 test codes |
| [tests](tests) | test programs |
| [tcl](tcl) | TCL sources for rlink backend |
| [vivado](vivado) | scripts for Xilinx Vivado |

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tools/tests/README.md Normal file
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This directory tree contains **test programs** and is organized in
| Directory | Content |
| --------- | ------- |
| [divtst](divtst) | `divtst` program: test DIV instruction response |

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tools/tests/divtst/README.md Normal file
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## divtst: a test program testing DIV instruction response
The `divtst` program tests the `DIV` instruction with a set of test
cases and checks whether the response agrees with the expected values.
The program is available in two versions
- for BSD Unix systems, written in C and assembler, see directory [bsd](bsd)
- for RSX systems, written in MACRO-11 assembler, see directory [rsx](rsx)
Some results for different systems is available in directory [data](data).
The `divtst` program read the test cases from a file with the high and low part
of dividend and the divisor followed by _expected_ condition codes, quotient,
and remainder. All in octal like
```
; ddh ddl dr : nzvc q r # comments
000000 000000 000003 : 0100 000000 000000 # 0/ 3: 0, 0
000000 000004 000003 : 0000 000001 000001 # 4/ 3: 1, 1
025253 052525 125252 : 1000 100000 052525 # 715871573/-21846:-32768, 21845
000000 000000 000000 : 0111 000000 000000 # 0/ 0: 0, 0
025253 052527 125252 : 1010 025253 052527 # 715871575/-21846: 10923, 21847
```
The comment gives dividend, divisor, quotient, and remainder in decimal for
easier understanding, but is not interpreted by the program.
The output has the same format and contains _found_ condition codes quotient
and remainder. If the found response differs from the expected values
error indicators are added
```
CBAD for C mismatch
VBAD for V mismatch
ZBAD for Z mismatch (only checked if V=0)
NBAD for N mismatch (only checked if V=0)
QBAD for quotient mismatch (only checked if V=0)
RBAD for remainder mismatch (only checked if V=0)
```
Note that the N and Z condition codes are _unspecified_ for the `DIV`
instruction after a zero divide or overflow abort, which both set V=1.
The `w11` sets N=0 Z=1 for zero divide and Z=0 and N to the expected sign
of the result for an overflow. Same does SimH. The expected condition codes
in the file [tstall.dat](tstall.dat) are set like this for V=1 cases,
but not checked.
The state of the two result registers is also not specified when V=1 is set.
In some CPUs and some cases the registers preserve the original state, in other
cases, they are written. This is flagged with two markers
```
R0MOD for R0 changed when V=1 seen
R1MOD for R1 changed when V=1 seen
```
These markers do not indicate an error, they just flag how `DIV` behaves in
these unspecified cases.

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tools/tests/divtst/bsd/Makefile Normal file
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# $Id: Makefile 1266 2022-07-30 17:33:07Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
divtst : divtst.o dotst.o getpsw.o
cc -o divtst divtst.o dotst.o getpsw.o
divtst.o : divtst.c
cc -O -c divtst.c
clean :
rm -f *.o divtst

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tools/tests/divtst/bsd/README.md Normal file
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## divtst: BSD version
Copy all files from this directory and the files `testall.dat` and `veri.dat`
from the parent directorty to the target system. To build the task simply use
```
make
```
and to execute it use
```
./divtst <tstall.dat >tstall.log
./divtst <veri.dat >veri.log
```
The `DIV` test results are in file `tstall.log`.
The file `veri.log` checks the error flagging and should give an error for
each line.

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tools/tests/divtst/bsd/divtst.c Normal file
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/* $Id: divtst.c 1266 2022-07-30 17:33:07Z mueller $ */
/* SPDX-License-Identifier: GPL-3.0-or-later */
/* Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de> */
/* Revision History: */
/* Date Rev Version Comment */
/* 2014-07-24 570 1.0.1 use %06o throughout */
/* 2014-07-20 570 1.0 Initial version */
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
doline(ibuf, obuf, trace)
char *ibuf;
char *obuf;
int trace;
{
int idat[3];
int edat[3];
int odat[3];
int nscan;
int eccn, eccz, eccv, eccc;
int occn, occz, occv, occc;
int nout = 0;
if (trace) fprintf(stderr, "++line: '%s'\n", ibuf);
/* handle ; comment lines or empty lines, simply return */
if (ibuf[0]==0 || ibuf[0]==';') {
return 0;
}
/* handle # comment lines, simply copy and return */
if (ibuf[0] == '#') {
strcpy(obuf, ibuf);
return strlen(obuf);
}
/* handle command lines, parse input, quit on error */
nscan = sscanf(ibuf, "%o %o %o : %1d%1d%1d%1d %o %o",
idat+0, idat+1, idat+2,
&eccn, &eccz, &eccv, &eccc, edat+1, edat+2);
if (trace) {
fprintf(stderr, "++nscan: %d\n", nscan);
fprintf(stderr, "++idat: %06o %06o %06o\n",
idat[0], idat[1], idat[2]);
fprintf(stderr, "++edat: %d%d%d%d %06o %06o\n",
eccn, eccz, eccv, eccc, edat[1], edat[2]);
}
if (nscan != 9) return -1;
/* perform div test */
odat[0] = 0;
odat[1] = 0;
odat[2] = 0;
dotst(idat, odat);
occn = ((odat[0] & 010) != 0); /* returned N */
occz = ((odat[0] & 004) != 0); /* returned Z */
occv = ((odat[0] & 002) != 0); /* returned V */
occc = ((odat[0] & 001) != 0); /* returned C */
if (trace) {
fprintf(stderr, "++odat: %d%d%d%d %02o %06o %06o\n",
occn, occz, occv, occc, odat[0], odat[1], odat[2]);
}
nout += sprintf(obuf+nout, "%06o %06o %06o : %d%d%d%d %06o %06o",
idat[0], idat[1], idat[2],
occn, occz, occv, occc,
odat[1], odat[2]);
if (occv != eccv) nout += sprintf(obuf+nout, " VBAD");
if (occc != eccc) nout += sprintf(obuf+nout, " CBAD");
if (occv) { /* V=1 returned */
if (odat[1] != idat[0]) nout += sprintf(obuf+nout, " R0MOD");
if (odat[2] != idat[1]) nout += sprintf(obuf+nout, " R1MOD");
} else { /* V=0 returned */
if (occn != eccn) nout += sprintf(obuf+nout, " NBAD");
if (occz != eccz) nout += sprintf(obuf+nout, " ZBAD");
if (odat[1] != edat[1]) nout += sprintf(obuf+nout, " QBAD");
if (odat[2] != edat[2]) nout += sprintf(obuf+nout, " RBAD");
}
return strlen(obuf);
}
main(argc, argv)
int argc;
char *argv[];
{
char ibuf[132];
char obuf[132];
int trace = 0;
int argi;
for (argi=1; argi<argc; argi++) {
if (strcmp(argv[argi], "-v") == 0) trace = 1;
}
while (fgets(ibuf, 132, stdin)) {
int nout = 0;
int len = strlen(ibuf);
if (len>0 && ibuf[len-1] == '\n') ibuf[len-1] = 0;
obuf[0] = 0;
nout = doline(ibuf, obuf, trace);
if (nout < 0) {
fprintf(stderr, "divtst-E: bad input line '%s'\n", ibuf);
fprintf(stderr, "divtst-E: aborting divtst\n");
exit(1);
}
if (nout > 0) fprintf(stdout, "%s\n", obuf);
}
exit(0);
}

49
tools/tests/divtst/bsd/dotst.s Normal file
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/ $Id: dotst.s 1266 2022-07-30 17:33:07Z mueller $
/ SPDX-License-Identifier: GPL-3.0-or-later
/ Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/
/ called from C as
/ dotst(idat, odat)
/ with
/ idat[0] divident high (even r)
/ idat[1] divident low (odd r)
/ idat[2] divisor
/ and returns in odat
/ odat[0] psw
/ odat[1] quotient (even r)
/ odat[2] reminder (odd r)
/
/ Revision History:
/ Date Rev Version Comment
/ 2014-07-20 570 1.0 Initial version
/
.globl _dotst
.text
_dotst: mov r2,-(sp) / save r2 (r0,r1 are volatile)
/ now (sp) -> saved r2
/ 2(sp) -> return address
/ 4(sp) -> 1st arg: idat
/ 6(sp) -> 2ns arg: odat
mov 4(sp), r2 / r2 = idat
mov (r2), r0 / load dd high
mov 2(r2),r1 / load dd low
div 4(r2),r0 / do divide
jsr pc, getpsw / obtain psw in user mode
mov 6(sp), r2 / r2 = odat
mov valpsw, (r2) / store psw
mov r0, 2(r2) / store quotient
mov r1, 4(r2) / store remainder
mov (sp)+,r2 / restore r2
rts pc

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tools/tests/divtst/bsd/getpsw.s Normal file
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/ $Id: getpsw.s 1266 2022-07-30 17:33:07Z mueller $
/ SPDX-License-Identifier: GPL-3.0-or-later
/ Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
/
/ Revision History:
/ Date Rev Version Comment
/ 2014-07-20 570 1.0 Initial version
/
.globl valpsw
.data
valpsw: 0
.text
.globl getpsw
getpsw:
bmi cc1xxx / branch on N=1
beq cc01xx / branch on N=0,Z=1
bvs cc001x / branch on N=0,Z=0,V=1
bcs cc0001 / branch on N=0,Z=0,V=0,C=1
mov $000, valpsw / here N=0,Z=0,V=0,C=0
rts pc
cc0001: mov $001, valpsw / here N=0,Z=0,V=0,C=1
rts pc
cc001x: bcs cc0011 / branch on N=0,Z=0,V=1,C=1
mov $002, valpsw / here N=0,Z=0,V=1,C=0
rts pc
cc0011: mov $003, valpsw / here N=0,Z=0,V=1,C=1
rts pc
cc01xx: bvs cc011x / branch on N=0,Z=1,V=1
bcs cc0101 / branch on N=0,Z=1,V=0,C=1
mov $004, valpsw / here N=0,Z=1,V=0,C=0
rts pc
cc0101: mov $005, valpsw / here N=0,Z=1,V=0,C=1
rts pc
cc011x: bcs cc0111 / branch on N=0,Z=1,V=1,C=1
mov $006, valpsw / here N=0,Z=1,V=1,C=0
rts pc
cc0111: mov $007, valpsw / here N=0,Z=1,V=1,C=1
rts pc
cc1xxx: beq cc01xx / branch on N=1,Z=1
bvs cc001x / branch on N=1,Z=0,V=1
bcs cc1001 / branch on N=1,Z=0,V=0,C=1
mov $010, valpsw / here N=1,Z=0,V=0,C=0
rts pc
cc1001: mov $011, valpsw / here N=1,Z=0,V=0,C=1
rts pc
cc101x: bcs cc1011 / branch on N=1,Z=0,V=1,C=1
mov $012, valpsw / here N=1,Z=0,V=1,C=0
rts pc
cc1011: mov $013, valpsw / here N=1,Z=0,V=1,C=1
rts pc
cc11xx: bvs cc111x / branch on N=1,Z=1,V=1
bcs cc1101 / branch on N=1,Z=1,V=0,C=1
mov $014, valpsw / here N=1,Z=1,V=0,C=0
rts pc
cc1101: mov $015, valpsw / here N=1,Z=1,V=0,C=1
rts pc
cc111x: bcs cc1111 / branch on N=1,Z=1,V=1,C=1
mov $016, valpsw / here N=1,Z=1,V=1,C=0
rts pc
cc1111: mov $017, valpsw / here N=1,Z=1,V=1,C=1
rts pc

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tools/tests/divtst/data/2014-08-22_1170_btq.log Normal file
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# test_div: test div instruction
# test basics (via testd2)
# dr>0
000000 000000 000003 : 0100 000000 000000
000000 000001 000003 : 0100 000000 000001
000000 000002 000003 : 0100 000000 000002
000000 000003 000003 : 0000 000001 000000
000000 000004 000003 : 0000 000001 000001
177777 177777 000003 : 0100 000000 177777
177777 177776 000003 : 0100 000000 177776
177777 177775 000003 : 1000 177777 000000
177777 177774 000003 : 1000 177777 177777
# dr<0
000000 000000 177775 : 0100 000000 000000
000000 000001 177775 : 0100 000000 000001
000000 000002 177775 : 0100 000000 000002
000000 000003 177775 : 1000 177777 000000
000000 000004 177775 : 1000 177777 000001
177777 177777 177775 : 0100 000000 177777
177777 177776 177775 : 0100 000000 177776
177777 177775 177775 : 0000 000001 000000
177777 177774 177775 : 0000 000001 177777
# dr==0
000000 000000 000000 : 0111 000000 000000
000000 000001 000000 : 0111 000000 000001
177777 177777 000000 : 0111 177777 177777
# test 4 quadrant basics (via testd2)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test 4 quadrant basics (via testdqr)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test q=100000 boundary cases (q = max neg value)
# case dd>0, dr<0 -- factor 21846
025253 000000 125252 : 1000 100000 000000
025253 000001 125252 : 1000 100000 000001
025253 052524 125252 : 1000 100000 052524
025253 052525 125252 : 1000 100000 052525
025253 052526 125252 : 0110 077777 000000 R0MOD R1MOD
025253 052527 125252 : 0110 077777 000001 R0MOD R1MOD
# case dd<0, dr>0 -- factor 21846
152525 000000 052526 : 1000 100000 000000
152524 177777 052526 : 1000 100000 177777
152524 125254 052526 : 1000 100000 125254
152524 125253 052526 : 1000 100000 125253
152524 125252 052526 : 0110 077777 000000 R0MOD R1MOD
152524 125251 052526 : 0110 077777 177777 R0MOD R1MOD
# case dd>0, dr<0 -- factor 21847
025253 100000 125251 : 1000 100000 000000
025253 100001 125251 : 1000 100000 000001
025253 152525 125251 : 1000 100000 052525
025253 152526 125251 : 1000 100000 052526
025253 152527 125251 : 0110 077777 000000 R0MOD R1MOD
025253 152530 125251 : 0110 077777 000001 R0MOD R1MOD
# case dd<0, dr>0 -- factor 21847
152524 100000 052527 : 1000 100000 000000
152524 077777 052527 : 1000 100000 177777
152524 025253 052527 : 1000 100000 125253
152524 025252 052527 : 1000 100000 125252
152524 025251 052527 : 0110 077777 000000 R0MOD R1MOD
152524 025250 052527 : 0110 077777 177777 R0MOD R1MOD
# test q=077777 boundary cases (q = max pos value)
# case dd>0, dr>0 -- factor 21846
025252 125252 052526 : 0000 077777 000000
025252 125253 052526 : 0000 077777 000001
025252 177776 052526 : 0000 077777 052524
025252 177777 052526 : 0000 077777 052525
025253 000000 052526 : 0110 025253 000000
025253 000001 052526 : 0110 025253 000001
# case dd<0, dr<0 -- factor 21846
152525 052526 125252 : 0000 077777 000000
152525 052525 125252 : 0000 077777 177777
152525 000002 125252 : 0000 077777 125254
152525 000001 125252 : 0000 077777 125253
152525 000000 125252 : 0110 025253 000000 R0MOD
152524 177777 125252 : 0110 025253 000001 R0MOD R1MOD
# case dd>0, dr>0 -- factor 21847
025253 025251 052527 : 0000 077777 000000
025253 025252 052527 : 0000 077777 000001
025253 077776 052527 : 0000 077777 052525
025253 077777 052527 : 0000 077777 052526
025253 100000 052527 : 0110 025253 100000
025253 100001 052527 : 0110 025253 100001
# case dd<0, dr<0 -- factor 21847
152524 152527 125251 : 0000 077777 000000
152524 152526 125251 : 0000 077777 177777
152524 100002 125251 : 0000 077777 125253
152524 100001 125251 : 0000 077777 125252
152524 100001 125251 : 0000 077777 125252
152524 100000 125251 : 0110 025253 100000 R0MOD
# test dr=100000 boundary cases (dr = max neg value)
# case dd<0, q>0
177777 100000 100000 : 0000 000001 000000
177777 077777 100000 : 0000 000001 177777
177777 000001 100000 : 0000 000001 100001
177777 000000 100000 : 0000 000002 000000
177776 177777 100000 : 0000 000002 177777
177776 100001 100000 : 0000 000002 100001
177776 100000 100000 : 0000 000003 000000
177776 077777 100000 : 0000 000003 177777
177776 000001 100000 : 0000 000003 100001
177776 000000 100000 : 0000 000004 000000
177775 177777 100000 : 0000 000004 177777
177775 100001 100000 : 0000 000004 100001
177775 000000 100000 : 0000 000006 000000
140003 000000 100000 : 0000 077772 000000
140002 000000 100000 : 0000 077774 000000
140001 100000 100000 : 0000 077775 000000
140001 000000 100000 : 0000 077776 000000
140000 177777 100000 : 0000 077776 177777
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000001 100000 : 0000 077777 100001
# case dd>0, q<0
000000 100000 100000 : 1000 177777 000000
000000 100001 100000 : 1000 177777 000001
000000 177777 100000 : 1000 177777 077777
000001 000000 100000 : 1000 177776 000000
000001 000001 100000 : 1000 177776 000001
000001 077777 100000 : 1000 177776 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077777 100000 : 1000 100000 077777
# test dr=077777 boundary cases (dr = max pos value)
# case dd>0, q>0
000000 077777 077777 : 0000 000001 000000
000000 100000 077777 : 0000 000001 000001
000000 177775 077777 : 0000 000001 077776
000000 177776 077777 : 0000 000002 000000
000000 177777 077777 : 0000 000002 000001
000001 077774 077777 : 0000 000002 077776
037776 100002 077777 : 0000 077776 000000
037776 100003 077777 : 0000 077776 000001
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077777 077777 : 0000 077777 077776
# case dd<0, q<0
177777 100001 077777 : 1000 177777 000000
177777 100000 077777 : 1000 177777 177777
177777 000003 077777 : 1000 177777 100002
177777 000002 077777 : 1000 177776 000000
177777 000001 077777 : 1000 177776 177777
177776 100004 077777 : 1000 177776 100002
140000 177777 077777 : 1000 100001 000000
140000 177776 077777 : 1000 100001 177777
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000002 077777 : 1000 100000 100002
# test dd max cases
# case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077776 100000 : 1000 100000 077776
040000 077777 100000 : 1000 100000 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
# case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077776 077777 : 0000 077777 077775
037777 077777 077777 : 0000 077777 077776
037777 100000 077777 : 0110 037777 100000
037776 100001 077777 : 0000 077775 077776
# case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000003 077777 : 1000 100000 100003
140000 000002 077777 : 1000 100000 100002
140000 000001 077777 : 0110 077777 000000 R0MOD R1MOD
140000 000000 077777 : 0010 040000 000000 R0MOD
# case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000002 100000 : 0000 077777 100002
140000 000001 100000 : 0000 077777 100001
140000 000000 100000 : 0110 040000 000000 R0MOD
137777 177777 100000 : 0110 040000 000001 R0MOD R1MOD
# test late div quit cases in 2 quadrant algorithm
177777 100001 177777 : 0000 077777 000000
177777 100000 177777 : 0110 000000 100000 R0MOD
177777 077777 177777 : 0110 000000 100001 R0MOD R1MOD
177777 000002 177776 : 0000 077777 000000
177777 000001 177776 : 0000 077777 177777
177777 000000 177776 : 0110 000001 000000 R0MOD
177776 177777 177776 : 0110 000001 000001 R0MOD R1MOD
# test big divident overflow cases
077777 177777 000001 : 0010 077777 177777
077777 177777 000002 : 0010 077777 177777
077777 177777 177777 : 0010 077777 177777
077777 177777 177776 : 0010 077777 177777
100000 000000 000001 : 0110 100000 000000
100000 000000 000002 : 0110 100000 000000
100000 000000 177777 : 0110 100000 000000
100000 000000 177776 : 0110 100000 000000

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# test_div: test div instruction
# test basics (via testd2)
# dr>0
000000 000000 000003 : 0100 000000 000000
000000 000001 000003 : 0100 000000 000001
000000 000002 000003 : 0100 000000 000002
000000 000003 000003 : 0000 000001 000000
000000 000004 000003 : 0000 000001 000001
177777 177777 000003 : 0100 000000 177777
177777 177776 000003 : 0100 000000 177776
177777 177775 000003 : 1000 177777 000000
177777 177774 000003 : 1000 177777 177777
# dr<0
000000 000000 177775 : 0100 000000 000000
000000 000001 177775 : 0100 000000 000001
000000 000002 177775 : 0100 000000 000002
000000 000003 177775 : 1000 177777 000000
000000 000004 177775 : 1000 177777 000001
177777 177777 177775 : 0100 000000 177777
177777 177776 177775 : 0100 000000 177776
177777 177775 177775 : 0000 000001 000000
177777 177774 177775 : 0000 000001 177777
# dr==0
000000 000000 000000 : 0111 000000 000000
000000 000001 000000 : 0111 000000 000001
177777 177777 000000 : 0111 177777 177777
# test 4 quadrant basics (via testd2)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test 4 quadrant basics (via testdqr)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test q=100000 boundary cases (q = max neg value)
# case dd>0, dr<0 -- factor 21846
025253 000000 125252 : 1000 100000 000000
025253 000001 125252 : 1000 100000 000001
025253 052524 125252 : 1000 100000 052524
025253 052525 125252 : 1000 100000 052525
025253 052526 125252 : 0010 025253 052526
025253 052527 125252 : 0010 025253 052527
# case dd<0, dr>0 -- factor 21846
152525 000000 052526 : 1000 100000 000000
152524 177777 052526 : 1000 100000 177777
152524 125254 052526 : 1000 100000 125254
152524 125253 052526 : 1000 100000 125253
152524 125252 052526 : 0010 152524 125252
152524 125251 052526 : 0010 152524 125251
# case dd>0, dr<0 -- factor 21847
025253 100000 125251 : 1000 100000 000000
025253 100001 125251 : 1000 100000 000001
025253 152525 125251 : 1000 100000 052525
025253 152526 125251 : 1000 100000 052526
025253 152527 125251 : 0010 025253 152527
025253 152530 125251 : 0010 025253 152530
# case dd<0, dr>0 -- factor 21847
152524 100000 052527 : 1000 100000 000000
152524 077777 052527 : 1000 100000 177777
152524 025253 052527 : 1000 100000 125253
152524 025252 052527 : 1000 100000 125252
152524 025251 052527 : 0010 152524 025251
152524 025250 052527 : 0010 152524 025250
# test q=077777 boundary cases (q = max pos value)
# case dd>0, dr>0 -- factor 21846
025252 125252 052526 : 0000 077777 000000
025252 125253 052526 : 0000 077777 000001
025252 177776 052526 : 0000 077777 052524
025252 177777 052526 : 0000 077777 052525
025253 000000 052526 : 0010 025253 000000
025253 000001 052526 : 0010 025253 000001
# case dd<0, dr<0 -- factor 21846
152525 052526 125252 : 0000 077777 000000
152525 052525 125252 : 0000 077777 177777
152525 000002 125252 : 0000 077777 125254
152525 000001 125252 : 0000 077777 125253
152525 000000 125252 : 0010 152525 000000
152524 177777 125252 : 0010 152524 177777
# case dd>0, dr>0 -- factor 21847
025253 025251 052527 : 0000 077777 000000
025253 025252 052527 : 0000 077777 000001
025253 077776 052527 : 0000 077777 052525
025253 077777 052527 : 0000 077777 052526
025253 100000 052527 : 0010 025253 100000
025253 100001 052527 : 0010 025253 100001
# case dd<0, dr<0 -- factor 21847
152524 152527 125251 : 0000 077777 000000
152524 152526 125251 : 0000 077777 177777
152524 100002 125251 : 0000 077777 125253
152524 100001 125251 : 0000 077777 125252
152524 100001 125251 : 0000 077777 125252
152524 100000 125251 : 0010 152524 100000
# test dr=100000 boundary cases (dr = max neg value)
# case dd<0, q>0
177777 100000 100000 : 0000 000001 000000
177777 077777 100000 : 0000 000001 177777
177777 000001 100000 : 0000 000001 100001
177777 000000 100000 : 0000 000002 000000
177776 177777 100000 : 0000 000002 177777
177776 100001 100000 : 0000 000002 100001
177776 100000 100000 : 0000 000003 000000
177776 077777 100000 : 0000 000003 177777
177776 000001 100000 : 0000 000003 100001
177776 000000 100000 : 0000 000004 000000
177775 177777 100000 : 0000 000004 177777
177775 100001 100000 : 0000 000004 100001
177775 000000 100000 : 0000 000006 000000
140003 000000 100000 : 0000 077772 000000
140002 000000 100000 : 0000 077774 000000
140001 100000 100000 : 0000 077775 000000
140001 000000 100000 : 0000 077776 000000
140000 177777 100000 : 0000 077776 177777
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000001 100000 : 0000 077777 100001
# case dd>0, q<0
000000 100000 100000 : 1000 177777 000000
000000 100001 100000 : 1000 177777 000001
000000 177777 100000 : 1000 177777 077777
000001 000000 100000 : 1000 177776 000000
000001 000001 100000 : 1000 177776 000001
000001 077777 100000 : 1000 177776 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077777 100000 : 1000 100000 077777
# test dr=077777 boundary cases (dr = max pos value)
# case dd>0, q>0
000000 077777 077777 : 0000 000001 000000
000000 100000 077777 : 0000 000001 000001
000000 177775 077777 : 0000 000001 077776
000000 177776 077777 : 0000 000002 000000
000000 177777 077777 : 0000 000002 000001
000001 077774 077777 : 0000 000002 077776
037776 100002 077777 : 0000 077776 000000
037776 100003 077777 : 0000 077776 000001
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077777 077777 : 0000 077777 077776
# case dd<0, q<0
177777 100001 077777 : 1000 177777 000000
177777 100000 077777 : 1000 177777 177777
177777 000003 077777 : 1000 177777 100002
177777 000002 077777 : 1000 177776 000000
177777 000001 077777 : 1000 177776 177777
177776 100004 077777 : 1000 177776 100002
140000 177777 077777 : 1000 100001 000000
140000 177776 077777 : 1000 100001 177777
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000002 077777 : 1000 100000 100002
# test dd max cases
# case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077776 100000 : 1000 100000 077776
040000 077777 100000 : 1000 100000 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
# case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077776 077777 : 0000 077777 077775
037777 077777 077777 : 0000 077777 077776
037777 100000 077777 : 0010 037777 100000
037776 100001 077777 : 0000 077775 077776
# case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000003 077777 : 1000 100000 100003
140000 000002 077777 : 1000 100000 100002
140000 000001 077777 : 0010 140000 000001
140000 000000 077777 : 0010 140000 000000
# case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000002 100000 : 0000 077777 100002
140000 000001 100000 : 0000 077777 100001
140000 000000 100000 : 0010 140000 000000
137777 177777 100000 : 0010 137777 177777
# test late div quit cases in 2 quadrant algorithm
177777 100001 177777 : 0000 077777 000000
177777 100000 177777 : 0010 177777 100000
177777 077777 177777 : 0010 177777 077777
177777 000002 177776 : 0000 077777 000000
177777 000001 177776 : 0000 077777 177777
177777 000000 177776 : 0010 177777 000000
177776 177777 177776 : 0010 177776 177777
# test big divident overflow cases
077777 177777 000001 : 0010 077777 177777
077777 177777 000002 : 0010 077777 177777
077777 177777 177777 : 0010 077777 177777
077777 177777 177776 : 0010 077777 177777
100000 000000 000001 : 0010 100000 000000
100000 000000 000002 : 0010 100000 000000
100000 000000 177777 : 0010 100000 000000
100000 000000 177776 : 0010 100000 000000

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# test_div: test div instruction
# test basics (via testd2)
# dr>0
000000 000000 000003 : 0100 000000 000000
000000 000001 000003 : 0100 000000 000001
000000 000002 000003 : 0100 000000 000002
000000 000003 000003 : 0000 000001 000000
000000 000004 000003 : 0000 000001 000001
177777 177777 000003 : 0100 000000 177777
177777 177776 000003 : 0100 000000 177776
177777 177775 000003 : 1000 177777 000000
177777 177774 000003 : 1000 177777 177777
# dr<0
000000 000000 177775 : 0100 000000 000000
000000 000001 177775 : 0100 000000 000001
000000 000002 177775 : 0100 000000 000002
000000 000003 177775 : 1000 177777 000000
000000 000004 177775 : 1000 177777 000001
177777 177777 177775 : 0100 000000 177777
177777 177776 177775 : 0100 000000 177776
177777 177775 177775 : 0000 000001 000000
177777 177774 177775 : 0000 000001 177777
# dr==0
000000 000000 000000 : 0111 000000 000000
000000 000001 000000 : 0011 000000 000001
177777 177777 000000 : 0011 177777 177777
# test 4 quadrant basics (via testd2)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test 4 quadrant basics (via testdqr)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test q=100000 boundary cases (q = max neg value)
# case dd>0, dr<0 -- factor 21846
025253 000000 125252 : 1000 100000 000000
025253 000001 125252 : 1000 100000 000001
025253 052524 125252 : 1000 100000 052524
025253 052525 125252 : 1000 100000 052525
025253 052526 125252 : 0010 077777 000000 R0MOD R1MOD
025253 052527 125252 : 0010 077777 000001 R0MOD R1MOD
# case dd<0, dr>0 -- factor 21846
152525 000000 052526 : 1000 100000 000000
152524 177777 052526 : 1000 100000 177777
152524 125254 052526 : 1000 100000 125254
152524 125253 052526 : 1000 100000 125253
152524 125252 052526 : 0010 077777 000000 R0MOD R1MOD
152524 125251 052526 : 0010 077777 177777 R0MOD R1MOD
# case dd>0, dr<0 -- factor 21847
025253 100000 125251 : 1000 100000 000000
025253 100001 125251 : 1000 100000 000001
025253 152525 125251 : 1000 100000 052525
025253 152526 125251 : 1000 100000 052526
025253 152527 125251 : 0010 077777 000000 R0MOD R1MOD
025253 152530 125251 : 0010 077777 000001 R0MOD R1MOD
# case dd<0, dr>0 -- factor 21847
152524 100000 052527 : 1000 100000 000000
152524 077777 052527 : 1000 100000 177777
152524 025253 052527 : 1000 100000 125253
152524 025252 052527 : 1000 100000 125252
152524 025251 052527 : 0010 077777 000000 R0MOD R1MOD
152524 025250 052527 : 0010 077777 177777 R0MOD R1MOD
# test q=077777 boundary cases (q = max pos value)
# case dd>0, dr>0 -- factor 21846
025252 125252 052526 : 0000 077777 000000
025252 125253 052526 : 0000 077777 000001
025252 177776 052526 : 0000 077777 052524
025252 177777 052526 : 0000 077777 052525
025253 000000 052526 : 0010 100000 000000 R0MOD
025253 000001 052526 : 0010 100000 000001 R0MOD
# case dd<0, dr<0 -- factor 21846
152525 052526 125252 : 0000 077777 000000
152525 052525 125252 : 0000 077777 177777
152525 000002 125252 : 0000 077777 125254
152525 000001 125252 : 0000 077777 125253
152525 000000 125252 : 0010 100000 000000 R0MOD
152524 177777 125252 : 0010 100000 177777 R0MOD
# case dd>0, dr>0 -- factor 21847
025253 025251 052527 : 0000 077777 000000
025253 025252 052527 : 0000 077777 000001
025253 077776 052527 : 0000 077777 052525
025253 077777 052527 : 0000 077777 052526
025253 100000 052527 : 0010 100000 000000 R0MOD R1MOD
025253 100001 052527 : 0010 100000 000001 R0MOD R1MOD
# case dd<0, dr<0 -- factor 21847
152524 152527 125251 : 0000 077777 000000
152524 152526 125251 : 0000 077777 177777
152524 100002 125251 : 0000 077777 125253
152524 100001 125251 : 0000 077777 125252
152524 100001 125251 : 0000 077777 125252
152524 100000 125251 : 0010 100000 000000 R0MOD R1MOD
# test dr=100000 boundary cases (dr = max neg value)
# case dd<0, q>0
177777 100000 100000 : 0000 000001 000000
177777 077777 100000 : 0000 000001 177777
177777 000001 100000 : 0000 000001 100001
177777 000000 100000 : 0000 000002 000000
177776 177777 100000 : 0000 000002 177777
177776 100001 100000 : 0000 000002 100001
177776 100000 100000 : 0000 000003 000000
177776 077777 100000 : 0000 000003 177777
177776 000001 100000 : 0000 000003 100001
177776 000000 100000 : 0000 000004 000000
177775 177777 100000 : 0000 000004 177777
177775 100001 100000 : 0000 000004 100001
177775 000000 100000 : 0000 000006 000000
140003 000000 100000 : 0000 077772 000000
140002 000000 100000 : 0000 077774 000000
140001 100000 100000 : 0000 077775 000000
140001 000000 100000 : 0000 077776 000000
140000 177777 100000 : 0000 077776 177777
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000001 100000 : 0000 077777 100001
# case dd>0, q<0
000000 100000 100000 : 1000 177777 000000
000000 100001 100000 : 1000 177777 000001
000000 177777 100000 : 1000 177777 077777
000001 000000 100000 : 1000 177776 000000
000001 000001 100000 : 1000 177776 000001
000001 077777 100000 : 1000 177776 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077777 100000 : 1000 100000 077777
# test dr=077777 boundary cases (dr = max pos value)
# case dd>0, q>0
000000 077777 077777 : 0000 000001 000000
000000 100000 077777 : 0000 000001 000001
000000 177775 077777 : 0000 000001 077776
000000 177776 077777 : 0000 000002 000000
000000 177777 077777 : 0000 000002 000001
000001 077774 077777 : 0000 000002 077776
037776 100002 077777 : 0000 077776 000000
037776 100003 077777 : 0000 077776 000001
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077777 077777 : 0000 077777 077776
# case dd<0, q<0
177777 100001 077777 : 1000 177777 000000
177777 100000 077777 : 1000 177777 177777
177777 000003 077777 : 1000 177777 100002
177777 000002 077777 : 1000 177776 000000
177777 000001 077777 : 1000 177776 177777
177776 100004 077777 : 1000 177776 100002
140000 177777 077777 : 1000 100001 000000
140000 177776 077777 : 1000 100001 177777
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000002 077777 : 1000 100000 100002
# test dd max cases
# case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077776 100000 : 1000 100000 077776
040000 077777 100000 : 1000 100000 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
# case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077776 077777 : 0000 077777 077775
037777 077777 077777 : 0000 077777 077776
037777 100000 077777 : 0010 100000 000000 R0MOD R1MOD
037776 100001 077777 : 0000 077775 077776
# case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000003 077777 : 1000 100000 100003
140000 000002 077777 : 1000 100000 100002
140000 000001 077777 : 0010 077777 000000 R0MOD R1MOD
140000 000000 077777 : 0010 077777 177777 R0MOD R1MOD
# case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000002 100000 : 0000 077777 100002
140000 000001 100000 : 0000 077777 100001
140000 000000 100000 : 0010 100000 000000 R0MOD
137777 177777 100000 : 0010 100000 177777 R0MOD
# test late div quit cases in 2 quadrant algorithm
177777 100001 177777 : 0000 077777 000000
177777 100000 177777 : 0010 100000 000000 R0MOD R1MOD
177777 077777 177777 : 0010 100001 000000 R0MOD R1MOD
177777 000002 177776 : 0000 077777 000000
177777 000001 177776 : 0000 077777 177777
177777 000000 177776 : 0010 100000 000000 R0MOD
177776 177777 177776 : 0010 100000 177777 R0MOD
# test big divident overflow cases
077777 177777 000001 : 0010 177777 000000 R0MOD R1MOD
077777 177777 000002 : 0010 177777 000001 R0MOD R1MOD
077777 177777 177777 : 0010 000001 000000 R0MOD R1MOD
077777 177777 177776 : 0010 000001 000001 R0MOD R1MOD
100000 000000 000001 : 0110 000000 000000 R0MOD
100000 000000 000002 : 0110 000000 000000 R0MOD
100000 000000 177777 : 0110 000000 000000 R0MOD
100000 000000 177776 : 0110 000000 000000 R0MOD

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# test_div: test div instruction
# test basics (via testd2)
# dr>0
000000 000000 000003 : 0100 000000 000000
000000 000001 000003 : 0100 000000 000001
000000 000002 000003 : 0100 000000 000002
000000 000003 000003 : 0000 000001 000000
000000 000004 000003 : 0000 000001 000001
177777 177777 000003 : 0100 000000 177777
177777 177776 000003 : 0100 000000 177776
177777 177775 000003 : 1000 177777 000000
177777 177774 000003 : 1000 177777 177777
# dr<0
000000 000000 177775 : 0100 000000 000000
000000 000001 177775 : 0100 000000 000001
000000 000002 177775 : 0100 000000 000002
000000 000003 177775 : 1000 177777 000000
000000 000004 177775 : 1000 177777 000001
177777 177777 177775 : 0100 000000 177777
177777 177776 177775 : 0100 000000 177776
177777 177775 177775 : 0000 000001 000000
177777 177774 177775 : 0000 000001 177777
# dr==0
000000 000000 000000 : 0111 000000 000000
000000 000001 000000 : 0111 000000 000001
177777 177777 000000 : 0111 177777 177777
# test 4 quadrant basics (via testd2)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test 4 quadrant basics (via testdqr)
000000 000042 000005 : 0000 000006 000004
000000 000042 177773 : 1000 177772 000004
177777 177736 000005 : 1000 177772 177774
177777 177736 177773 : 0000 000006 177774
# test q=100000 boundary cases (q = max neg value)
# case dd>0, dr<0 -- factor 21846
025253 000000 125252 : 1000 100000 000000
025253 000001 125252 : 1000 100000 000001
025253 052524 125252 : 1000 100000 052524
025253 052525 125252 : 1000 100000 052525
025253 052526 125252 : 0010 025253 052526
025253 052527 125252 : 0010 025253 052527
# case dd<0, dr>0 -- factor 21846
152525 000000 052526 : 1000 100000 000000
152524 177777 052526 : 1000 100000 177777
152524 125254 052526 : 1000 100000 125254
152524 125253 052526 : 1000 100000 125253
152524 125252 052526 : 0010 152524 125252
152524 125251 052526 : 0010 152524 125251
# case dd>0, dr<0 -- factor 21847
025253 100000 125251 : 1000 100000 000000
025253 100001 125251 : 1000 100000 000001
025253 152525 125251 : 1000 100000 052525
025253 152526 125251 : 1000 100000 052526
025253 152527 125251 : 0010 025253 152527
025253 152530 125251 : 0010 025253 152530
# case dd<0, dr>0 -- factor 21847
152524 100000 052527 : 1000 100000 000000
152524 077777 052527 : 1000 100000 177777
152524 025253 052527 : 1000 100000 125253
152524 025252 052527 : 1000 100000 125252
152524 025251 052527 : 0010 152524 025251
152524 025250 052527 : 0010 152524 025250
# test q=077777 boundary cases (q = max pos value)
# case dd>0, dr>0 -- factor 21846
025252 125252 052526 : 0000 077777 000000
025252 125253 052526 : 0000 077777 000001
025252 177776 052526 : 0000 077777 052524
025252 177777 052526 : 0000 077777 052525
025253 000000 052526 : 0010 025253 000000
025253 000001 052526 : 0010 025253 000001
# case dd<0, dr<0 -- factor 21846
152525 052526 125252 : 0000 077777 000000
152525 052525 125252 : 0000 077777 177777
152525 000002 125252 : 0000 077777 125254
152525 000001 125252 : 0000 077777 125253
152525 000000 125252 : 0010 152525 000000
152524 177777 125252 : 0010 152524 177777
# case dd>0, dr>0 -- factor 21847
025253 025251 052527 : 0000 077777 000000
025253 025252 052527 : 0000 077777 000001
025253 077776 052527 : 0000 077777 052525
025253 077777 052527 : 0000 077777 052526
025253 100000 052527 : 0010 025253 100000
025253 100001 052527 : 0010 025253 100001
# case dd<0, dr<0 -- factor 21847
152524 152527 125251 : 0000 077777 000000
152524 152526 125251 : 0000 077777 177777
152524 100002 125251 : 0000 077777 125253
152524 100001 125251 : 0000 077777 125252
152524 100001 125251 : 0000 077777 125252
152524 100000 125251 : 0010 152524 100000
# test dr=100000 boundary cases (dr = max neg value)
# case dd<0, q>0
177777 100000 100000 : 0000 000001 000000
177777 077777 100000 : 0000 000001 177777
177777 000001 100000 : 0000 000001 100001
177777 000000 100000 : 0000 000002 000000
177776 177777 100000 : 0000 000002 177777
177776 100001 100000 : 0000 000002 100001
177776 100000 100000 : 0000 000003 000000
177776 077777 100000 : 0000 000003 177777
177776 000001 100000 : 0000 000003 100001
177776 000000 100000 : 0000 000004 000000
177775 177777 100000 : 0000 000004 177777
177775 100001 100000 : 0000 000004 100001
177775 000000 100000 : 0000 000006 000000
140003 000000 100000 : 0000 077772 000000
140002 000000 100000 : 0000 077774 000000
140001 100000 100000 : 0000 077775 000000
140001 000000 100000 : 0000 077776 000000
140000 177777 100000 : 0000 077776 177777
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000001 100000 : 0000 077777 100001
# case dd>0, q<0
000000 100000 100000 : 1000 177777 000000
000000 100001 100000 : 1000 177777 000001
000000 177777 100000 : 1000 177777 077777
000001 000000 100000 : 1000 177776 000000
000001 000001 100000 : 1000 177776 000001
000001 077777 100000 : 1000 177776 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077777 100000 : 1000 100000 077777
# test dr=077777 boundary cases (dr = max pos value)
# case dd>0, q>0
000000 077777 077777 : 0000 000001 000000
000000 100000 077777 : 0000 000001 000001
000000 177775 077777 : 0000 000001 077776
000000 177776 077777 : 0000 000002 000000
000000 177777 077777 : 0000 000002 000001
000001 077774 077777 : 0000 000002 077776
037776 100002 077777 : 0000 077776 000000
037776 100003 077777 : 0000 077776 000001
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077777 077777 : 0000 077777 077776
# case dd<0, q<0
177777 100001 077777 : 1000 177777 000000
177777 100000 077777 : 1000 177777 177777
177777 000003 077777 : 1000 177777 100002
177777 000002 077777 : 1000 177776 000000
177777 000001 077777 : 1000 177776 177777
177776 100004 077777 : 1000 177776 100002
140000 177777 077777 : 1000 100001 000000
140000 177776 077777 : 1000 100001 177777
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000002 077777 : 1000 100000 100002
# test dd max cases
# case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591
037777 177777 100000 : 1000 100001 077777
040000 000000 100000 : 1000 100000 000000
040000 000001 100000 : 1000 100000 000001
040000 077776 100000 : 1000 100000 077776
040000 077777 100000 : 1000 100000 077777
037777 100000 100000 : 1000 100001 000000
037777 100001 100000 : 1000 100001 000001
# case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055
037777 000000 077777 : 0000 077776 077776
037777 000001 077777 : 0000 077777 000000
037777 000002 077777 : 0000 077777 000001
037777 077776 077777 : 0000 077777 077775
037777 077777 077777 : 0000 077777 077776
037777 100000 077777 : 0010 037777 100000
037776 100001 077777 : 0000 077775 077776
# case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822
140000 100001 077777 : 1000 100001 100002
140000 100000 077777 : 1000 100000 000000
140000 077777 077777 : 1000 100000 177777
140000 000003 077777 : 1000 100000 100003
140000 000002 077777 : 1000 100000 100002
140000 000001 077777 : 0010 140000 000001
140000 000000 077777 : 0010 140000 000000
# case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823
140000 100001 100000 : 0000 077776 100001
140000 100000 100000 : 0000 077777 000000
140000 077777 100000 : 0000 077777 177777
140000 000002 100000 : 0000 077777 100002
140000 000001 100000 : 0000 077777 100001
140000 000000 100000 : 0010 140000 000000
137777 177777 100000 : 0010 137777 177777
# test late div quit cases in 2 quadrant algorithm
177777 100001 177777 : 0000 077777 000000
177777 100000 177777 : 0010 177777 100000
177777 077777 177777 : 0010 177777 077777
177777 000002 177776 : 0000 077777 000000
177777 000001 177776 : 0000 077777 177777
177777 000000 177776 : 0010 177777 000000
177776 177777 177776 : 0010 177776 177777
# test big divident overflow cases
077777 177777 000001 : 0010 077777 177777
077777 177777 000002 : 0010 077777 177777
077777 177777 177777 : 0010 077777 177777
077777 177777 177776 : 0010 077777 177777
100000 000000 000001 : 0010 100000 000000
100000 000000 000002 : 0010 100000 000000
100000 000000 177777 : 0010 100000 000000
100000 000000 177776 : 0010 100000 000000

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## divtst: data collection
`divstst` has been run on real PDP-11 CPUs as well as on simulated CPUs
with the [SimH](http://simh.trailing-edge.com/) and the
[e11](http://www.dbit.com/) simulator.
The results are available in
| Case | sim | CPU | Comment |
| --------- | --- | --- | ------- |
| [2014-08-22_1170_btq](2014-08-22_1170_btq.log) | real | 11/70 | from Johnny Billquist, node magica |
| [2014-08-22_1193_btq](2014-08-22_1170_btq.log) | real | 11/93 (J11) | from Johnny Billquist, node pontus |
| [2014-08-22_e11_1174_btq](2014-08-22_e11_1174_btq.log) | e11 | 11/74 | from Johnny Billquist, node mim |
| [2014-08-22_simh_1194_btq](2014-08-22_simh_1194_btq.log) | SimH | 11/94 (J11) | from Johnny Billquist, node jocke |
The file name encodes the approximate date of data taking (relevant for
simulators which indeed change over time), the sim/CPU case, and the source
of data.
### Some findings
The N and Z condition codes and the registers are _unspecified_ after an
overflow abort of the `DIV` instruction. The only thing guaranteed is
that V=1 and C=0. The seen responses for the _unspecified_ parts
are indeed different, a good example is
```
ddh ddl dr : nzvc q r remarks
177777 100000 177777 : 0110 000000 100000 real 11/70: Z=1, R0MOD
177777 100000 177777 : 0010 177777 100000 real 11/93: r0,r1 unchanged
177777 100000 177777 : 0010 100000 000000 e11 11/74: R0MOD R1MOD
```

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## divtst: RSX version
Copy all files from this directory and the files `testall.dat` and `veri.dat`
from the parent directorty to the target system. To build the task simply use
```
@divtstbld
```
and to execute it use
```
run divtst
@divtst
```
which is equivalent to
```
>run divtst
div>/o=tstall
div>@tstall.dat
div>^Z
```
The `DIV` test results are in file `tstall.log`.

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; $Id: divtst.cmd 1266 2022-07-30 17:33:07Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
/o=tstall.log
@tstall.dat

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; $Id: divtst.mac 1266 2022-07-30 17:33:07Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Test DIV instruction
;
; Revision History:
; Date Rev Version Comment
; 2014-07-26 572 1.0.1 /v now echos command lines on ti:
; 2014-07-25 571 1.0 Initial version
;
.enabl lc
.mcall fsrsz$,finit$
.mcall gcmlb$, gcmld$, gcml$
.mcall fdbdf$,fdat$a,fdop$a,nmblk$
.mcall open$w,close$,put$
.mcall qiow$s, exit$s
fsrsz$ 2 ; 2 open files (cmd and output)
.psect data,d,rw
fdbout: fdbdf$
fdat$a r.var,fd.cr
fdop$a 2.,ofdspt,ofdnam,fo.wrt
ofdspt: .word 0,0
.word 0,0
.word 0,ofname
ofname: .blkb 20.
ofdnam: nmblk$ divtst,log
; setup with maxd=3.,prmpt=div,lun=1.,size=134.
gclblk: gcmlb$ 3.,div,gclbuf,1.,,132.
gclbuf: .blkb 134. ; +2 byte to allow zero termination
vflag: .byte 0 ; set if /v seen
oflag: .byte 0 ; set if /o seen (file open)
obuf: .blkb 132. ; result line buffer
idat: .blkw 3. ; test input: ddh,ddl,dr
edat: .blkw 2. ; expected: q,r
eccn: .byte ; expected cc's
eccz: .byte
eccv: .byte
eccc: .byte
odat: .blkw 3. ; test output: psw,q,r
occn: .byte ; output cc's
occz: .byte
occv: .byte
occc: .byte
.psect
; --------------------------------------------------------------------
; main program
main: finit$
bisb #ge.lc,gclblk+g.mode
10$: gcml$ #gclblk
tstb gclblk+g.err
bne 20$ ; read failed
mov gclblk+g.cmld+2,r0
mov gclblk+g.cmld,r1
beq 10$ ; ignore empty lines
mov r0,r2
add r1,r2
clrb (r2) ; add zero termination
call docmd
br 10$
20$: cmpb gclblk+g.err,#ge.eof ; eof ?
beq 90$ ; yes: exit
mov #mgcl,r0
mov #lmgcl,r1
call pcons
90$: ; all done
tstb oflag ; ofile open ?
beq 91$
close$ #fdbout
91$: exit$s
.psect text,d,rw
mgcl: .ascii /get command line error/
lmgcl=.-mgcl
.psect
; --------------------------------------------------------------------
; docmd: handle one input line (look for switches)
; r0 buf (in) ptr to command string (is zero terminated)
; r1 len (in) length of string
docmd: cmpb (r0),#'# ; # comment ?
bne 1$
call pline ; print
return ; and go for next
1$: tstb vflag ; /v ?
beq 10$
call pcons ; if /v, trace input on console
10$: cmpb (r0),#'/ ; switch ?
bne 30$
cmpb 1(r0),#'v ; /v switch ?
bne 20$
movb #1,vflag ; /v seen
return
20$: cmpb 1(r0),#'o ; /o switch ?
bne 90$
cmpb 2(r0),#'= ; = seen ?
bne 90$
tstb oflag ; already open ?
beq 21$
close$ #fdbout
21$: movb #1,oflag ; /o=name seen
; filename must be uppercase
; --> so convert it !!
mov r2,-(sp)
mov r3,-(sp)
mov r4,-(sp)
mov r5,-(sp)
mov #ofname,r2 ; ptr to filename string of ofdspt
mov #20.,r3 ; max 20 chars
mov r0,r4
add #3,r4 ; ptr after /o=
22$: movb (r4)+,r5 ; get char
beq 25$ ; end of string ?
cmpb r5,#'a ; between a and z
blt 24$
cmpb r5,#'z
bgt 24$
23$: sub #40,r5 ; yes: convert to uppercase
24$: movb r5,(r2)+ ; store
sob r3,22$
25$: sub #ofname,r2 ; calculate size
mov r2,ofdspt+10 ; and store in descriptor
mov (sp)+,r5
mov (sp)+,r4
mov (sp)+,r3
mov (sp)+,r2
open$w #fdbout ; open file
bcs 92$
return
30$: call doidat ; get input data
bcs 91$ ; quit on error
mov #idat,r0
mov #odat,r1
call dotst ; execute div test
call dooccx ; splitt psw -> occx flags
mov #obuf,r0
call doodat ; write result line
call doochk ; do checks, write check remarks
sub #obuf,r0
mov r0,r1 ; r1 output length
mov #obuf,r0
call pline ; write result line (to cons or file)
return
90$: mov #mswi,r0
mov #lmswi,r1
call pcons
return
91$: mov #mconv,r0
mov #lmconv,r1
call pcons
return
92$: mov #mopen,r0
mov #lmopen,r1
call pcons
clrb oflag
return
.psect text,d,rw
mswi: .ascii |bad switch, only /o or /o=name allowed|
lmswi=.-mswi
mconv: .ascii /bad test line, likely conversion error/
lmconv=.-mconv
mopen: .ascii /open failed/
lmopen=.-mopen
.psect
; --------------------------------------------------------------------
; doidat: parse test command, get all values to idat and eccx
; r0 ibuf (in) ptr to command string (is zero terminated)
doidat: mov r4,-(sp)
mov r5,-(sp)
mov #idat,r5 ; fill idat array
mov #3,r4 ; go for 3 values
1$: call getoct
bcs 99$
mov r1,(r5)+
sob r4,1$
call getsep ; check and eat separator
bcs 99$
mov #eccn,r5 ; fill eccx flags
mov #4,r4 ; go for 4 values
2$: call getbit
bcs 99$
movb r1,(r5)+
sob r4,2$
call getoct ; finally get 2 edat values
bcs 99$
mov r1,edat
call getoct
bcs 99$
mov r1,edat+2
99$: mov (sp)+,r5
mov (sp)+,r4
return
; --------------------------------------------------------------------
; dooccx: splitt returned psw to condition code bits
dooccx: mov r2,-(sp)
mov r4,-(sp)
mov r5,-(sp)
mov odat,r1
mov #occn+4,r5 ; fill eccx flags (in C to N order)
mov #4,r4 ; go for 4 bits
1$: clr r2
ror r1 ; extract lsb
rol r2 ; get to reg again
movb r2,-(r5) ; and store (in C to N order)
sob r4,1$
mov (sp)+,r5
mov (sp)+,r4
mov (sp)+,r2
return
; --------------------------------------------------------------------
; doodat: write result line
; r0 obuf (i/o) ptr to output buffer (advanced)
doodat: mov r4,-(sp)
mov r5,-(sp)
mov #idat,r5 ; write idat array
mov #3,r4 ; with 3 values
1$: mov (r5)+,r1
call putoct
movb #' ,(r0)+
sob r4,1$
movb #':,(r0)+ ; write separator
movb #' ,(r0)+
mov #occn,r5 ; write occ flags
mov #4,r4 ; with 4 values
2$: movb (r5)+,r1
call putbit
sob r4,2$
movb #' ,(r0)+
mov #odat+2,r5 ; write odat q and r
mov #2,r4 ; with 2 values
3$: mov (r5)+,r1
call putoct
movb #' ,(r0)+
sob r4,3$
dec r0 ; undo last blank
mov (sp)+,r5
mov (sp)+,r4
return
; --------------------------------------------------------------------
; doochk: do checks, add remarks to result line
; r0 obuf (i/o) ptr to output buffer (advanced)
doochk: mov r4,-(sp)
mov r5,-(sp)
cmpb occv,eccv
beq 1$
mov #mvbad,r1
call puttxt
1$: cmpb occc,eccc
beq 2$
mov #mcbad,r1
call puttxt
2$: tstb occv
beq 20$
cmp odat+2,idat ; r0 modified ? q != ddh
beq 11$
mov #mr0mod,r1
call puttxt
11$: cmp odat+4,idat+2 ; r1 modified ? r != ddl
beq 30$
mov #mr1mod,r1
call puttxt
br 30$
20$: cmpb occn,eccn
beq 21$
mov #mnbad,r1
call puttxt
21$: cmpb occz,eccz
beq 22$
mov #mzbad,r1
call puttxt
22$: cmp odat+2,edat ; q ok ?
beq 23$
mov #mqbad,r1
call puttxt
23$: cmp odat+4,edat+2 ; r ok ?
beq 30$
mov #mrbad,r1
call puttxt
30$: mov (sp)+,r5
mov (sp)+,r4
return
.psect text,d,rw
mnbad: .asciz / NBAD/
mzbad: .asciz / ZBAD/
mvbad: .asciz / VBAD/
mcbad: .asciz / CBAD/
mqbad: .asciz / QBAD/
mrbad: .asciz / RBAD/
mr0mod: .asciz / R0MOD/
mr1mod: .asciz / R1MOD/
.psect
; --------------------------------------------------------------------
; getoct: get octal number
; r0 ibuf (i/o) ptr to ibuf (advanced to char after number)
; r1 num (out) number
; C set on error
getoct: call skipws ; skip white space
mov r2,-(sp)
clr r1
1$: movb (r0)+,r2 ; get char
beq 3$ ; zero ? end string ?
cmpb r2,#' ; blank ?
beq 3$
sub #'0,r2 ; get digit value
blt 2$ ; octal ?
cmp r2,#7 ; octal ?
bgt 2$
ash #3,r1 ; <<3
bis r2,r1
br 1$
2$: sec ; bad char seen
br 4$
3$: clc ; ok, blank or end seen
4$: mov (sp)+,r2
return
; --------------------------------------------------------------------
; getbit: get bit (single 0 or 1)
; r0 ibuf (i/o) ptr to ibuf (advanced to char after number)
; r1 num (out) number
; C set on error
getbit: call skipws
movb (r0),r1
sub #'0,r1
beq 3$
blt 2$
cmp r1,#1
ble 3$
2$: sec
br 4$
3$: inc r0
clc
4$: return
; --------------------------------------------------------------------
; getsep: look for : separator
; r0 ibuf (i/o) ptr to ibuf (advanced to char after sep)
; C set on error
getsep: call skipws
cmpb (r0),#':
bne 1$
inc r0
clc
return
1$: sec
return
; --------------------------------------------------------------------
; skipws: skip over blanks
; r0 ibuf (i/o) ptr to ibuf (advanced to char after blanks)
skipws: tstb (r0)
beq 1$
cmpb (r0),#'
bne 1$
inc r0
br skipws
1$: return
; --------------------------------------------------------------------
; putoct: put octal number
; r0 obuf (i/o) ptr to obuf (advanced)
; r1 num (in) number
putoct: mov r2,-(sp)
mov r3,-(sp)
mov #6,r3
add r3,r0
1$: mov r1,r2
bic #177770,r2
add #'0,r2
movb r2,-(r0)
clc
ror r1
clc
ror r1
clc
ror r1
sob r3,1$
add #6,r0
mov (sp)+,r3
mov (sp)+,r2
return
; --------------------------------------------------------------------
; putbit: put bit (single 0 or 1)
; r0 obuf (i/o) ptr to obuf (advanced)
; r1 num (in) number
putbit: tst r1
bne 1$
movb #'0,(r0)+
return
1$: movb #'1,(r0)+
return
; --------------------------------------------------------------------
; puttxt: put asciz text
; r0 obuf (i/o) ptr to obuf (advanced)
; r1 num (in) ptr to text (zero terminated)
puttxt: tstb (r1) ; last char ?
beq 1$
movb (r1)+,(r0)+
br puttxt
1$: return
; --------------------------------------------------------------------
; pline: print line (to file or console)
; r0 buf (in) ptr to text string
; r1 len (in) length of string
pline: tstb oflag ; /o seen ?
bne 1$
call pcons ; no: write console
return
1$: call pfile ; yes: write file
return
; --------------------------------------------------------------------
; pcons: print line to console
; r0 buf (in) ptr to text string
; r1 len (in) length of string
pcons: tst r1
bne 1$ ; is string empty ?
return ; yes: simply ignore (qio will bark)
1$: qiow$s #io.wlb,#5,#1,,#iost,,<r0,r1,#40>
bcs 10$
tstb iost
blt 10$
return
10$: mov $dsw,r2
mov iost,r3
mov iost+2,r4
mov #12345,r5
iot
.psect data,d,rw
.even
iost: .blkw 2
; --------------------------------------------------------------------
; pfile: print line to output file
; r0 buf (in) ptr to text string
; r1 len (in) length of string
pfile: mov r2,-(sp)
mov r0,r2 ; mov obuf ptr to r2
; r0 will be used as fdb ptr !!
put$ #fdbout,r2,r1
mov (sp)+,r2
return
; --------------------------------------------------------------------
.end main

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; $Id: divtstbld.cmd 1266 2022-07-30 17:33:07Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
mac divtst,divtst/-sp=divtst
mac dotst,dotst/-sp=dotst
mac getpsw,getpsw/-sp=getpsw
tkb @divtsttkb.cmd

7
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; $Id: divtsttkb.cmd 1266 2022-07-30 17:33:07Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
divtst,divtst/-sp=divtst,dotst,getpsw
/
asg=ti:1

45
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; $Id: dotst.mac 1266 2022-07-30 17:33:07Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; called like
; mov #idat,r0
; mov #odat,r1
; jsr pc,dotst
; with
; idat[0] divident high (even r)
; idat[1] divident low (odd r)
; idat[2] divisor
; and returns in odat
; odat[0] psw
; odat[1] quotient (even r)
; odat[2] reminder (odd r)
;
; Revision History:
; Date Rev Version Comment
; 2014-07-20 571 1.0 Initial version (cloned from 211bsd version)
;
.globl getpsw
.globl valpsw
dotst:: mov r2,-(sp)
mov r3,-(sp)
mov (r0), r2 ; load dd high
mov 2(r0),r3 ; load dd low
div 4(r0),r2 ; do divide
call getpsw ; obtain psw in user mode
mov valpsw, (r1) ; store psw
mov r2, 2(r1) ; store quotient
mov r3, 4(r1) ; store remainder
mov (sp)+,r3
mov (sp)+,r2
return
.end

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; $Id: getpsw.mac 1266 2022-07-30 17:33:07Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2014-07-20 570 1.0 Initial version (cloned from 211bsd version)
;
.psect data,d,rw
.even
valpsw::.word 0
.psect
getpsw::bmi cc1xxx ; branch on N=1
beq cc01xx ; branch on N=0,Z=1
bvs cc001x ; branch on N=0,Z=0,V=1
bcs cc0001 ; branch on N=0,Z=0,V=0,C=1
mov #000, valpsw ; here N=0,Z=0,V=0,C=0
return
cc0001: mov #001, valpsw ; here N=0,Z=0,V=0,C=1
return
cc001x: bcs cc0011 ; branch on N=0,Z=0,V=1,C=1
mov #002, valpsw ; here N=0,Z=0,V=1,C=0
return
cc0011: mov #003, valpsw ; here N=0,Z=0,V=1,C=1
return
cc01xx: bvs cc011x ; branch on N=0,Z=1,V=1
bcs cc0101 ; branch on N=0,Z=1,V=0,C=1
mov #004, valpsw ; here N=0,Z=1,V=0,C=0
return
cc0101: mov #005, valpsw ; here N=0,Z=1,V=0,C=1
return
cc011x: bcs cc0111 ; branch on N=0,Z=1,V=1,C=1
mov #006, valpsw ; here N=0,Z=1,V=1,C=0
return
cc0111: mov #007, valpsw ; here N=0,Z=1,V=1,C=1
return
cc1xxx: beq cc01xx ; branch on N=1,Z=1
bvs cc001x ; branch on N=1,Z=0,V=1
bcs cc1001 ; branch on N=1,Z=0,V=0,C=1
mov #010, valpsw ; here N=1,Z=0,V=0,C=0
return
cc1001: mov #011, valpsw ; here N=1,Z=0,V=0,C=1
return
cc101x: bcs cc1011 ; branch on N=1,Z=0,V=1,C=1
mov #012, valpsw ; here N=1,Z=0,V=1,C=0
return
cc1011: mov #013, valpsw ; here N=1,Z=0,V=1,C=1
return
cc11xx: bvs cc111x ; branch on N=1,Z=1,V=1
bcs cc1101 ; branch on N=1,Z=1,V=0,C=1
mov #014, valpsw ; here N=1,Z=1,V=0,C=0
return
cc1101: mov #015, valpsw ; here N=1,Z=1,V=0,C=1
return
cc111x: bcs cc1111 ; branch on N=1,Z=1,V=1,C=1
mov #016, valpsw ; here N=1,Z=1,V=1,C=0
return
cc1111: mov #017, valpsw ; here N=1,Z=1,V=1,C=1
return
.end

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tools/tests/divtst/tstall.dat Normal file
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; $Id: tstall.dat 1265 2022-07-30 14:30:48Z mueller $
;
# test_div: test div instruction
# test basics (via testd2)
# dr>0
000000 000000 000003 : 0100 000000 000000 # 0/ 3: 0, 0
000000 000001 000003 : 0100 000000 000001 # 1/ 3: 0, 1
000000 000002 000003 : 0100 000000 000002 # 2/ 3: 0, 2
000000 000003 000003 : 0000 000001 000000 # 3/ 3: 1, 0
000000 000004 000003 : 0000 000001 000001 # 4/ 3: 1, 1
177777 177777 000003 : 0100 000000 177777 # -1/ 3: 0, -1
177777 177776 000003 : 0100 000000 177776 # -2/ 3: 0, -2
177777 177775 000003 : 1000 177777 000000 # -3/ 3: -1, 0
177777 177774 000003 : 1000 177777 177777 # -4/ 3: -1, -1
# dr<0
000000 000000 177775 : 0100 000000 000000 # 0/ -3: 0, 0
000000 000001 177775 : 0100 000000 000001 # 1/ -3: 0, 1
000000 000002 177775 : 0100 000000 000002 # 2/ -3: 0, 2
000000 000003 177775 : 1000 177777 000000 # 3/ -3: -1, 0
000000 000004 177775 : 1000 177777 000001 # 4/ -3: -1, 1
177777 177777 177775 : 0100 000000 177777 # -1/ -3: 0, -1
177777 177776 177775 : 0100 000000 177776 # -2/ -3: 0, -2
177777 177775 177775 : 0000 000001 000000 # -3/ -3: 1, 0
177777 177774 177775 : 0000 000001 177777 # -4/ -3: 1, -1
# dr==0
000000 000000 000000 : 0111 000000 000000 # 0/ 0: 0, 0
000000 000001 000000 : 0111 000000 000000 # 1/ 0: 0, 0
177777 177777 000000 : 0111 000000 000000 # -1/ 0: 0, 0
# test 4 quadrant basics (via testd2)
000000 000042 000005 : 0000 000006 000004 # 34/ 5: 6, 4
000000 000042 177773 : 1000 177772 000004 # 34/ -5: -6, 4
177777 177736 000005 : 1000 177772 177774 # -34/ 5: -6, -4
177777 177736 177773 : 0000 000006 177774 # -34/ -5: 6, -4
# test 4 quadrant basics (via testdqr)
000000 000042 000005 : 0000 000006 000004 # 34/ 5: 6, 4
000000 000042 177773 : 1000 177772 000004 # 34/ -5: -6, 4
177777 177736 000005 : 1000 177772 177774 # -34/ 5: -6, -4
177777 177736 177773 : 0000 000006 177774 # -34/ -5: 6, -4
# test q=100000 boundary cases (q = max neg value)
# case dd>0, dr<0 -- factor 21846
025253 000000 125252 : 1000 100000 000000 # 715849728/-21846:-32768, 0
025253 000001 125252 : 1000 100000 000001 # 715849729/-21846:-32768, 1
025253 052524 125252 : 1000 100000 052524 # 715871572/-21846:-32768, 21844
025253 052525 125252 : 1000 100000 052525 # 715871573/-21846:-32768, 21845
025253 052526 125252 : 1010 025253 052526 # 715871574/-21846: 10923, 21846
025253 052527 125252 : 1010 025253 052527 # 715871575/-21846: 10923, 21847
# case dd<0, dr>0 -- factor 21846
152525 000000 052526 : 1000 100000 000000 # -715849728/ 21846:-32768, 0
152524 177777 052526 : 1000 100000 177777 # -715849729/ 21846:-32768, -1
152524 125254 052526 : 1000 100000 125254 # -715871572/ 21846:-32768,-21844
152524 125253 052526 : 1000 100000 125253 # -715871573/ 21846:-32768,-21845
152524 125252 052526 : 1010 152524 125252 # -715871574/ 21846:-10924,-21846
152524 125251 052526 : 1010 152524 125251 # -715871575/ 21846:-10924,-21847
# case dd>0, dr<0 -- factor 21847
025253 100000 125251 : 1000 100000 000000 # 715882496/-21847:-32768, 0
025253 100001 125251 : 1000 100000 000001 # 715882497/-21847:-32768, 1
025253 152525 125251 : 1000 100000 052525 # 715904341/-21847:-32768, 21845
025253 152526 125251 : 1000 100000 052526 # 715904342/-21847:-32768, 21846
025253 152527 125251 : 1010 025253 152527 # 715904343/-21847: 10923,-10921
025253 152530 125251 : 1010 025253 152530 # 715904344/-21847: 10923,-10920
# case dd<0, dr>0 -- factor 21847
152524 100000 052527 : 1000 100000 000000 # -715882496/ 21847:-32768, 0
152524 077777 052527 : 1000 100000 177777 # -715882497/ 21847:-32768, -1
152524 025253 052527 : 1000 100000 125253 # -715904341/ 21847:-32768,-21845
152524 025252 052527 : 1000 100000 125252 # -715904342/ 21847:-32768,-21846
152524 025251 052527 : 1010 152524 025251 # -715904343/ 21847:-10924, 10921
152524 025250 052527 : 1010 152524 025250 # -715904344/ 21847:-10924, 10920
# test q=077777 boundary cases (q = max pos value)
# case dd>0, dr>0 -- factor 21846
025252 125252 052526 : 0000 077777 000000 # 715827882/ 21846: 32767, 0
025252 125253 052526 : 0000 077777 000001 # 715827883/ 21846: 32767, 1
025252 177776 052526 : 0000 077777 052524 # 715849726/ 21846: 32767, 21844
025252 177777 052526 : 0000 077777 052525 # 715849727/ 21846: 32767, 21845
025253 000000 052526 : 0010 025253 000000 # 715849728/ 21846: 10923, 0
025253 000001 052526 : 0010 025253 000001 # 715849729/ 21846: 10923, 1
# case dd<0, dr<0 -- factor 21846
152525 052526 125252 : 0000 077777 000000 # -715827882/-21846: 32767, 0
152525 052525 125252 : 0000 077777 177777 # -715827883/-21846: 32767, -1
152525 000002 125252 : 0000 077777 125254 # -715849726/-21846: 32767,-21844
152525 000001 125252 : 0000 077777 125253 # -715849727/-21846: 32767,-21845
152525 000000 125252 : 0010 152525 000000 # -715849728/-21846:-10923, 0
152524 177777 125252 : 0010 152524 177777 # -715849729/-21846:-10924, -1
# case dd>0, dr>0 -- factor 21847
025253 025251 052527 : 0000 077777 000000 # 715860649/ 21847: 32767, 0
025253 025252 052527 : 0000 077777 000001 # 715860650/ 21847: 32767, 1
025253 077776 052527 : 0000 077777 052525 # 715882494/ 21847: 32767, 21845
025253 077777 052527 : 0000 077777 052526 # 715882495/ 21847: 32767, 21846
025253 100000 052527 : 0010 025253 100000 # 715882496/ 21847: 10923,-32768
025253 100001 052527 : 0010 025253 100001 # 715882497/ 21847: 10923,-32767
# case dd<0, dr<0 -- factor 21847
152524 152527 125251 : 0000 077777 000000 # -715860649/-21847: 32767, 0
152524 152526 125251 : 0000 077777 177777 # -715860650/-21847: 32767, -1
152524 100002 125251 : 0000 077777 125253 # -715882494/-21847: 32767,-21845
152524 100001 125251 : 0000 077777 125252 # -715882495/-21847: 32767,-21846
152524 100001 125251 : 0000 077777 125252 # -715882495/-21847: 32767,-21846
152524 100000 125251 : 0010 152524 100000 # -715882496/-21847:-10924,-32768
# test dr=100000 boundary cases (dr = max neg value)
# case dd<0, q>0
177777 100000 100000 : 0000 000001 000000 # -32768/-32768: 1, 0
177777 077777 100000 : 0000 000001 177777 # -32769/-32768: 1, -1
177777 000001 100000 : 0000 000001 100001 # -65535/-32768: 1,-32767
177777 000000 100000 : 0000 000002 000000 # -65536/-32768: 2, 0
177776 177777 100000 : 0000 000002 177777 # -65537/-32768: 2, -1
177776 100001 100000 : 0000 000002 100001 # -98303/-32768: 2,-32767
177776 100000 100000 : 0000 000003 000000 # -98304/-32768: 3, 0
177776 077777 100000 : 0000 000003 177777 # -98305/-32768: 3, -1
177776 000001 100000 : 0000 000003 100001 # -131071/-32768: 3,-32767
177776 000000 100000 : 0000 000004 000000 # -131072/-32768: 4, 0
177775 177777 100000 : 0000 000004 177777 # -131073/-32768: 4, -1
177775 100001 100000 : 0000 000004 100001 # -163839/-32768: 4,-32767
177775 000000 100000 : 0000 000006 000000 # -196608/-32768: 6, 0
140003 000000 100000 : 0000 077772 000000 # -1073545216/-32768: 32762, 0
140002 000000 100000 : 0000 077774 000000 # -1073610752/-32768: 32764, 0
140001 100000 100000 : 0000 077775 000000 # -1073643520/-32768: 32765, 0
140001 000000 100000 : 0000 077776 000000 # -1073676288/-32768: 32766, 0
140000 177777 100000 : 0000 077776 177777 # -1073676289/-32768: 32766, -1
140000 100001 100000 : 0000 077776 100001 # -1073709055/-32768: 32766,-32767
140000 100000 100000 : 0000 077777 000000 # -1073709056/-32768: 32767, 0
140000 077777 100000 : 0000 077777 177777 # -1073709057/-32768: 32767, -1
140000 000001 100000 : 0000 077777 100001 # -1073741823/-32768: 32767,-32767
# case dd>0, q<0
000000 100000 100000 : 1000 177777 000000 # 32768/-32768: -1, 0
000000 100001 100000 : 1000 177777 000001 # 32769/-32768: -1, 1
000000 177777 100000 : 1000 177777 077777 # 65535/-32768: -1, 32767
000001 000000 100000 : 1000 177776 000000 # 65536/-32768: -2, 0
000001 000001 100000 : 1000 177776 000001 # 65537/-32768: -2, 1
000001 077777 100000 : 1000 177776 077777 # 98303/-32768: -2, 32767
037777 100000 100000 : 1000 100001 000000 # 1073709056/-32768:-32767, 0
037777 100001 100000 : 1000 100001 000001 # 1073709057/-32768:-32767, 1
037777 177777 100000 : 1000 100001 077777 # 1073741823/-32768:-32767, 32767
040000 000000 100000 : 1000 100000 000000 # 1073741824/-32768:-32768, 0
040000 000001 100000 : 1000 100000 000001 # 1073741825/-32768:-32768, 1
040000 077777 100000 : 1000 100000 077777 # 1073774591/-32768:-32768, 32767
# test dr=077777 boundary cases (dr = max pos value)
# case dd>0, q>0
000000 077777 077777 : 0000 000001 000000 # 32767/ 32767: 1, 0
000000 100000 077777 : 0000 000001 000001 # 32768/ 32767: 1, 1
000000 177775 077777 : 0000 000001 077776 # 65533/ 32767: 1, 32766
000000 177776 077777 : 0000 000002 000000 # 65534/ 32767: 2, 0
000000 177777 077777 : 0000 000002 000001 # 65535/ 32767: 2, 1
000001 077774 077777 : 0000 000002 077776 # 98300/ 32767: 2, 32766
037776 100002 077777 : 0000 077776 000000 # 1073643522/ 32767: 32766, 0
037776 100003 077777 : 0000 077776 000001 # 1073643523/ 32767: 32766, 1
037777 000000 077777 : 0000 077776 077776 # 1073676288/ 32767: 32766, 32766
037777 000001 077777 : 0000 077777 000000 # 1073676289/ 32767: 32767, 0
037777 000002 077777 : 0000 077777 000001 # 1073676290/ 32767: 32767, 1
037777 077777 077777 : 0000 077777 077776 # 1073709055/ 32767: 32767, 32766
# case dd<0, q<0
177777 100001 077777 : 1000 177777 000000 # -32767/ 32767: -1, 0
177777 100000 077777 : 1000 177777 177777 # -32768/ 32767: -1, -1
177777 000003 077777 : 1000 177777 100002 # -65533/ 32767: -1,-32766
177777 000002 077777 : 1000 177776 000000 # -65534/ 32767: -2, 0
177777 000001 077777 : 1000 177776 177777 # -65535/ 32767: -2, -1
177776 100004 077777 : 1000 177776 100002 # -98300/ 32767: -2,-32766
140000 177777 077777 : 1000 100001 000000 # -1073676289/ 32767:-32767, 0
140000 177776 077777 : 1000 100001 177777 # -1073676290/ 32767:-32767, -1
140000 100001 077777 : 1000 100001 100002 # -1073709055/ 32767:-32767,-32766
140000 100000 077777 : 1000 100000 000000 # -1073709056/ 32767:-32768, 0
140000 077777 077777 : 1000 100000 177777 # -1073709057/ 32767:-32768, -1
140000 000002 077777 : 1000 100000 100002 # -1073741822/ 32767:-32768,-32766
# test dd max cases
# case dd>0 dr<0 near nmax*nmax+nmax-1 = +1073774591
037777 177777 100000 : 1000 100001 077777 # 1073741823/-32768:-32767, 32767
040000 000000 100000 : 1000 100000 000000 # 1073741824/-32768:-32768, 0
040000 000001 100000 : 1000 100000 000001 # 1073741825/-32768:-32768, 1
040000 077776 100000 : 1000 100000 077776 # 1073774590/-32768:-32768, 32766
040000 077777 100000 : 1000 100000 077777 # 1073774591/-32768:-32768, 32767
037777 100000 100000 : 1000 100001 000000 # 1073709056/-32768:-32767, 0
037777 100001 100000 : 1000 100001 000001 # 1073709057/-32768:-32767, 1
# case dd>0 dr>0 near pmax*pmax+pmax-1 = +1073709055
037777 000000 077777 : 0000 077776 077776 # 1073676288/ 32767: 32766, 32766
037777 000001 077777 : 0000 077777 000000 # 1073676289/ 32767: 32767, 0
037777 000002 077777 : 0000 077777 000001 # 1073676290/ 32767: 32767, 1
037777 077776 077777 : 0000 077777 077775 # 1073709054/ 32767: 32767, 32765
037777 077777 077777 : 0000 077777 077776 # 1073709055/ 32767: 32767, 32766
037777 100000 077777 : 0010 037777 100000 # 1073709056/ 32767: 16383,-32768
037776 100001 077777 : 0000 077775 077776 # 1073643521/ 32767: 32765, 32766
# case dd<0 dr>0 near nmax*pmax+pmax-1 = -1073741822
140000 100001 077777 : 1000 100001 100002 # -1073709055/ 32767:-32767,-32766
140000 100000 077777 : 1000 100000 000000 # -1073709056/ 32767:-32768, 0
140000 077777 077777 : 1000 100000 177777 # -1073709057/ 32767:-32768, -1
140000 000003 077777 : 1000 100000 100003 # -1073741821/ 32767:-32768,-32765
140000 000002 077777 : 1000 100000 100002 # -1073741822/ 32767:-32768,-32766
140000 000001 077777 : 1010 140000 000001 # -1073741823/ 32767:-16384, 1
140000 000000 077777 : 1010 140000 000000 # -1073741824/ 32767:-16384, 0
# case dd<0 dr<0 near pmax*nmax+nmax-1 = -1073741823
140000 100001 100000 : 0000 077776 100001 # -1073709055/-32768: 32766,-32767
140000 100000 100000 : 0000 077777 000000 # -1073709056/-32768: 32767, 0
140000 077777 100000 : 0000 077777 177777 # -1073709057/-32768: 32767, -1
140000 000002 100000 : 0000 077777 100002 # -1073741822/-32768: 32767,-32766
140000 000001 100000 : 0000 077777 100001 # -1073741823/-32768: 32767,-32767
140000 000000 100000 : 0010 140000 000000 # -1073741824/-32768:-16384, 0
137777 177777 100000 : 0010 137777 177777 # -1073741825/-32768:-16385, -1
# test late div quit cases in 2 quadrant algorithm
177777 100001 177777 : 0000 077777 000000 # -32767/ -1: 32767, 0
177777 100000 177777 : 0010 000000 000000 # -32768/ -1: 0, 0
177777 077777 177777 : 0010 000000 000000 # -32769/ -1: 0, 0
177777 000002 177776 : 0000 077777 000000 # -65534/ -2: 32767, 0
177777 000001 177776 : 0000 077777 177777 # -65535/ -2: 32767, -1
177777 000000 177776 : 0010 000000 000000 # -65536/ -2: 0, 0
177776 177777 177776 : 0010 000000 000000 # -65537/ -2: 0, 0
# test big divident overflow cases
077777 177777 000001 : 0010 000000 000000 # 2147483647/ 1: 0, 0
077777 177777 000002 : 0010 000000 000000 # 2147483647/ 2: 0, 0
077777 177777 177777 : 1010 000000 000000 # 2147483647/ -1: 0, 0
077777 177777 177776 : 1010 000000 000000 # 2147483647/ -2: 0, 0
100000 000000 000001 : 1010 000000 000000 # -2147483648/ 1: 0, 0
100000 000000 000002 : 1010 000000 000000 # -2147483648/ 2: 0, 0
100000 000000 177777 : 0010 000000 000000 # -2147483648/ -1: 0, 0
100000 000000 177776 : 0010 000000 000000 # -2147483648/ -2: 0, 0

16
tools/tests/divtst/veri.dat Normal file
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; $Id: veri.dat 1265 2022-07-30 14:30:48Z mueller $
;
# verify divtst: some intentionally wrong expects; use 34/5:6,4
#
# expect NBAD
000000 000042 000005 : 1000 000006 000004 # 34/ 5: 6, 4
# expect ZBAD
000000 000042 000005 : 0100 000006 000004 # 34/ 5: 6, 4
# expect VBAD
000000 000042 000005 : 0010 000006 000004 # 34/ 5: 6, 4
# expect CBAD
000000 000042 000005 : 0001 000006 000004 # 34/ 5: 6, 4
# expect QBAD
000000 000042 000005 : 0000 000005 000004 # 34/ 5: 6, 4
# expect RBAD
000000 000042 000005 : 0000 000006 000005 # 34/ 5: 6, 4