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rtl/sys_gen: add READMEs

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wfjm
2019-08-10 08:30:29 +02:00
parent 2837308cbe
commit 7cccce5a51
7 changed files with 71 additions and 9 deletions
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rtl/sys_gen/README.md
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This directory sub-tree contains **HDL sources for top level designs**
and is organized in
| Directory | Content |
| --------- | ------- |
| [tst_mig](tst_mig) | MIG core tester |
| [tst_rlink](tst_rlink) | rlink tester (over serial links) |
| [tst_rlink_cuff](tst_rlink_cuff) | rlink tester (over Cypress FX2 USB) |
| [tst_serloop](tst_serloop) | serial port loop back tester |
| [tst_snhumanio](tst_snhumanio) | Digilent board human IO tester |
| [tst_sram](tst_sram) | memory tester (SRAM or CRAM) |
| [w11a](w11a) | w11a systems |
| Directory | Content | s3 | n2 | n3 |atl| n4 | n4d| arty| as7| b3 | c7 |
| -------------------------------- | -------------------------------- |:--:|:--:|:--:|:-:|:--:|:--:|:---:|:--:|:--:|:--:|
| [tst_mig](tst_mig) | MIG core tester | - | - | - | - | - | y | y | - | - | - |
| [tst_rlink](tst_rlink) | rlink tester (over serial links) | y | y | y | - | y | y | y | - | y | y |
| [tst_rlink_cuff](tst_rlink_cuff) | rlink tester (over Cypress FX2) | - | y | y | y | - | - | - | - | - | - |
| [tst_serloop](tst_serloop) | serial port loop back tester | y | y | y | - | y | y | - | - | - | - |
| [tst_snhumanio](tst_snhumanio) | Digilent board human IO tester | y | y | y | y | y | y | - | - | y | - |
| [tst_sram](tst_sram) | memory tester | y | y | y | - | y | y | y | - | - | y |
| [w11a](w11a) | w11a systems | y | y | y | - | y | y | y | y | y | y |

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rtl/sys_gen/tst_mig/README.md Normal file
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This directory sub-tree contains **MIG core tester systems**
and is organized in
| Directory | Content |
| --------- | ------- |
| [arty](arty) | design for Digilent Arty A7-35 |
| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ |

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rtl/sys_gen/tst_rlink/README.md Normal file
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This directory sub-tree contains **rlink over serial link tester systems**
and is organized in
| Directory | Content |
| --------- | ------- |
| [arty](arty) | design for Digilent Arty A7-35 |
| [basys3](basys3) | design for Digilent Basys3 |
| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) |
| [nexys2](nexys2) | design for Digilent Nexys2 |
| [nexys3](nexys3) | design for Digilent Nexys3 |
| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) |
| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ |
| [s3board](s3board) | design for Digilent S3BOARD |

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rtl/sys_gen/tst_rlink_cuff/README.md Normal file
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This directory sub-tree contains **rlink over Cypress FX2 tester systems**
and is organized in
| Directory | Content |
| --------- | ------- |
| [atlys](atlys) | design for Digilent Atlys |
| [nexys2](nexys2) | design for Digilent Nexys2 |
| [nexys3](nexys3) | design for Digilent Nexys3 |

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rtl/sys_gen/tst_serloop/README.md Normal file
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This directory sub-tree contains **serial port loop back tester systems**
and is organized in
| Directory | Content |
| --------- | ------- |
| [nexys2](nexys2) | design for Digilent Nexys2 |
| [nexys3](nexys3) | design for Digilent Nexys3 |
| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) |
| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ |
| [s3board](s3board) | design for Digilent S3BOARD |

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rtl/sys_gen/tst_snhumanio/README.md Normal file
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This directory sub-tree contains **Digilent board human IO tester systems**
and is organized in
| Directory | Content |
| --------- | ------- |
| [atlys](atlys) | design for Digilent Atlys |
| [basys3](basys3) | design for Digilent Basys3 |
| [nexys2](nexys2) | design for Digilent Nexys2 |
| [nexys3](nexys3) | design for Digilent Nexys3 |
| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) |
| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ |
| [s3board](s3board) | design for Digilent S3BOARD |

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rtl/sys_gen/tst_sram/README.md Normal file
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This directory sub-tree contains **memory tester systems**
and is organized in
| Directory | Content |
| --------- | ------- |
| [arty](arty) | design for Digilent Arty A7-35 |
| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) |
| [nexys2](nexys2) | design for Digilent Nexys2 |
| [nexys3](nexys3) | design for Digilent Nexys3 |
| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) |
| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR _!! only sim-tested !!_ |
| [s3board](s3board) | design for Digilent S3BOARD |