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add tbench test_w11a_cpu_halt; minor changes; cosmetics

Browse Source 
- tools/src/
  - librwxxtpp/RtclRw11Cpu.cpp: fix rust code name
- tools/tbench
  - cp/test_cp_cpubasics.tcl: use symbolic names via regbld
  - w11a/test_w11a_cdma.tcl: fix attention harvest
  - w11a/test_w11a_cpu_halt.tcl: added, verifies fatal CPU halts
  - w11a/test_w11a_inst_wait.tcl: check cpu status
  - w11a/w11a_all.dat: add test_w11a_cpu_halt.tc
- tools/tcode
  - cpu_basics.mac: extend test A4.5
This commit is contained in:
wfjm
2023-01-07 13:51:33 +01:00
parent ba4aa45c48
commit 7f2d7f97d0
8 changed files with 311 additions and 112 deletions
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6
tools/src/librwxxtpp/RtclRw11Cpu.cpp
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@@ -1,10 +1,10 @@
// $Id: RtclRw11Cpu.cpp 1346 2023-01-06 12:56:08Z mueller $
// $Id: RtclRw11Cpu.cpp 1347 2023-01-07 12:48:58Z mueller $
// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// Revision History:
// Date Rev Version Comment
// 2023-01-05 1346 1.2.37 use kCPUUBMAP
// 2023-01-06 1347 1.2.37 use kCPUUBMAP, fix rust code name
// 2022-09-03 1292 1.2.36 M_show: fix mmr1 display, better mmr0 display
// 2022-08-11 1276 1.2.35 ssr->mmr rename
// 2022-07-07 1249 1.2.34 BUGFIX: quit before mem write if asm-11 error seen
@@ -1299,7 +1299,7 @@ int RtclRw11Cpu::M_show(RtclArgs& args)
const char* mode[4] = {"k","s","?","u"};
const char* rust[16] = {"init", "HALTed", "reset", "stopped",
"stepped", "suspend", "hbpt", "..run..",
"F:vecfet", "F:redstk", "1010", "1011",
"F:vecfet", "F:recser", "1010", "1011",
"F:seq", "F:vmbox" , "1101", "1111"};
while (args.NextOpt(opt, optset)) {

53
tools/tbench/cp/test_cp_cpubasics.tcl
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@@ -1,10 +1,10 @@
# $Id: test_cp_cpubasics.tcl 1346 2023-01-06 12:56:08Z mueller $
# $Id: test_cp_cpubasics.tcl 1347 2023-01-07 12:48:58Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-05 1346 1.1.2 add creset test
# 2023-01-06 1347 1.1.2 add creset test
# 2015-07-19 702 1.1.1 ignore attn in stat checks
# 2015-05-09 676 1.1 w11a start/stop/suspend overhaul
# 2013-03-31 502 1.0 Initial version
@@ -14,6 +14,7 @@
# 2. execute code via -start, -stapc
# 3. single step code via -step
# 4. verify -suspend, -resume
# 5. verify -creset
#
# ----------------------------------------------------------------------------
@@ -25,9 +26,9 @@ rlc log " load simple linear code via lsasm"
$cpu ldasm -lst lst -sym sym {
. = 1000
start: inc r2
inc r2
inc r2
halt
100$: inc r2
200$: inc r2
300$: halt
stop:
}
@@ -54,21 +55,21 @@ rlc log " execute via -step"
$cpu cp -wr2 00300 \
-wpc $sym(start)
$cpu cp -step \
-rpc -edata [expr {$sym(start)+002}] \
-rpc -edata $sym(start:100$) \
-rr2 -edata 00301 \
-rstat -edata 000100
-rstat -edata [regbld rw11::CP_STAT {rust step}]
$cpu cp -step \
-rpc -edata [expr {$sym(start)+004}] \
-rpc -edata $sym(start:200$) \
-rr2 -edata 00302 \
-rstat -edata 000100
-rstat -edata [regbld rw11::CP_STAT {rust step}]
$cpu cp -step \
-rpc -edata [expr {$sym(start)+006}] \
-rpc -edata $sym(start:300$) \
-rr2 -edata 00303 \
-rstat -edata 000100
-rstat -edata [regbld rw11::CP_STAT {rust step}]
$cpu cp -step \
-rpc -edata [expr {$sym(start)+010}] \
-rpc -edata $sym(stop) \
-rr2 -edata 00303 \
-rstat -edata 000020
-rstat -edata [regbld rw11::CP_STAT {rust halt}]
rlc log " A2: suspend/resume basics; cpugo,cpususp flags ------------"
# define tmpproc for r2 increment checks
@@ -135,24 +136,28 @@ rlc log " creset, check cpususp=0"
$cpu cp -creset \
-rr2 -estat 0
rlc log " A3: check that creset clears PSW,MMR0, MMR3 ---------------"
rlc log " A3: check that creset clears PSW,STKLIM,MMR0,MMR3 ---------"
set mmr0 [$cpu imap mmr0]
set mmr3 [$cpu imap mmr3]
set stklim [$cpu imap stklim]
set mmr0 [$cpu imap mmr0]
set mmr3 [$cpu imap mmr3]
set psw_val [regbld rw11::PSW rset {pri 7}]
set mmr0_val [regbld rw11::MMR0 anr ale ard trp ent ena]
set mmr3_val [regbld rw11::MMR3 ena_ubm ena_22bit d_km d_sm d_um]
rlc log " write ps,mmr0,mmr3 and read back"
rlc log " write ps,stklim,mmr0,mmr3 and read back"
$cpu cp -wps $psw_val \
-wibr $mmr0 $mmr0_val \
-wibr $mmr3 $mmr3_val \
-wibr $stklim 0400 \
-wibr $mmr0 $mmr0_val \
-wibr $mmr3 $mmr3_val \
-rps -edata $psw_val \
-ribr $mmr0 -edata $mmr0_val \
-ribr $mmr3 -edata $mmr3_val
-ribr $stklim -edata 0400 \
-ribr $mmr0 -edata $mmr0_val \
-ribr $mmr3 -edata $mmr3_val
rlc log " creset and check that ps,mmr0,mmr3 cleared"
rlc log " creset and check that ps,stklim,mmr0,mmr3 cleared"
$cpu cp -creset \
-rps -edata 0 \
-ribr $mmr0 -edata 0 \
-ribr $mmr3 -edata 0
-ribr $stklim -edata 0 \
-ribr $mmr0 -edata 0 \
-ribr $mmr3 -edata 0

9
tools/tbench/w11a/test_w11a_cdma.tcl
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@@ -1,10 +1,10 @@
# $Id: test_w11a_cdma.tcl 1346 2023-01-06 12:56:08Z mueller $
# $Id: test_w11a_cdma.tcl 1347 2023-01-07 12:48:58Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2023- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-06 1346 1.0 Initial version
# 2023-01-07 1347 1.0 Initial version
#
# Test bwm/brm while CPU active
#
@@ -83,6 +83,7 @@ rw11::asmtreg $cpu pc $sym(start:100$)
$cpu cp -wal $sym(buf) \
-brm [llength $buf] -edata $buf
rw11::asmtreg $cpu pc $sym(start:100$)
# stop code
$cpu cp -stop
# stop code and harvest attention
$cpu cp -stop \
-attn

168
tools/tbench/w11a/test_w11a_cpu_halt.tcl Normal file
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@@ -0,0 +1,168 @@
# $Id: test_w11a_cpu_halt.tcl 1347 2023-01-07 12:48:58Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2023- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-06 1347 1.0 Initial version
#
# Test CPU fatal halt conditions:
# vecfet: vector fetch error halt
# recser: recursive stack error halt
# The other two, sfail and vfail, are internal bug checks, no known way
# to check them, and if there were, the CPU core would be fixed.
#
# Both vecfet and recset can only happen with MMU enabled.
# ----------------------------------------------------------------------------
rlc log "test_w11a_cpu_halt: test CPU fatal halt conditions ------------------"
$cpu ldasm -lst lst -sym sym {
.include |lib/defs_cpu.mac|
.include |lib/defs_mmu.mac|
.include |lib/vec_cpucatch.mac|
;
kipdr0 = kipdr+ 0
kipar0 = kipar+ 0
kipdr1 = kipdr+ 2
kipar1 = kipar+ 2
kipdr6 = kipdr+14
kipar6 = kipar+14
kipdr7 = kipdr+16
kipar7 = kipar+16
p1base = <1*20000> ; page 1
p6base = <6*20000> ; page 6
;
. = 1000
stack1:
;
; code 1: initial set up of MMU, execute EMT ---------------
start1: mov #stack1,sp
; set up MMU: 1-to-1 mapping for kernel
mov #<127.*md.plf>!md.arw,r5
mov r5,kipdr0 ; rw
mov r5,kipdr1 ; rw
clr kipdr6 ; non-resident
mov r5,kipdr7 ; rw
mov #000000,kipar0
mov #000200,kipar1
mov #001400,kipar6
mov #177600,kipar7
; set up EMT handler
mov #vh.emt,v..emt
; enable MMU and execute EMT
mov #m0.ena,mmr0
inc r0 ; bump trace count
emt 100
inc r0 ; bump trace count
halt
stop1:
;
vh.emt: inc r0 ; bump trace count
rti
;
; code 2: vector fetch failure after EMT -------------------
. = p1base
.blkw 32.
stack2:
start2: mov #stack2,sp
; unmap page 0, any vector fetch must fail, test with EMT
clr kipdr0
; enable MMU and execute EMT
mov #m0.ena,mmr0
inc r0 ; bump trace count
emt 100 ; -> vecfet CPU halt
100$: inc r0 ; bump trace count
halt
stop2:
;
; code 3: recursive stack error after EMT ------------------
start3: mov #stack1,sp ; stack in page 0
; map page 0 read-only, so fetch succeeds, but push fails
mov #<127.*md.plf>!md.ara,kipdr0
; enable MMU and execute EMT
mov #m0.ena,mmr0
inc r0 ; bump trace count
emt 100 ; -> recser CPU halt
100$: inc r0 ; bump trace count
halt
stop3:
;
; code 4: recursive stack error after STKLIM abort ---------
.blkw 32.
stack4:
start4: mov #stack4,sp ; stack in page 1
; map page 0 still read-only; set STKLIM to prevent stack pusk
mov #stack4,cp.slr
; enable MMU and execute stack push
mov #m0.ena,mmr0
inc r0 ; bump trace count
clr -(sp) ; -> recser CPU halt
100$: inc r0 ; bump trace count
halt
stop4:
;
; code 5: recursive stack error after MMU abort ---------
start5: mov #p6base,sp ; stack in page 6
; map page 0 still read-only; page 6 is unmapped
mov #stack4,cp.slr
; enable MMU and execute stack push
mov #m0.ena,mmr0
inc r0 ; bump trace count
clr -(sp) ; -> recser CPU halt
100$: inc r0 ; bump trace count
halt
stop5:
}
# --------------------------------------------------------------------
rlc log " A1: initial set up of MMU, execute EMT --------------------"
# that test is warmup, shows that MMU setup works
$cpu cp -wr0 0 \
-stapc $sym(start1)
rw11::asmwait $cpu sym
$cpu cp -rr0 -edata 3 \
-rpc -edata $sym(stop1) \
-rstat -edata [regbld rw11::CP_STAT {rust halt}]
# --------------------------------------------------------------------
rlc log " A2: vecfet halt after unmap page 0 and EMT ----------------"
$cpu cp -wr0 0 \
-stapc $sym(start2)
rw11::asmwait $cpu sym
$cpu cp -rr0 -edata 1 \
-rpc -edata $sym(start2:100$) \
-rstat -edata [regbld rw11::CP_STAT {rust vecfet}]
# --------------------------------------------------------------------
rlc log " A3: recser halt cases -------------------------------------"
rlc log " A3.1: after page 0 read-only and EMT ----------"
$cpu cp -wr0 0 \
-stapc $sym(start3)
rw11::asmwait $cpu sym
$cpu cp -rr0 -edata 1 \
-rpc -edata $sym(start3:100$) \
-rstat -edata [regbld rw11::CP_STAT {rust recser}]
# --------------------------------------------------------------------
rlc log " A3.2: after STKLIM abort ----------------------"
$cpu cp -wr0 0 \
-stapc $sym(start4)
rw11::asmwait $cpu sym
$cpu cp -rr0 -edata 1 \
-rpc -edata $sym(start4:100$) \
-rstat -edata [regbld rw11::CP_STAT {rust recser}]
# --------------------------------------------------------------------
rlc log " A3.3: after MMU abort -------------------------"
$cpu cp -wr0 0 \
-stapc $sym(start5)
rw11::asmwait $cpu sym
$cpu cp -rr0 -edata 1 \
-rpc -edata $sym(start5:100$) \
-rstat -edata [regbld rw11::CP_STAT {rust recser}]

49
tools/tbench/w11a/test_w11a_inst_wait.tcl
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@@ -1,10 +1,10 @@
# $Id: test_w11a_inst_wait.tcl 1346 2023-01-06 12:56:08Z mueller $
# $Id: test_w11a_inst_wait.tcl 1347 2023-01-07 12:48:58Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2023- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-06 1346 1.0 Initial version
# 2023-01-06 1347 1.0 Initial version
#
# Test WAIT instruction. Can't be done in tcode because the test requires
# console interaction for monitoring the CPU state.
@@ -39,24 +39,27 @@ rlc log " A1: test that wait does wait-------------------------------"
rw11::asmrun $cpu sym r0 0
# check that wait does wait
rw11::asmtreg $cpu r0 1 \
sp $sym(stack) \
pc $sym(start:200$)
rw11::asmtreg $cpu r0 1 \
sp $sym(stack) \
pc $sym(start:200$)
rw11::asmtreg $cpu r0 1 \
sp $sym(stack) \
pc $sym(start:200$)
$cpu cp -rr0 -edata 1 \
-rsp -edata $sym(stack) \
-rpc -edata $sym(start:200$) \
-rstat -edata [regbld rw11::CP_STAT {rust runs} go]
$cpu cp -rr0 -edata 1 \
-rsp -edata $sym(stack) \
-rpc -edata $sym(start:200$) \
-rstat -edata [regbld rw11::CP_STAT {rust runs} go]
$cpu cp -rr0 -edata 1 \
-rsp -edata $sym(stack) \
-rpc -edata $sym(start:200$) \
-rstat -edata [regbld rw11::CP_STAT {rust runs} go]
# trigger PIRQ interrupt with console write to cp.pir
$cpu cp -wibr [$cpu imap pirq] [regbld rw11::PIRQ {pir 2}]
# check that interrupt was handled and cpu halted
rw11::asmwait $cpu sym; # checks pc
rw11::asmtreg $cpu r0 2 \
sp $sym(stack)
$cpu cp -rr0 -edata 2 \
-rsp -edata $sym(stack) \
-rstat -edata [regbld rw11::CP_STAT {rust halt}]
rlc log " A2: test that doesn't block when single stepped -----------"
@@ -64,17 +67,17 @@ $cpu cp -wr0 0 \
-wpc $sym(start)
# step over 1st inc
$cpu cp -step \
-rr0 -edata 1 \
-rpc -edata $sym(start:100$) \
-rstat -edata 000100
-rr0 -edata 1 \
-rpc -edata $sym(start:100$) \
-rstat -edata [regbld rw11::CP_STAT {rust step}]
# step over wait
$cpu cp -step \
-rr0 -edata 1 \
-rpc -edata $sym(start:200$) \
-rstat -edata 000100
-rr0 -edata 1 \
-rpc -edata $sym(start:200$) \
-rstat -edata [regbld rw11::CP_STAT {rust step}]
# step over 2nd inc
$cpu cp -step \
-rr0 -edata 2 \
-rpc -edata $sym(start:300$) \
-rstat -edata 000100
-rr0 -edata 2 \
-rpc -edata $sym(start:300$) \
-rstat -edata [regbld rw11::CP_STAT {rust step}]
$cpu cp -stop

3
tools/tbench/w11a/w11a_all.dat
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@@ -1,4 +1,4 @@
# $Id: w11a_all.dat 1346 2023-01-06 12:56:08Z mueller $
# $Id: w11a_all.dat 1347 2023-01-07 12:48:58Z mueller $
#
## steering file for all w11a tests
#
@@ -15,4 +15,5 @@ test_w11a_inst_quick.tcl
test_w11a_inst_traps.tcl
test_w11a_inst_wait.tcl
test_w11a_cdma.tcl
test_w11a_cpu_halt.tcl
#

31
tools/tcode/cpu_basics.mac
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@@ -1,10 +1,10 @@
; $Id: cpu_basics.mac 1345 2023-01-04 18:05:42Z mueller $
; $Id: cpu_basics.mac 1347 2023-01-07 12:48:58Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2015-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2023-01-04 1345 1.0 Initial version
; 2023-01-07 1347 1.0 Initial version
; 2015-08-30 710 0.1 First draft
;
; Test CPU basics: most instructions except traps, EIS and FPP
@@ -31,7 +31,7 @@
; A4.2 jsr + cc
; A4.3 jsr r0-r5
; A4.4 jsr sp and rts sp
; A4.5 jsr r1,(r1)+
; A4.5 jsr r1,(r1)+ and jsr r2,@(r2)+
; A5 mark
;
; Test A1: ccop + bxx +++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -1001,7 +1001,7 @@ ta0404: hcmpeq sp,#stack ; check stack is default
;
9999$: iot ; end of test A4.4
;
; Test A4.5 -- jsr r1,(r1)+ ++++++++++++++++++++++++++++++++++++++++++
; Test A4.5 -- jsr r1,(r1)+ and jsr r2,@(r2)+ ++++++++++++++++++++++++
; Using the same register in the destination specifier and as linkage
; register is possible and works as usual.
;
@@ -1010,13 +1010,34 @@ ta0405: mov #200$,r1
100$: .word 000301 ; 1st arg
.word 000302 ; 2nd arg
hcmpeq #200$+2,r1 ; check that incremented r1 restored
br 9999$
br 1000$
;
200$: hcmpeq #100$,r1 ; check r1 holds address after jsr
hcmpeq #301,(r1)+ ; process 1st arg
hcmpeq #302,(r1)+ ; process 1st arg
rts r1
;
; Even using the 'linkage register' as list pointer in the caller and as
; argument pointer in the callee works as expected.
;
1000$: mov #1100$,r2 ; r2 prt to list of subroutines
jsr r2,@(r2)+ ; call 1st in list
.word 000401
jsr r2,@(r2)+ ; call 2nd in list
.word 000501
.word 000502
br 9999$
;
1100$: .word 1200$
.word 1300$
;
1200$: hcmpeq #401,(r2)+ ; process 1st arg
rts r2
;
1300$: hcmpeq #501,(r2)+ ; process 1st arg
hcmpeq #502,(r2)+ ; process 2nd arg
rts r2
9999$: iot ; end of test A4.5
;
; Test A5 -- mark ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

104
tools/tcode/cpu_mmu.mac
View File

@@ -1,4 +1,4 @@
; $Id: cpu_mmu.mac 1346 2023-01-06 12:56:08Z mueller $
; $Id: cpu_mmu.mac 1347 2023-01-07 12:48:58Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
@@ -28,60 +28,60 @@
.include |lib/tcode_std_base.mac|
.include |lib/defs_mmu.mac|
; some useful definitions
uipdr0 = uipdr+ 0
uipar0 = uipar+ 0
udpdr0 = udpdr+ 0
udpar0 = udpar+ 0
udpdr1 = udpdr+ 2
udpar1 = udpar+ 2
udpdr2 = udpdr+ 4
udpar2 = udpar+ 4
uipdr0 = uipdr+ 0
uipar0 = uipar+ 0
udpdr0 = udpdr+ 0
udpar0 = udpar+ 0
udpdr1 = udpdr+ 2
udpar1 = udpar+ 2
udpdr2 = udpdr+ 4
udpar2 = udpar+ 4
sipdr0 = sipdr+ 0
sipar0 = sipar+ 0
sipdr1 = sipdr+ 2
sipar1 = sipar+ 2
sipdr2 = sipdr+ 4
sipar2 = sipar+ 4
sipdr3 = sipdr+ 6
sipar3 = sipar+ 6
sipdr6 = sipdr+14
sipar6 = sipar+14
sipdr7 = sipdr+16
sipar7 = sipar+16
sipdr0 = sipdr+ 0
sipar0 = sipar+ 0
sipdr1 = sipdr+ 2
sipar1 = sipar+ 2
sipdr2 = sipdr+ 4
sipar2 = sipar+ 4
sipdr3 = sipdr+ 6
sipar3 = sipar+ 6
sipdr6 = sipdr+14
sipar6 = sipar+14
sipdr7 = sipdr+16
sipar7 = sipar+16
kipdr0 = kipdr+ 0
kipar0 = kipar+ 0
kdpdr0 = kdpdr+ 0
kdpar0 = kdpar+ 0
kipdr1 = kipdr+ 2
kipar1 = kipar+ 2
kdpdr1 = kdpdr+ 2
kdpar1 = kdpar+ 2
kipdr5 = kipdr+12
kipdr6 = kipdr+14
kipar6 = kipar+14
kdpdr6 = kdpdr+14
kdpar6 = kdpar+14
kipdr7 = kipdr+16
kipar7 = kipar+16
kdpdr7 = kdpdr+16
kdpar7 = kdpar+16
kipdr0 = kipdr+ 0
kipar0 = kipar+ 0
kdpdr0 = kdpdr+ 0
kdpar0 = kdpar+ 0
kipdr1 = kipdr+ 2
kipar1 = kipar+ 2
kdpdr1 = kdpdr+ 2
kdpar1 = kdpar+ 2
kipdr5 = kipdr+12
kipdr6 = kipdr+14
kipar6 = kipar+14
kdpdr6 = kdpdr+14
kdpar6 = kdpar+14
kipdr7 = kipdr+16
kipar7 = kipar+16
kdpdr7 = kdpdr+16
kdpar7 = kdpar+16
p0p1p2 = <1*100>+2 ; page 0, +1 click, +2
p0p1p4 = <1*100>+4 ; page 0, +1 click, +4
p1base = <1*20000> ; page 1
p1p0p2 = p1base+2 ; page 1, +2
p1m1p0 = p1base+<127.*100> ; page 1, 128-1 click
p2base = <2*20000> ; page 2
p2m1p0 = p2base+<127.*100> ; page 1, 128-1 click
p2m1m4 = p2base+<127.*100>-4 ; page 1, 128-1 click, -4
p3base = <3*20000> ; page 3
p4base = <4*20000> ; page 4
p5base = <5*20000> ; page 5
p6base = <6*20000> ; page 6
p6p1p2 = p6base+<1*100>+2 ; page 6, +1 click, +2
p7base = <7*20000> ; page 7
p0p1p2 = <1*100>+2 ; page 0, +1 click, +2
p0p1p4 = <1*100>+4 ; page 0, +1 click, +4
p1base = <1*20000> ; page 1
p1p0p2 = p1base+2 ; page 1, +2
p1m1p0 = p1base+<127.*100> ; page 1, 128-1 click
p2base = <2*20000> ; page 2
p2m1p0 = p2base+<127.*100> ; page 1, 128-1 click
p2m1m4 = p2base+<127.*100>-4 ; page 1, 128-1 click, -4
p3base = <3*20000> ; page 3
p4base = <4*20000> ; page 4
p5base = <5*20000> ; page 5
p6base = <6*20000> ; page 6
p6p1p2 = p6base+<1*100>+2 ; page 6, +1 click, +2
p7base = <7*20000> ; page 7
;
; helper macro for trace area check setup (from cpu_details A4)
.macro htinit,buf,nent