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update tbench and tcode

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- tools/bin/tmuconv: add memory system register names
- tools/src
  - librw11/Rw11Cpu: add kCPUUBMAP
  - librwxxtpp/RtclRw11Cpu.cpp: use kCPUUBMAP
- tools/tbench
  - cp/cp_all.dat: add test_cp_ubmap.tcl
  - cp/test_cp_cpubasics.tcl: add creset test
  - cp/test_cp_gr.tcl: streamline, use longer command chains
  - cp/test_cp_membasics.tcl: add 22bit mode tests
  - cp/test_cp_ubmap.tcl: added, test access via ubmap
  - w11a/test_w11a_dstr_word_flow.tcl: renamed from test_w11a_dstm_word_flow.tcl
  - w11a/test_w11a_cdma.tcl: added, test bwm/brm with active CPU
  - w11a/test_w11a_inst_traps.tcl: use defs_cpu.mac include
  - w11a/test_w11a_inst_wait.tcl: added, tests WAIT instruction
  - w11a/w11a_all.dat: add test_w11a_inst_wait.tcl, test_w11a_cdma.tcl
- tools/tcl/rw11/defs.tcl: add A_UBMAP
- tools/tcode
  - cpu_details.mac: add A5
  - cpu_mmu.mac: add F2
This commit is contained in:
wfjm 2023-01-06 14:02:45 +01:00
parent fdc3479c14
commit ba4aa45c48
19 changed files with 501 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
tools/bin/tmuconv
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@ -1,10 +1,11 @@
#!/usr/bin/perl -w
# $Id: tmuconv 1340 2023-01-01 08:43:05Z mueller $
# $Id: tmuconv 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2008-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2008-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-05 1346 1.1.13 add memory system register names
# 2022-12-29 1340 1.1.12 fix ru header
# 2022-12-01 1324 1.1.11 change VFETCH text for MMU(250) and FPP(244)
# 2022-11-18 1316 1.1.10 add -t_ru06 and -t_flow
@ -279,6 +280,12 @@ my %pdp11_regs = ( # use simh naming convention
177770=> "mbrk",
177766=> "cpuerr",
177764=> "sysid",
177762=> "hisize", # not a simh name !!
177760=> "losize", # not a simh name !!
177752=> "hm", # not a simh name !!
177744=> "syserr", # not a simh name !!
177742=> "hiaddr", # not a simh name !!
177740=> "loaddr", # not a simh name !!
177600=> "uipdr0",
177602=> "uipdr1",
177604=> "uipdr2",

6
tools/src/librw11/Rw11Cpu.cpp
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@ -1,9 +1,10 @@
// $Id: Rw11Cpu.cpp 1274 2022-08-08 09:21:53Z mueller $
// $Id: Rw11Cpu.cpp 1346 2023-01-06 12:56:08Z mueller $
// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// Revision History:
// Date Rev Version Comment
// 2023-01-05 1346 1.2.22 add kCPUUBMAP
// 2022-08-08 1274 1.2.21 ssr->mmr rename
// 2019-06-29 1175 1.2.20 MemWriteByte(): use membe
// 2019-04-30 1143 1.2.19 add m9312 setup and HasM9312()
@ -144,6 +145,7 @@ const uint16_t Rw11Cpu::kCPUMBRK;
const uint16_t Rw11Cpu::kCPUERR;
const uint16_t Rw11Cpu::kCPUSYSID;
const uint16_t Rw11Cpu::kCPUSDREG;
const uint16_t Rw11Cpu::kCPUUBMAP;
const uint16_t Rw11Cpu::kMEMHISIZE;
const uint16_t Rw11Cpu::kMEMLOSIZE;

7
tools/src/librw11/Rw11Cpu.hpp
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@ -1,9 +1,10 @@
// $Id: Rw11Cpu.hpp 1274 2022-08-08 09:21:53Z mueller $
// $Id: Rw11Cpu.hpp 1346 2023-01-06 12:56:08Z mueller $
// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// Revision History:
// Date Rev Version Comment
// 2023-01-05 1346 1.2.22 add kCPUUBMAP
// 2022-08-08 1274 1.2.21 ssr->mmr rename
// 2019-06-07 1160 1.2.20 Stats() not longer const
// 2019-04-30 1143 1.2.19 add HasM9312()
@ -34,7 +35,6 @@
// 2013-01-27 478 0.1 First draft
// ---------------------------------------------------------------------------
/*!
\brief Declaration of class Rw11Cpu.
*/
@ -246,6 +246,7 @@ namespace Retro {
static const uint16_t kCPUERR = 0177766; //!< CPU CPUERR address
static const uint16_t kCPUSYSID = 0177764; //!< CPU SYSID address
static const uint16_t kCPUSDREG = 0177570; //!< CPU SDREG address
static const uint16_t kCPUUBMAP = 0170200; //!< UBMAP base address
static const uint16_t kMEMHISIZE = 0177762; //!< MEM HISIZE address
static const uint16_t kMEMLOSIZE = 0177760; //!< MEM LOSIZE address

7
tools/src/librwxxtpp/RtclRw11Cpu.cpp
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@ -1,9 +1,10 @@
// $Id: RtclRw11Cpu.cpp 1292 2022-09-04 06:10:05Z mueller $
// $Id: RtclRw11Cpu.cpp 1346 2023-01-06 12:56:08Z mueller $
// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// Revision History:
// Date Rev Version Comment
// 2023-01-05 1346 1.2.37 use kCPUUBMAP
// 2022-09-03 1292 1.2.36 M_show: fix mmr1 display, better mmr0 display
// 2022-08-11 1276 1.2.35 ssr->mmr rename
// 2022-07-07 1249 1.2.34 BUGFIX: quit before mem write if asm-11 error seen
@ -1466,7 +1467,7 @@ int RtclRw11Cpu::M_show(RtclArgs& args)
} else if (opt == "-ubmap") {
uint16_t ubmap[64];
RlinkCommandList clist;
clist.AddWreg(base + Rw11Cpu::kCPAL, 0170200);
clist.AddWreg(base + Rw11Cpu::kCPAL, Rw11Cpu::kCPUUBMAP);
clist.AddRblk(base + Rw11Cpu::kCPMEMI, ubmap, 64);
if (!Server().Exec(clist, emsg)) return args.Quit(emsg);
sos << "unibus map:" << endl;

4
tools/tbench/.gitignore vendored Normal file
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@ -0,0 +1,4 @@
# simulation stuff
rlink_cext_*
sysmon_stim
tmu_ofile

3
tools/tbench/cp/cp_all.dat
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@ -1,4 +1,4 @@
# $Id: cp_all.dat 1310 2022-10-27 16:15:50Z mueller $
# $Id: cp_all.dat 1346 2023-01-06 12:56:08Z mueller $
#
## steering file for all cp tests
#
@ -6,5 +6,6 @@ test_cp_gr.tcl
test_cp_psw.tcl
test_cp_membasics.tcl
test_cp_ibrbasics.tcl
test_cp_ubmap.tcl
test_cp_cpubasics.tcl
#

29
tools/tbench/cp/test_cp_cpubasics.tcl
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@ -1,9 +1,10 @@
# $Id: test_cp_cpubasics.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_cp_cpubasics.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-05 1346 1.1.2 add creset test
# 2015-07-19 702 1.1.1 ignore attn in stat checks
# 2015-05-09 676 1.1 w11a start/stop/suspend overhaul
# 2013-03-31 502 1.0 Initial version
@ -114,7 +115,7 @@ $cpu cp -resume \
tmpproc_checkr2inc $rr2_1
tmpproc_checkr2inc [expr {$rr2_2 - $rr2_1}]
rlc log " suspend than step, two steps should inc r2 once"
rlc log " suspend then step, two steps should inc r2 once"
$cpu cp -suspend \
-wr2 00000 \
-step \
@ -133,3 +134,25 @@ rlc log " creset, check cpususp=0"
# cycle delay. So do -estat after next command
$cpu cp -creset \
-rr2 -estat 0
rlc log " A3: check that creset clears PSW,MMR0, MMR3 ---------------"
set mmr0 [$cpu imap mmr0]
set mmr3 [$cpu imap mmr3]
set psw_val [regbld rw11::PSW rset {pri 7}]
set mmr0_val [regbld rw11::MMR0 anr ale ard trp ent ena]
set mmr3_val [regbld rw11::MMR3 ena_ubm ena_22bit d_km d_sm d_um]
rlc log " write ps,mmr0,mmr3 and read back"
$cpu cp -wps $psw_val \
-wibr $mmr0 $mmr0_val \
-wibr $mmr3 $mmr3_val \
-rps -edata $psw_val \
-ribr $mmr0 -edata $mmr0_val \
-ribr $mmr3 -edata $mmr3_val
rlc log " creset and check that ps,mmr0,mmr3 cleared"
$cpu cp -creset \
-rps -edata 0 \
-ribr $mmr0 -edata 0 \
-ribr $mmr3 -edata 0

69
tools/tbench/cp/test_cp_gr.tcl
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@ -1,9 +1,10 @@
# $Id: test_cp_gr.tcl 1310 2022-10-27 16:15:50Z mueller $
# $Id: test_cp_gr.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-05 1346 1.0.2 streamline, use longer command chains
# 2022-10-27 1309 1.0.1 rename _gpr -> _gr
# 2013-03-31 502 1.0 Initial version
#
@ -16,49 +17,49 @@
# ----------------------------------------------------------------------------
rlc log "test_cp_gr: test cp access to general registers ---------------------"
rlc log " write set 0"
$cpu cp -wps 0000000
$cpu cp -wr0 0000001 \
-wr1 0000101
$cpu cp -wr2 0000201 \
-wr3 0000301
$cpu cp -wr4 0000401 \
$cpu cp -wps 0000000 \
-wr0 0000001 \
-wr1 0000101 \
-wr2 0000201 \
-wr3 0000301 \
-wr4 0000401 \
-wr5 0000501
rlc log " write set 1"
$cpu cp -wps 0004000
$cpu cp -wr0 0010001 \
-wr1 0010101
$cpu cp -wr2 0010201 \
-wr3 0010301
$cpu cp -wr4 0010401 \
$cpu cp -wps [regbld rw11::PSW rset] \
-wr0 0010001 \
-wr1 0010101 \
-wr2 0010201 \
-wr3 0010301 \
-wr4 0010401 \
-wr5 0010501
rlc log " write all sp and pc"
$cpu cp -wps 0000000 -wsp 0000601; # ksp
$cpu cp -wps 0040000 -wsp 0010601; # ssp
$cpu cp -wps 0140000 -wsp 0020601; # usp
$cpu cp -wps 0000000 -wpc 0000701; # pc
$cpu cp -wps [regbld rw11::PSW {cmode k}] -wsp 0000601 \
-wps [regbld rw11::PSW {cmode s}] -wsp 0010601 \
-wps [regbld rw11::PSW {cmode u}] -wsp 0020601 \
-wps [regbld rw11::PSW {cmode k}] -wpc 0000701
rlc log " read set 0"
$cpu cp -wps 0000000; # set 0
$cpu cp -rr0 -edata 0000001 \
-rr1 -edata 0000101
$cpu cp -rr2 -edata 0000201 \
-rr3 -edata 0000301
$cpu cp -rr4 -edata 0000401 \
$cpu cp -wps 0000000 \
-rr0 -edata 0000001 \
-rr1 -edata 0000101 \
-rr2 -edata 0000201 \
-rr3 -edata 0000301 \
-rr4 -edata 0000401 \
-rr5 -edata 0000501
rlc log " read set 1"
$cpu cp -wps 0004000; # set 1
$cpu cp -rr0 -edata 0010001 \
-rr1 -edata 0010101
$cpu cp -rr2 -edata 0010201 \
-rr3 -edata 0010301
$cpu cp -rr4 -edata 0010401 \
$cpu cp -wps [regbld rw11::PSW rset] \
-rr0 -edata 0010001 \
-rr1 -edata 0010101 \
-rr2 -edata 0010201 \
-rr3 -edata 0010301 \
-rr4 -edata 0010401 \
-rr5 -edata 0010501
rlc log " read all sp and pc"
$cpu cp -wps 0000000 -rsp -edata 0000601; # ksp
$cpu cp -wps 0040000 -rsp -edata 0010601; # ssp
$cpu cp -wps 0140000 -rsp -edata 0020601; # usp
$cpu cp -wps 0000000 -rpc -edata 0000701; # pc
$cpu cp -wps [regbld rw11::PSW {cmode k}] -rsp -edata 0000601 \
-wps [regbld rw11::PSW {cmode s}] -rsp -edata 0010601 \
-wps [regbld rw11::PSW {cmode u}] -rsp -edata 0020601 \
-wps [regbld rw11::PSW {cmode k}] -rpc -edata 0000701

47
tools/tbench/cp/test_cp_membasics.tcl
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@ -1,23 +1,26 @@
# $Id: test_cp_membasics.tcl 1170 2019-06-22 20:58:52Z mueller $
# $Id: test_cp_membasics.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2014-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2014-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-06 1346 1.1.1 add 22bit mode tests
# 2019-06-22 1170 1.1 add membe tests for memory accesses
# 2014-03-02 552 1.0 Initial version
#
# Test very basic memory interface gymnastics
# 1. write/read address register
# 2. write/read memory via wm/wmi/rm/rmi (16 bit mode)
# 3. write/read memory via bwm/brm (16 bit mode)
#
# 1. write/read address register
# 2. write/read memory via wm/wmi/rm/rmi (16 bit mode)
# 3. write/read memory via bwm/brm (16 bit mode)
# 4. write/read memory test membe (16 bit mode)
# 5. write/read memory via bwm/brm (22 bit mode)
# Note: ubmap mode is tested in test_cp_ubmap.tcl
# ----------------------------------------------------------------------------
rlc log "test_cp_membasics: Test very basic memory interface gymnastics ------"
# --------------------------------------------------------------------
rlc log " write/read address register"
rlc log " A1: write/read address register ---------------------------"
# test wal
$cpu cp -wal 002000 \
@ -31,7 +34,7 @@ $cpu cp -wal 003000 \
-rah -edata 000001
# --------------------------------------------------------------------
rlc log " write/read memory via wm/wmi/rm/rmi (16 bit mode)"
rlc log " A2: write/read memory via wm/wmi/rm/rmi (16 bit mode) -----"
# simple write/read without increment
$cpu cp -wal 002000 \
@ -64,7 +67,7 @@ $cpu cp -wal 002100 \
-rah -edata 000000
# --------------------------------------------------------------------
rlc log " write/read memory via bwm/brm (16 bit mode)"
rlc log " A3: write/read memory via bwm/brm (16 bit mode) -----------"
$cpu cp -wal 02200 \
-bwm {007700 007710 007720 007730}
@ -72,7 +75,7 @@ $cpu cp -wal 02200 \
-brm 4 -edata {007700 007710 007720 007730}
# --------------------------------------------------------------------
rlc log " write/read memory - test membe (16 bit mode)"
rlc log " A4: write/read memory - test membe (16 bit mode) ----------"
# init 4 words
$cpu cp -wal 002300 \
@ -123,3 +126,27 @@ $cpu cp -wal 002300 \
-brm 4 -edata {0x4400 0x5599 0x66cc 0x7733} \
-wmembe [bvi b2 "11"] \
-rmembe -edata [bvi b3 "011"]
# --------------------------------------------------------------------
rlc log " A5: write/read memory via bwm/brm (22 bit mode) -----------"
# determine memory size from losize and write/read top 32 memory words
# get losize (is last click of available memory)
$cpu cp -ribr [$cpu imap losize] losize
set watop [expr $losize<<6]; # clicks to bytes
set waltop [expr $watop & 0177776]; # get lower 16 bit
set wahtop [expr ($watop>>16) & 076]; # get upper 6 bit
set buf {}
for {set i 0} {$i < 32} {incr i} {
lappend buf [expr 0123000 + $i]
}
# write in 22bit mode
$cpu cp -wal $waltop \
-wah [regbld rw11::CP_AH p22 [list addr $wahtop]] \
-bwm $buf
# read and check
$cpu cp -wal $waltop \
-wah [regbld rw11::CP_AH p22 [list addr $wahtop]] \
-brm [llength $buf] -edata $buf

81
tools/tbench/cp/test_cp_ubmap.tcl Normal file
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@ -0,0 +1,81 @@
# $Id: test_cp_ubmap.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2023- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-05 1346 1.0 Initial version
#
# Test memory access via ubmap
#
# ----------------------------------------------------------------------------
rlc log "test_cp_ubmap: Test ubmap and memory access via ubmap ------------"
rlc log " A1: write/read ubmap registers ----------------------------"
rlc log " write ubmap registers"
set ubval {}
for {set i 0} {$i < 31} {incr i} {
lappend ubval [expr 0110000 + 010*$i]
lappend ubval [expr 040 + $i]
}
$cpu cp -wal $rw11::A_UBMAP \
-bwm $ubval
rlc log " read and check ubmap registers"
$cpu cp -wal $rw11::A_UBMAP \
-brm [llength $ubval] -edata $ubval
rlc log " A2: write/read memory via ubmap ---------------------------"
# ubmap.0 offsets by 03000
# data will be written 01400 (unmapped) and 04400 (mapped)
rlc log " bwm via ubmap with mmr3 ubmap disabled"
$cpu cp -wal $rw11::A_UBMAP \
-bwm {003000 0}
$cpu cp -wal 001400 \
-wah [regbld rw11::CP_AH ubm] \
-bwm {000111 000222 000333 000444}
rlc log " check via direct read"
$cpu cp -wal 001400 \
-brm 4 -edata {000111 000222 000333 000444}
rlc log " bwm via ubmap with mmr3 ubmap enabled"
$cpu cp -wibr [$cpu imap mmr3] [regbld rw11::MMR3 ena_ubm]
$cpu cp -wal 001400 \
-wah [regbld rw11::CP_AH ubm] \
-bwm {010111 010222 010333 010444}
rlc log " check via direct read"
$cpu cp -wal 001400 \
-brm 4 -edata {000111 000222 000333 000444} \
-wal 004400 \
-brm 4 -edata {010111 010222 010333 010444}
rlc log " read via ubmap"
$cpu cp -wal 001400 \
-wah [regbld rw11::CP_AH ubm] \
-brm 4 -edata {010111 010222 010333 010444}
rlc log " A3: write/read memory via ubmap over page border ----------"
# ubmap.0 offsets by 04000
# ubmap.1 offsets by 05000
# transfer to 017774:020002 goes to 023774,023776,005000,005002
$cpu cp -wal $rw11::A_UBMAP \
-bwm {004000 0 005000 0}
$cpu cp -wal 023774 -bwm {0 0 0} \
-wal 025000 -bwm {0 0 0}
rlc log " bwm via ubmap with mmr3 ubmap enabled"
$cpu cp -wal 017774 \
-wah [regbld rw11::CP_AH ubm] \
-bwm {030111 030222 030333 030444}
rlc log " check via direct read"
$cpu cp -wal 023774 -brm 3 -edata {030111 030222 0} \
-wal 005000 -brm 3 -edata {030333 030444 0}
rlc log " read via ubmap"
$cpu cp -wal 017774 \
-wah [regbld rw11::CP_AH ubm] \
-brm 5 -edata {030111 030222 030333 030444 0}

88
tools/tbench/w11a/test_w11a_cdma.tcl Normal file
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@ -0,0 +1,88 @@
# $Id: test_w11a_cdma.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2023- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-06 1346 1.0 Initial version
#
# Test bwm/brm while CPU active
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_cdma: test bwm/brm while CPU active -----------------------"
rlc log " A1: bwm/brm while CPU busy --------------------------------"
$cpu ldasm -lst lst -sym sym {
. = 1000
stack:
start: clr r0 ; clear stop flag
clr r1 ; clear counter
mov #data,r2 ; ptr to data
100$: inc r1 ; bump counter
mov r2,r3 ; bump buffer
inc (r3)+
inc (r3)+
inc (r3)+
inc (r3)+
tst r0 ; check stop flag
beq 100$ ; loop till set
halt
stop:
;
data: .word 0
.word 0
.word 0
.word 0
buf: .blkw 128. ; buffer for dma
}
set buf {}
for {set i 0} {$i < 128} {incr i} {
lappend buf [expr 0075000 + $i]
}
# start code
rw11::asmrun $cpu sym
# write to buffer
$cpu cp -wal $sym(buf) \
-bwm $buf
# read back and check
$cpu cp -wal $sym(buf) \
-brm [llength $buf] -edata $buf
# end code by setting stop flag
$cpu cp -wr0 1
rw11::asmwait $cpu sym
# check that counter and data are consistent
$cpu cp -rr1 cnt
$cpu cp -wal $sym(data) \
-brm 4 -edata [list $cnt $cnt $cnt $cnt]
rlc log " A2: bwm/brm while CPU in WAIT -----------------------------"
$cpu ldasm -lst lst -sym sym {
. = 1000
stack:
start: wait ; wait for interrupt
100$: halt
stop:
;
buf: .blkw 128. ; buffer for dma
}
# start code
$cpu cp -creset \
-stapc $sym(start)
# check that wait does wait
rw11::asmtreg $cpu pc $sym(start:100$)
# write to buffer
$cpu cp -wal $sym(buf) \
-bwm $buf
rw11::asmtreg $cpu pc $sym(start:100$)
# read back and check
$cpu cp -wal $sym(buf) \
-brm [llength $buf] -edata $buf
rw11::asmtreg $cpu pc $sym(start:100$)
# stop code
$cpu cp -stop

9
tools/tbench/w11a/test_w11a_dstm_word_flow.tcl → tools/tbench/w11a/test_w11a_dstr_word_flow.tcl
View File

@ -1,18 +1,19 @@
# $Id: test_w11a_dstm_word_flow.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_w11a_dstr_word_flow.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-05 1346 1.0.3 renamed dstm -> dstr (as it is named vhdl)
# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
# 2014-03-01 552 1.0.1 check that unused regs stay 0
# 2013-03-31 502 1.0 Initial version
#
# Test dstm flow with inc ... instructions for word access
# Test dstr flow with inc ... instructions for word access
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_dstm_word_flow: test dstm flow for word with inc ..."
rlc log "test_w11a_dstr_word_flow: test dstr flow for word with inc ..."
rlc log " r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5)"
# code register pre/post conditions beyond defaults

39
tools/tbench/w11a/test_w11a_inst_traps.tcl
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@ -1,9 +1,10 @@
# $Id: test_w11a_inst_traps.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_w11a_inst_traps.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-06 1346 1.0.3 use defs_cpu.mac include
# 2014-07-27 575 1.0.2 drop tout value from asmwait, reply on asmwait_tout
# 2014-03-01 552 1.0.1 check that unused regs stay 0; use stack:; check sp;
# 2013-04-01 502 1.0 Initial version
@ -12,51 +13,51 @@
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_inst_traps: test trap type instructions"
rlc log "test_w11a_inst_traps: test trap type instructions -------------------"
# code register pre/post conditions beyond defaults
# r5 #data -> #data+6*5*2
$cpu ldasm -lst lst -sym sym {
.include |lib/defs_cpu.mac|
;
. = 14
.word h.bpt ; vec 14: bpt
.word vh.bpt ; vec 14: bpt
.word 340
.word h.iot ; vec 20: iot
.word vh.iot ; vec 20: iot
.word 341
. = 30
.word h.emt ; vec 30: emt
.word vh.emt ; vec 30: emt
.word 342
.word h.trp ; vec 34: trap
.word vh.trp ; vec 34: trap
.word 343
;
psw = 177776
;
. = 1000
stack:
start: mov #350,@#psw
start: mov #350,@#cp.psw
bpt
350$: mov #351,@#psw
350$: mov #351,@#cp.psw
iot
351$: mov #352,@#psw
351$: mov #352,@#cp.psw
emt 100
352$: mov #353,@#psw
352$: mov #353,@#cp.psw
emt 200
353$: mov #354,@#psw
353$: mov #354,@#cp.psw
trap 10
354$: mov #355,@#psw
354$: mov #355,@#cp.psw
trap 20
355$: halt
stop:
;
h.bpt: mov @#psw,(r5)+ ; record psw
vh.bpt: mov @#cp.psw,(r5)+ ; record psw
mov #1014,(r5)+ ; record trap id
br iexit
h.iot: mov @#psw,(r5)+
vh.iot: mov @#cp.psw,(r5)+
mov #1020,(r5)+
br iexit
h.emt: mov @#psw,(r5)+
vh.emt: mov @#cp.psw,(r5)+
mov #1030,(r5)+
br iexit
h.trp: mov @#psw,(r5)+
vh.trp: mov @#cp.psw,(r5)+
mov #1034,(r5)+
;
iexit: mov (sp),r4 ; get stack PC

80
tools/tbench/w11a/test_w11a_inst_wait.tcl Normal file
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@ -0,0 +1,80 @@
# $Id: test_w11a_inst_wait.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2023- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-06 1346 1.0 Initial version
#
# Test WAIT instruction. Can't be done in tcode because the test requires
# console interaction for monitoring the CPU state.
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_inst_wait: test wait instruction --------------------------"
$cpu ldasm -lst lst -sym sym {
.include |lib/defs_cpu.mac|
;
; setup pirq vector
. = 000240
.word vh.pir
.word cp.pr7
;
. = 1000
stack:
start: inc r0
100$: wait ; wait for interrupt
200$: inc r0
300$: halt
stop:
;
; PIRQ handler
vh.pir: clr cp.pir ; cancel PIRQ requests
rti
}
rlc log " A1: test that wait does wait-------------------------------"
rw11::asmrun $cpu sym r0 0
# check that wait does wait
rw11::asmtreg $cpu r0 1 \
sp $sym(stack) \
pc $sym(start:200$)
rw11::asmtreg $cpu r0 1 \
sp $sym(stack) \
pc $sym(start:200$)
rw11::asmtreg $cpu r0 1 \
sp $sym(stack) \
pc $sym(start:200$)
# trigger PIRQ interrupt with console write to cp.pir
$cpu cp -wibr [$cpu imap pirq] [regbld rw11::PIRQ {pir 2}]
# check that interrupt was handled and cpu halted
rw11::asmwait $cpu sym; # checks pc
rw11::asmtreg $cpu r0 2 \
sp $sym(stack)
rlc log " A2: test that doesn't block when single stepped -----------"
$cpu cp -wr0 0 \
-wpc $sym(start)
# step over 1st inc
$cpu cp -step \
-rr0 -edata 1 \
-rpc -edata $sym(start:100$) \
-rstat -edata 000100
# step over wait
$cpu cp -step \
-rr0 -edata 1 \
-rpc -edata $sym(start:200$) \
-rstat -edata 000100
# step over 2nd inc
$cpu cp -step \
-rr0 -edata 2 \
-rpc -edata $sym(start:300$) \
-rstat -edata 000100
$cpu cp -stop

6
tools/tbench/w11a/test_w11a_mem70.tcl
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@ -1,13 +1,13 @@
# $Id: test_w11a_mem70.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_w11a_mem70.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2017-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2017-06-25 916 1.0 Initial version
#
# Test 11/70 memory system registers and cache
# adopt from old pdpcp style stim files
# adapted from old pdpcp style stim files
# tb/tb_w11a_mem70.dat --> tests 1-3
# tb/tb_w11a_mem70_n2.dat --> test 4 (size adaptive now)
# tb/tb_w11a_mem70_s3.dat /

6
tools/tbench/w11a/w11a_all.dat
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@ -1,4 +1,4 @@
# $Id: w11a_all.dat 1320 2022-11-22 18:52:59Z mueller $
# $Id: w11a_all.dat 1346 2023-01-06 12:56:08Z mueller $
#
## steering file for all w11a tests
#
@ -8,9 +8,11 @@ test_w11a_mem70.tcl
#
test_w11a_srcr_word_flow.tcl
test_w11a_dstw_word_flow.tcl
test_w11a_dstm_word_flow.tcl
test_w11a_dstr_word_flow.tcl
test_w11a_dsta_flow.tcl
#
test_w11a_inst_quick.tcl
test_w11a_inst_traps.tcl
test_w11a_inst_wait.tcl
test_w11a_cdma.tcl
#

8
tools/tcl/rw11/defs.tcl
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@ -1,9 +1,10 @@
# $Id: defs.tcl 1323 2022-12-01 08:00:41Z mueller $
# $Id: defs.tcl 1346 2023-01-06 12:56:08Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2014-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-01-05 1346 1.0.13 add A_UBMAP
# 2022-11-29 1323 1.0.12 rename adderr -> oddadr (in cpuerr)
# 2022-11-21 1320 1.0.11 rename RUST recrsv -> recser
# 2022-09-03 1292 1.0.10 shorter field names for MMR0,MMR1
@ -96,6 +97,9 @@ namespace eval rw11 {
set A_CNTRL 0177746
regdsc CNTRL {frep 5 2} {fmiss 3 2} {disutrap 1} {distrap 0}
#
# UBMAP - Unibus mapping register base ---------------------------
set A_UBMAP 0170200
#
# setup regmap
#
rw11util::regmap_add rw11 psw {?? PSW}

24
tools/tcode/cpu_details.mac
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@ -1,10 +1,10 @@
; $Id: cpu_details.mac 1345 2023-01-04 18:05:42Z mueller $
; $Id: cpu_details.mac 1346 2023-01-06 12:56:08Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2023-01-04 1345 1.0 Initial version
; 2023-01-06 1346 1.0 Initial version
; 2022-07-18 1259 0.1 First draft
;
; Test CPU details
@ -98,6 +98,7 @@
; part 8: traced RTI that clears tbit
; part 9: EMT that sets tbit
; part 10: PIRQ that sets tbit
; A5 MBRK
;
; Test A1: PIRQ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; This sub-section verifies operation of PIRQ register
@ -1534,6 +1535,23 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler
;
9999$: iot ; end of test A4.4
;
; Test A5: MBRK +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Test A5.1 -- MBRK direct write/read test +++++++++++++++++++++++++++
; MBRK is a writable and readable 8 bit register an has no specific
; function in w11.
;
ta0501: mov #cp.mbr,r0
clr (r0)
htsteq (r0)
mov #177777,(r0) ; test word write
hcmpeq #377,(r0)
movb #123,(r0) ; write low byte
hcmpeq #123,(r0)
movb #321,1(r0) ; write high byte (no effect)
hcmpeq #123,(r0)
;
9999$: iot ; end of test A5.1
;
; Section B: Stress and flow tests ===========================================
; B1 address mode torture tests
; B1.1 src-dst update hazards with (r0)+,(r0)
@ -2133,7 +2151,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler
; END OF ALL TESTS - loop closure ============================================
;
mov tstno,r0 ; hack, for easy monitoring ...
hcmpeq tstno,#38. ; all tests done ?
hcmpeq tstno,#39. ; all tests done ?
;
jmp loop
;

74
tools/tcode/cpu_mmu.mac
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@ -1,10 +1,10 @@
; $Id: cpu_mmu.mac 1345 2023-01-04 18:05:42Z mueller $
; $Id: cpu_mmu.mac 1346 2023-01-06 12:56:08Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2023-01-04 1345 1.0 Initial version
; 2023-01-05 1346 1.0 Initial version
; 2022-07-24 1262 0.1 First draft
;
; Test CPU MMU: all aspects of the MMU
@ -53,8 +53,11 @@
kipdr0 = kipdr+ 0
kipar0 = kipar+ 0
kdpdr0 = kdpdr+ 0
kdpar0 = kdpar+ 0
kipdr1 = kipdr+ 2
kipar1 = kipar+ 2
kdpdr1 = kdpdr+ 2
kdpar1 = kdpar+ 2
kipdr5 = kipdr+12
kipdr6 = kipdr+14
kipar6 = kipar+14
@ -62,6 +65,8 @@
kdpar6 = kdpar+14
kipdr7 = kipdr+16
kipar7 = kipar+16
kdpdr7 = kdpdr+16
kdpar7 = kdpar+16
p0p1p2 = <1*100>+2 ; page 0, +1 click, +2
p0p1p4 = <1*100>+4 ; page 0, +1 click, +4
@ -2514,8 +2519,10 @@ te0201: mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18
clr v..pir+2
;
; Section F: miscellaneous ===================================================
; F1.1 test D-to-I mapping for (PC) address modes I
; F1.2 test D-to-I mapping for (PC) address modes II
; F1 test D-to-I mapping
; F1.1 for (PC) address modes I
; F1.2 for (PC) address modes II
; F2 test LOSIZE register and access to full memory
;
; Test F1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
@ -2624,11 +2631,66 @@ tf0102: mov #154345,@#p6base ; inititialize target
;
9999$: iot ; end of test F1.2
;
; Summary
; Test F2: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; Test F2.1 -- test LOSIZE register and access to full memory ++++++++
; Read memory size from LOSIZE, write one word every 64 kB and read back.
; Quite fast: at most 60 words (4M-256k)/64k.
; Tests runs with kernel D space enabled (an exception!)
;
tf0201: mov kipdr0,kdpdr0 ; set up kernel D space 1-to-1 mapping
mov kipar0,kdpar0
mov kipdr1,kdpdr1
mov kipar1,kdpar1
mov kipdr6,kdpdr6
mov kipar6,kdpar6
mov kipdr7,kdpdr7
mov kipar7,kdpar7
mov #m3.e22!m3.dkm,mmr3 ; enable D space for kernel; 22 bit
mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
;
htsteq hisize ; HISIZE must be zero
mov losize,r0 ; last accessible click (64B)
inc r0
ccc
ror r0 ; shift right 10 bits, no sign extend
ash #-9.,r0 ; memory size in 64 kB chunks
dec r0 ; number of chunks to test
ble 2000$ ; quit if memory too small
mov #2000,r1 ; step size 64kB in clicks
mov #kdpar6,r2 ; ptr to kdpar6
mov #p6base,r3 ; ptr to write/read test location
; write memory
mov r0,r4 ; initialize counter
mov r1,r5 ; initialize current par
100$: mov r5,(r2) ; set par
mov r5,(r3) ; write data
add r1,r5 ; bump pointer
sob r4,100$
; read memory
mov r0,r4 ; initialize counter
mov r1,r5 ; initialize current par
200$: mov r5,(r2) ; set par
hcmpeq r5,(r3) ; check data
add r1,r5 ; bump pointer
sob r4,200$
;
2000$: reset ; mmu off ;! MMU off
clr kdpdr0
clr kdpar0
clr kdpdr1
clr kdpar1
clr kdpdr6
clr kdpar6
clr kdpdr7
clr kdpar7
;
9999$: iot ; end of test F2.1
;
; END OF ALL TESTS - loop closure ============================================
;
mov tstno,r0 ; hack, for easy monitoring ...
hcmpeq tstno,#32. ; all tests done ?
hcmpeq tstno,#33. ; all tests done ?
call chkpdr ; kernel pdr/par OK ?
;
jmp loop