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add tbench test_w11a_cpu_halt; minor changes; cosmetics

Browse Source 
- tools/src/
  - librwxxtpp/RtclRw11Cpu.cpp: fix rust code name
- tools/tbench
  - cp/test_cp_cpubasics.tcl: use symbolic names via regbld
  - w11a/test_w11a_cdma.tcl: fix attention harvest
  - w11a/test_w11a_cpu_halt.tcl: added, verifies fatal CPU halts
  - w11a/test_w11a_inst_wait.tcl: check cpu status
  - w11a/w11a_all.dat: add test_w11a_cpu_halt.tc
- tools/tcode
  - cpu_basics.mac: extend test A4.5
This commit is contained in:
wfjm
2023-01-07 13:51:33 +01:00
parent ba4aa45c48
commit 7f2d7f97d0
8 changed files with 311 additions and 112 deletions
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31
tools/tcode/cpu_basics.mac
View File

@@ -1,10 +1,10 @@
; $Id: cpu_basics.mac 1345 2023-01-04 18:05:42Z mueller $
; $Id: cpu_basics.mac 1347 2023-01-07 12:48:58Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2015-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2023-01-04 1345 1.0 Initial version
; 2023-01-07 1347 1.0 Initial version
; 2015-08-30 710 0.1 First draft
;
; Test CPU basics: most instructions except traps, EIS and FPP
@@ -31,7 +31,7 @@
; A4.2 jsr + cc
; A4.3 jsr r0-r5
; A4.4 jsr sp and rts sp
; A4.5 jsr r1,(r1)+
; A4.5 jsr r1,(r1)+ and jsr r2,@(r2)+
; A5 mark
;
; Test A1: ccop + bxx +++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -1001,7 +1001,7 @@ ta0404: hcmpeq sp,#stack ; check stack is default
;
9999$: iot ; end of test A4.4
;
; Test A4.5 -- jsr r1,(r1)+ ++++++++++++++++++++++++++++++++++++++++++
; Test A4.5 -- jsr r1,(r1)+ and jsr r2,@(r2)+ ++++++++++++++++++++++++
; Using the same register in the destination specifier and as linkage
; register is possible and works as usual.
;
@@ -1010,13 +1010,34 @@ ta0405: mov #200$,r1
100$: .word 000301 ; 1st arg
.word 000302 ; 2nd arg
hcmpeq #200$+2,r1 ; check that incremented r1 restored
br 9999$
br 1000$
;
200$: hcmpeq #100$,r1 ; check r1 holds address after jsr
hcmpeq #301,(r1)+ ; process 1st arg
hcmpeq #302,(r1)+ ; process 1st arg
rts r1
;
; Even using the 'linkage register' as list pointer in the caller and as
; argument pointer in the callee works as expected.
;
1000$: mov #1100$,r2 ; r2 prt to list of subroutines
jsr r2,@(r2)+ ; call 1st in list
.word 000401
jsr r2,@(r2)+ ; call 2nd in list
.word 000501
.word 000502
br 9999$
;
1100$: .word 1200$
.word 1300$
;
1200$: hcmpeq #401,(r2)+ ; process 1st arg
rts r2
;
1300$: hcmpeq #501,(r2)+ ; process 1st arg
hcmpeq #502,(r2)+ ; process 2nd arg
rts r2
9999$: iot ; end of test A4.5
;
; Test A5 -- mark ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

104
tools/tcode/cpu_mmu.mac
View File

@@ -1,4 +1,4 @@
; $Id: cpu_mmu.mac 1346 2023-01-06 12:56:08Z mueller $
; $Id: cpu_mmu.mac 1347 2023-01-07 12:48:58Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
@@ -28,60 +28,60 @@
.include |lib/tcode_std_base.mac|
.include |lib/defs_mmu.mac|
; some useful definitions
uipdr0 = uipdr+ 0
uipar0 = uipar+ 0
udpdr0 = udpdr+ 0
udpar0 = udpar+ 0
udpdr1 = udpdr+ 2
udpar1 = udpar+ 2
udpdr2 = udpdr+ 4
udpar2 = udpar+ 4
uipdr0 = uipdr+ 0
uipar0 = uipar+ 0
udpdr0 = udpdr+ 0
udpar0 = udpar+ 0
udpdr1 = udpdr+ 2
udpar1 = udpar+ 2
udpdr2 = udpdr+ 4
udpar2 = udpar+ 4
sipdr0 = sipdr+ 0
sipar0 = sipar+ 0
sipdr1 = sipdr+ 2
sipar1 = sipar+ 2
sipdr2 = sipdr+ 4
sipar2 = sipar+ 4
sipdr3 = sipdr+ 6
sipar3 = sipar+ 6
sipdr6 = sipdr+14
sipar6 = sipar+14
sipdr7 = sipdr+16
sipar7 = sipar+16
sipdr0 = sipdr+ 0
sipar0 = sipar+ 0
sipdr1 = sipdr+ 2
sipar1 = sipar+ 2
sipdr2 = sipdr+ 4
sipar2 = sipar+ 4
sipdr3 = sipdr+ 6
sipar3 = sipar+ 6
sipdr6 = sipdr+14
sipar6 = sipar+14
sipdr7 = sipdr+16
sipar7 = sipar+16
kipdr0 = kipdr+ 0
kipar0 = kipar+ 0
kdpdr0 = kdpdr+ 0
kdpar0 = kdpar+ 0
kipdr1 = kipdr+ 2
kipar1 = kipar+ 2
kdpdr1 = kdpdr+ 2
kdpar1 = kdpar+ 2
kipdr5 = kipdr+12
kipdr6 = kipdr+14
kipar6 = kipar+14
kdpdr6 = kdpdr+14
kdpar6 = kdpar+14
kipdr7 = kipdr+16
kipar7 = kipar+16
kdpdr7 = kdpdr+16
kdpar7 = kdpar+16
kipdr0 = kipdr+ 0
kipar0 = kipar+ 0
kdpdr0 = kdpdr+ 0
kdpar0 = kdpar+ 0
kipdr1 = kipdr+ 2
kipar1 = kipar+ 2
kdpdr1 = kdpdr+ 2
kdpar1 = kdpar+ 2
kipdr5 = kipdr+12
kipdr6 = kipdr+14
kipar6 = kipar+14
kdpdr6 = kdpdr+14
kdpar6 = kdpar+14
kipdr7 = kipdr+16
kipar7 = kipar+16
kdpdr7 = kdpdr+16
kdpar7 = kdpar+16
p0p1p2 = <1*100>+2 ; page 0, +1 click, +2
p0p1p4 = <1*100>+4 ; page 0, +1 click, +4
p1base = <1*20000> ; page 1
p1p0p2 = p1base+2 ; page 1, +2
p1m1p0 = p1base+<127.*100> ; page 1, 128-1 click
p2base = <2*20000> ; page 2
p2m1p0 = p2base+<127.*100> ; page 1, 128-1 click
p2m1m4 = p2base+<127.*100>-4 ; page 1, 128-1 click, -4
p3base = <3*20000> ; page 3
p4base = <4*20000> ; page 4
p5base = <5*20000> ; page 5
p6base = <6*20000> ; page 6
p6p1p2 = p6base+<1*100>+2 ; page 6, +1 click, +2
p7base = <7*20000> ; page 7
p0p1p2 = <1*100>+2 ; page 0, +1 click, +2
p0p1p4 = <1*100>+4 ; page 0, +1 click, +4
p1base = <1*20000> ; page 1
p1p0p2 = p1base+2 ; page 1, +2
p1m1p0 = p1base+<127.*100> ; page 1, 128-1 click
p2base = <2*20000> ; page 2
p2m1p0 = p2base+<127.*100> ; page 1, 128-1 click
p2m1m4 = p2base+<127.*100>-4 ; page 1, 128-1 click, -4
p3base = <3*20000> ; page 3
p4base = <4*20000> ; page 4
p5base = <5*20000> ; page 5
p6base = <6*20000> ; page 6
p6p1p2 = p6base+<1*100>+2 ; page 6, +1 click, +2
p7base = <7*20000> ; page 7
;
; helper macro for trace area check setup (from cpu_details A4)
.macro htinit,buf,nent