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add test_w11a_mem70.tcl; retire old tests tb_w11a_mem70*.dat
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wfjm
160
tools/tbench/w11a/test_w11a_mem70.tcl
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tools/tbench/w11a/test_w11a_mem70.tcl
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# $Id: test_w11a_mem70.tcl 916 2017-06-25 13:30:07Z mueller $
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#
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# Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# License disclaimer see License.txt in $RETROBASE directory
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#
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# Revision History:
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# Date Rev Version Comment
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# 2017-06-25 916 1.0 Initial version
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#
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# Test 11/70 memory system registers and cache
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# adopt from old pdpcp style stim files
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# tb/tb_w11a_mem70.dat --> tests 1-3
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# tb/tb_w11a_mem70_n2.dat --> test 4 (size adaptive now)
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# tb/tb_w11a_mem70_s3.dat /
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# ----------------------------------------------------------------------------
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rlc log "test_w11a_mem70: Test 11/70 memory system and cache ------"
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# --------------------------------------------------------------------
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rlc log " access all 11/70 memory system registers"
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# loaddr,hiaddr,syserr,cntrl,maint,hm and losize,hisize are contiguous
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$cpu cp -wal loaddr \
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-rmi -edata 000000 \
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-rmi -edata 000000 \
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-rmi -edata 000000 \
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-rmi -edata 000000 \
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-rmi -edata 000000 \
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-rmi \
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-wal losize \
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-rmi losize \
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-rmi -edata 000000
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set msize [expr {($losize+1) * 64}]
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rlc log [format " --> detected memory size: %4d kB" [expr {$msize/1024}]]
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# --------------------------------------------------------------------
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rlc log " Test 1: cache basic rmiss test - is data from mem on rmiss ?"
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# - the new configurable cache can be as big as 128 kByte
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# - the hit/miss tests below will work for up maximal cache size and use
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# 22bit mode access and two areas 128 kByte appart
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# wah/wal 00/0000xx or 000000xx
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# wah/wal 02/0000xx or 004000xx
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# write two areas
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$cpu cp -wa 00000000 -p22 \
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-bwm {000000 000002 000004 000006 000010 000012 000014 000016} \
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-wa 00400000 -p22 \
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-bwm {020000 020002 020004 020006 020010 020012 020014 020016}
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# read two areas, second read will definitively miss
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$cpu cp -wa 00000000 -p22 \
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-brm 8 -edata {000000 000002 000004 000006 000010 000012 000014 000016} \
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-wa 00400000 -p22 \
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-brm 8 -edata {020000 020002 020004 020006 020010 020012 020014 020016}
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# --------------------------------------------------------------------
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rlc log " Test 2: Hit/Miss register"
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# use data written in previous test
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# 7 read on same location -> 6 hits --> hm 111 111
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$cpu cp -wa 00400004 -p22 \
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-rm -edata 020004 \
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-rm -edata 020004 \
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-rm -edata 020004 \
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-rm -edata 020004 \
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-rm -edata 020004 \
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-rm -edata 020004 \
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-rm -edata 020004 \
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-wal hm \
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-rm -edata 000077
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# 1 read on conflicting address -> 1 miss --> hm 111 110
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# 1 read on next word in line -> 1 hit --> hm 111 101
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# read next 4 words -> alternating miss/hit --> hm 010 101
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$cpu cp -wa 00000004 -p22 \
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-rm -edata 000004 \
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-wal hm \
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-rm -edata 000076 \
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-wa 00000006 -p22 \
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-rm -edata 000006 \
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-wal hm \
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-rm -edata 000075 \
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-wa 00000010 -p22 \
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-rmi -edata 000010 \
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-rmi -edata 000012 \
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-rmi -edata 000014 \
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-rmi -edata 000016 \
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-wal hm \
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-rm -edata 000025
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# write next 4 words -> 4 miss --> hm 010 000
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# re-read these 4 words -> 4 hit --> hm 001 111
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$cpu cp -wa 00000020 -p22 \
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-bwm {000020 000022 000024 000026} \
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-wal hm \
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-rm -edata 000020 \
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-wa 00000020 -p22 \
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-brm 4 -edata {000020 000022 000024 000026} \
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-wal hm \
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-rm -edata 000017
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# --------------------------------------------------------------------
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rlc log " Test 3: Control Register: test force miss bits"
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# use data written in previous tests
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# set fmiss bits in cntrl
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# re-read last 4 words -> 4 forced misses --> hm 110 000
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# clear fmiss bits again
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$cpu cp -wal cntrl \
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-wm [regbld rw11::CNTRL {fmiss 3}] \
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-wa 00000020 -p22 \
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-brm 4 -edata {000020 000022 000024 000026} \
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-wal hm \
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-rm -edata 000060 \
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-wal cntrl \
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-wm 0
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# --------------------------------------------------------------------
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rlc log " Test 4: test full memory (touch (4-7)*2 sections of 16 words"
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# determine memory size in 2^n steps; chunck size is 1/4
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set msize2 [expr {2*1024*1024}]
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while {$msize < $msize2} {
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set msize2 [expr {$msize2 >> 1}]
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}
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set mstep [expr {$msize2 >> 2}]
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set nstep [expr {int($msize / $mstep)}]
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rlc log [format " --> %d chuncks with %4d kB" $nstep [expr {$mstep/1024}]]
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# write data
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set maddrlow 0
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set maddrhigh [expr {$mstep - 32}]
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set clist {}
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for {set i 0} {$i < $nstep} {incr i} {
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set vlist {}
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for {set j 0} {$j < 16} {incr j} { lappend vlist [expr {($i<<9) + ($j<<3)}] }
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lappend clist -wa $maddrlow -p22
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lappend clist -bwm $vlist
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set vlist {}
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for {set j 0} {$j < 16} {incr j} { lappend vlist [expr {($i<<9) + ($j<<3)+1}]}
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lappend clist -wa $maddrhigh -p22
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lappend clist -bwm $vlist
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incr maddrlow $mstep
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incr maddrhigh $mstep
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}
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$cpu cp {*}$clist
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# read data
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set maddrlow 0
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set maddrhigh [expr {$mstep - 32}]
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set clist {}
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for {set i 0} {$i < $nstep} {incr i} {
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set vlist {}
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for {set j 0} {$j < 16} {incr j} { lappend vlist [expr {($i<<9) + ($j<<3)}] }
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lappend clist -wa $maddrlow -p22
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lappend clist -brm 16 -edata $vlist
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set vlist {}
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for {set j 0} {$j < 16} {incr j} { lappend vlist [expr {($i<<9) + ($j<<3)+1}]}
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lappend clist -wa $maddrhigh -p22
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lappend clist -brm 16 -edata $vlist
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incr maddrlow $mstep
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incr maddrhigh $mstep
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}
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$cpu cp {*}$clist
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@@ -1,7 +1,9 @@
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# $Id: w11a_all.dat 831 2016-12-27 16:51:12Z mueller $
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# $Id: w11a_all.dat 916 2017-06-25 13:30:07Z mueller $
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#
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## steering file for all w11a tests
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#
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test_w11a_mem70.tcl
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#
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test_w11a_srcr_word_flow.tcl
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test_w11a_dstw_word_flow.tcl
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test_w11a_dstm_word_flow.tcl
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