mirror of
https://github.com/wfjm/w11.git
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23 line interrupt mapper for full system configuration
This commit is contained in:
Walter F.J. Mueller
@@ -17,6 +17,7 @@ software or firmware builds or that the documentation is consistent.
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The full set of tests is only run for tagged releases._
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### Summary
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- 23 line interrupt mapper now for full system configuration
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- man pages now [available online](http://www.retro11.de/manp/w11/man/cat1/).
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- add `sysmon_rbus` in `sys_tst_sram_n4`
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- Auto-dection of Digilent boards with `FT2232HQ` interface for
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@@ -1,4 +1,4 @@
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-- $Id: ib_intmap.vhd 641 2015-02-01 22:12:15Z mueller $
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-- $Id: ib_intmap.vhd 846 2017-01-29 13:01:59Z mueller $
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--
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-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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@@ -13,12 +13,18 @@
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_intmap - syn
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-- Description: pdp11: external interrupt mapper
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-- Description: pdp11: external interrupt mapper (15 line)
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
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--
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-- Synthesized:
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-- Date Rev viv Target flop lutl lutm bram slic MHz
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-- 2016-05-26 641 2016.4 xc7a100t-1 0 30 0 0 - -
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-- 2015-02-22 641 i 14.7 xc6slx16-2 0 20 0 0 9 -
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2011-11-18 427 1.2.2 now numeric_std clean
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5
rtl/ibus/ib_intmap24.vbom
Normal file
5
rtl/ibus/ib_intmap24.vbom
Normal file
@@ -0,0 +1,5 @@
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# libs
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../vlib/slvtypes.vhd
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iblib.vhd
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# design
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ib_intmap24.vhd
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164
rtl/ibus/ib_intmap24.vhd
Normal file
164
rtl/ibus/ib_intmap24.vhd
Normal file
@@ -0,0 +1,164 @@
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-- $Id: ib_intmap24.vhd 846 2017-01-29 13:01:59Z mueller $
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--
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-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 2, or at your option any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: ib_intmap24 - syn
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-- Description: pdp11: external interrupt mapper (23 line)
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--
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-- Dependencies: -
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-- Test bench: tb/tb_pdp11_core (implicit)
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2016.4; ghdl 0.33
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--
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-- Synthesized:
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-- Date Rev viv Target flop lutl lutm bram slic MHz
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-- 2016-05-26 641 2016.4 xc7a100t-1 0 48 0 0 - -
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-- 2015-02-22 641 i 14.7 xc6slx16-2 0 38 0 0 20 -
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2017-01-28 846 1.0 Initial version (cloned from ib_intmap.vhd)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.iblib.all;
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-- ----------------------------------------------------------------------------
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entity ib_intmap24 is -- external interrupt mapper (23 line)
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generic (
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INTMAP : intmap24_array_type := intmap24_array_init);
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port (
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EI_REQ : in slv24_1; -- interrupt request lines
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EI_ACKM : in slbit; -- interrupt acknowledge (from master)
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EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor)
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EI_PRI : out slv3; -- interrupt priority
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EI_VECT : out slv9_2 -- interrupt vector
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);
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end ib_intmap24;
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architecture syn of ib_intmap24 is
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signal EI_LINE : slv5 := (others=>'0'); -- external interrupt line
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type intp_type is array (23 downto 0) of slv3;
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type intv_type is array (23 downto 0) of slv9;
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constant conf_intp : intp_type :=
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(slv(to_unsigned(INTMAP(23).pri,3)), -- line 23
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slv(to_unsigned(INTMAP(22).pri,3)), -- line 22
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slv(to_unsigned(INTMAP(21).pri,3)), -- line 21
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slv(to_unsigned(INTMAP(20).pri,3)), -- line 20
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slv(to_unsigned(INTMAP(19).pri,3)), -- line 19
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slv(to_unsigned(INTMAP(18).pri,3)), -- line 18
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slv(to_unsigned(INTMAP(17).pri,3)), -- line 17
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slv(to_unsigned(INTMAP(16).pri,3)), -- line 16
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slv(to_unsigned(INTMAP(15).pri,3)), -- line 15
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slv(to_unsigned(INTMAP(14).pri,3)), -- line 14
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slv(to_unsigned(INTMAP(13).pri,3)), -- line 13
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slv(to_unsigned(INTMAP(12).pri,3)), -- line 12
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slv(to_unsigned(INTMAP(11).pri,3)), -- line 11
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slv(to_unsigned(INTMAP(10).pri,3)), -- line 10
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slv(to_unsigned(INTMAP( 9).pri,3)), -- line 9
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slv(to_unsigned(INTMAP( 8).pri,3)), -- line 8
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slv(to_unsigned(INTMAP( 7).pri,3)), -- line 7
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slv(to_unsigned(INTMAP( 6).pri,3)), -- line 6
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slv(to_unsigned(INTMAP( 5).pri,3)), -- line 5
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slv(to_unsigned(INTMAP( 4).pri,3)), -- line 4
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slv(to_unsigned(INTMAP( 3).pri,3)), -- line 3
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slv(to_unsigned(INTMAP( 2).pri,3)), -- line 2
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slv(to_unsigned(INTMAP( 1).pri,3)), -- line 1
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slv(to_unsigned( 0,3)) -- line 0 (always 0 !!)
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);
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constant conf_intv : intv_type :=
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(
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slv(to_unsigned(INTMAP(23).vec,9)), -- line 23
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slv(to_unsigned(INTMAP(22).vec,9)), -- line 22
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slv(to_unsigned(INTMAP(21).vec,9)), -- line 21
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slv(to_unsigned(INTMAP(20).vec,9)), -- line 20
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slv(to_unsigned(INTMAP(19).vec,9)), -- line 19
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slv(to_unsigned(INTMAP(18).vec,9)), -- line 18
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slv(to_unsigned(INTMAP(17).vec,9)), -- line 17
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slv(to_unsigned(INTMAP(16).vec,9)), -- line 16
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slv(to_unsigned(INTMAP(15).vec,9)), -- line 15
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slv(to_unsigned(INTMAP(14).vec,9)), -- line 14
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slv(to_unsigned(INTMAP(13).vec,9)), -- line 13
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slv(to_unsigned(INTMAP(12).vec,9)), -- line 12
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slv(to_unsigned(INTMAP(11).vec,9)), -- line 11
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slv(to_unsigned(INTMAP(10).vec,9)), -- line 10
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slv(to_unsigned(INTMAP( 9).vec,9)), -- line 9
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slv(to_unsigned(INTMAP( 8).vec,9)), -- line 8
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slv(to_unsigned(INTMAP( 7).vec,9)), -- line 7
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slv(to_unsigned(INTMAP( 6).vec,9)), -- line 6
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slv(to_unsigned(INTMAP( 5).vec,9)), -- line 5
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slv(to_unsigned(INTMAP( 4).vec,9)), -- line 4
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slv(to_unsigned(INTMAP( 3).vec,9)), -- line 3
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slv(to_unsigned(INTMAP( 2).vec,9)), -- line 2
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slv(to_unsigned(INTMAP( 1).vec,9)), -- line 1
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slv(to_unsigned( 0,9)) -- line 0 (always 0 !!)
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);
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-- attribute PRIORITY_EXTRACT : string;
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-- attribute PRIORITY_EXTRACT of EI_LINE : signal is "force";
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begin
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EI_LINE <= "10111" when EI_REQ(23)='1' else
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"10110" when EI_REQ(22)='1' else
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"10101" when EI_REQ(21)='1' else
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"10100" when EI_REQ(20)='1' else
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"10011" when EI_REQ(19)='1' else
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"10010" when EI_REQ(18)='1' else
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"10001" when EI_REQ(17)='1' else
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"10000" when EI_REQ(16)='1' else
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"01111" when EI_REQ(15)='1' else
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"01110" when EI_REQ(14)='1' else
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"01101" when EI_REQ(13)='1' else
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"01100" when EI_REQ(12)='1' else
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"01011" when EI_REQ(11)='1' else
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"01010" when EI_REQ(10)='1' else
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"01001" when EI_REQ( 9)='1' else
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"01000" when EI_REQ( 8)='1' else
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"00111" when EI_REQ( 7)='1' else
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"00110" when EI_REQ( 6)='1' else
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"00101" when EI_REQ( 5)='1' else
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"00100" when EI_REQ( 4)='1' else
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"00011" when EI_REQ( 3)='1' else
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"00010" when EI_REQ( 2)='1' else
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"00001" when EI_REQ( 1)='1' else
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"00000";
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proc_intmap : process (EI_LINE, EI_ACKM)
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variable iline : integer := 0;
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variable iei_ack : slv24 := (others=>'0');
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begin
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iline := to_integer(unsigned(EI_LINE));
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iei_ack := (others=>'0');
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if EI_ACKM = '1' then
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iei_ack(iline) := '1';
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end if;
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EI_ACK <= iei_ack(EI_ACK'range);
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EI_PRI <= conf_intp(iline);
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EI_VECT <= conf_intv(iline)(8 downto 2);
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end process proc_intmap;
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end syn;
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@@ -16,6 +16,6 @@ ibdr_lp11.vbom
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ibdr_sdreg.vbom
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ib_sres_or_4.vbom
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ib_sres_or_3.vbom
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ib_intmap.vbom
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ib_intmap24.vbom
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# design
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ibdr_maxisys.vhd
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@@ -1,6 +1,6 @@
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-- $Id: ibdr_maxisys.vhd 683 2015-05-17 21:54:35Z mueller $
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-- $Id: ibdr_maxisys.vhd 846 2017-01-29 13:01:59Z mueller $
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--
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-- Copyright 2009-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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-- Copyright 2009-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
|
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@@ -27,13 +27,16 @@
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-- ibdr_sdreg
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-- ib_sres_or_4
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-- ib_sres_or_3
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-- ib_intmap
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-- ib_intmap24
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-- Test bench: -
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-- Target Devices: generic
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-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
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--
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-- Synthesized (xst):
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-- Synthesized:
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2017-01-28 846 14.7 131013 xc6slx16-2 668 1562 30 577 s 8.5 intmap24
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-- 2017-01-28 683 viv 2016.4 xc7a100t-1 683 1684 48 - -
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-- 2017-01-28 683 14.7 131013 xc6slx16-2 668 1557 30 576 s 8.5 +TM11
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-- 2015-04-06 664 14.7 131013 xc6slx16-2 559 1068 29 410 s 9.1 +RHRP
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-- 2015-01-04 630 14.7 131013 xc6slx16-2 388 761 20 265 s 8.0 +RL11
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-- 2014-06-08 560 14.7 131013 xc6slx16-2 311 615 8 216 s 7.1
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@@ -42,6 +45,7 @@
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--
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-- Revision History:
|
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-- Date Rev Version Comment
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-- 2017-01-28 846 1.4 use ib_intmap24
|
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-- 2015-05-15 683 1.3.1 add TM11
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-- 2015-05-10 678 1.3 start/stop/suspend overhaul
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-- 2015-04-06 664 1.2.3 rename RPRM to RHRP
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@@ -116,9 +120,17 @@ end ibdr_maxisys;
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architecture syn of ibdr_maxisys is
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constant conf_intmap : intmap_array_type :=
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((8#260#,6), -- line 15 IIST
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(8#100#,6), -- line 14 KW11-L
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constant conf_intmap24 : intmap24_array_type :=
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(intmap_init, -- line 23 (unused)
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intmap_init, -- line 22 (unused)
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intmap_init, -- line 21 (unused)
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intmap_init, -- line 20 (unused)
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intmap_init, -- line 19 (unused)
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intmap_init, -- line 18 (unused)
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(8#104#,7), -- line 17 KW11-P
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(8#260#,6), -- line 16 IIST
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(8#100#,6), -- line 15 KW11-L
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(8#120#,5), -- line 14 DENUA
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(8#254#,5), -- line 13 RHRP
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(8#160#,5), -- line 12 RL11
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(8#220#,5), -- line 11 RK11
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@@ -166,8 +178,8 @@ architecture syn of ibdr_maxisys is
|
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signal IB_SRES_3 : ib_sres_type := ib_sres_init;
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signal IB_SRES_4 : ib_sres_type := ib_sres_init;
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signal EI_REQ : slv16_1 := (others=>'0');
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signal EI_ACK : slv16_1 := (others=>'0');
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signal EI_REQ : slv24_1 := (others=>'0');
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signal EI_ACK : slv24_1 := (others=>'0');
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signal EI_REQ_IIST : slbit := '0';
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signal EI_REQ_KW11P : slbit := '0';
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@@ -429,9 +441,9 @@ begin
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IB_SRES_OR => IB_SRES
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);
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INTMAP : ib_intmap
|
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INTMAP : ib_intmap24
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generic map (
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INTMAP => conf_intmap)
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INTMAP => conf_intmap24)
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port map (
|
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EI_REQ => EI_REQ,
|
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EI_ACKM => EI_ACKM,
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@@ -440,8 +452,11 @@ begin
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EI_VECT => EI_VECT
|
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);
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EI_REQ(15) <= EI_REQ_IIST;
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EI_REQ(14) <= EI_REQ_KW11L;
|
||||
EI_REQ(23 downto 18) <= (others=>'0');
|
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EI_REQ(17) <= EI_REQ_KW11P;
|
||||
EI_REQ(16) <= EI_REQ_IIST;
|
||||
EI_REQ(15) <= EI_REQ_KW11L;
|
||||
EI_REQ(14) <= EI_REQ_DEUNA;
|
||||
EI_REQ(13) <= EI_REQ_RHRP;
|
||||
EI_REQ(12) <= EI_REQ_RL11;
|
||||
EI_REQ(11) <= EI_REQ_RK11;
|
||||
@@ -456,8 +471,10 @@ begin
|
||||
EI_REQ( 2) <= EI_REQ_PC11PTP;
|
||||
EI_REQ( 1) <= EI_REQ_LP11;
|
||||
|
||||
EI_ACK_IIST <= EI_ACK(15);
|
||||
EI_ACK_KW11L <= EI_ACK(14);
|
||||
EI_ACK_KW11P <= EI_ACK(17);
|
||||
EI_ACK_IIST <= EI_ACK(16);
|
||||
EI_ACK_KW11L <= EI_ACK(15);
|
||||
EI_ACK_DEUNA <= EI_ACK(14);
|
||||
EI_ACK_RHRP <= EI_ACK(13);
|
||||
EI_ACK_RL11 <= EI_ACK(12);
|
||||
EI_ACK_RK11 <= EI_ACK(11);
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
-- $Id: iblib.vhd 770 2016-05-28 14:15:00Z mueller $
|
||||
-- $Id: iblib.vhd 846 2017-01-29 13:01:59Z mueller $
|
||||
--
|
||||
-- Copyright 2008-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
-- Copyright 2008-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
@@ -16,9 +16,10 @@
|
||||
-- Description: Definitions for ibus interface and bus entities
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.1; ghdl 0.18-0.33
|
||||
-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2017-01-28 846 2.2 add ib_intmap24
|
||||
-- 2016-05-28 770 2.1.1 use type natural for vec,pri fields of intmap_type
|
||||
-- 2015-04-24 668 2.1 add ibd_ibmon
|
||||
-- 2010-10-23 335 2.0.1 add ib_sel; add ib_sres_or_mon
|
||||
@@ -124,7 +125,7 @@ constant intmap_init : intmap_type := (0,0);
|
||||
type intmap_array_type is array (15 downto 0) of intmap_type;
|
||||
constant intmap_array_init : intmap_array_type := (others=>intmap_init);
|
||||
|
||||
component ib_intmap is -- external interrupt mapper
|
||||
component ib_intmap is -- external interrupt mapper (15 line)
|
||||
generic (
|
||||
INTMAP : intmap_array_type := intmap_array_init);
|
||||
port (
|
||||
@@ -136,6 +137,21 @@ component ib_intmap is -- external interrupt mapper
|
||||
);
|
||||
end component;
|
||||
|
||||
type intmap24_array_type is array (23 downto 0) of intmap_type;
|
||||
constant intmap24_array_init : intmap24_array_type := (others=>intmap_init);
|
||||
|
||||
component ib_intmap24 is -- external interrupt mapper (23 line)
|
||||
generic (
|
||||
INTMAP : intmap24_array_type := intmap24_array_init);
|
||||
port (
|
||||
EI_REQ : in slv24_1; -- interrupt request lines
|
||||
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
|
||||
EI_ACK : out slv24_1; -- interrupt acknowledge (to requestor)
|
||||
EI_PRI : out slv3; -- interrupt priority
|
||||
EI_VECT : out slv9_2 -- interrupt vector
|
||||
);
|
||||
end component;
|
||||
|
||||
component ibd_ibmon is -- ibus dev: ibus monitor
|
||||
generic (
|
||||
IB_ADDR : slv16 := slv(to_unsigned(8#160000#,16));
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
-- $Id: sys_w11a_n3.vhd 791 2016-07-21 22:01:10Z mueller $
|
||||
-- $Id: sys_w11a_n3.vhd 846 2017-01-29 13:01:59Z mueller $
|
||||
--
|
||||
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
@@ -34,6 +34,7 @@
|
||||
--
|
||||
-- Synthesized (xst):
|
||||
-- Date Rev ise Target flop lutl lutm slic t peri
|
||||
-- 2017-01-28 846 14.7 131013 xc6slx16-2 2680 5208 177 1843 ok: 80%
|
||||
-- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78%
|
||||
-- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77%
|
||||
-- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75%
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
-- $Id: slvtypes.vhd 641 2015-02-01 22:12:15Z mueller $
|
||||
-- $Id: slvtypes.vhd 846 2017-01-29 13:01:59Z mueller $
|
||||
--
|
||||
-- Copyright 2007-2008 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
-- Copyright 2007-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
|
||||
--
|
||||
-- This program is free software; you may redistribute and/or modify it under
|
||||
-- the terms of the GNU General Public License as published by the Free
|
||||
@@ -20,9 +20,10 @@
|
||||
-- commonly used (n downto 0) vectors
|
||||
--
|
||||
-- Dependencies: -
|
||||
-- Tool versions: ise 8.1-14.7; viv 2014.4; ghdl 0.18-0.31
|
||||
-- Tool versions: ise 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
|
||||
-- Revision History:
|
||||
-- Date Rev Version Comment
|
||||
-- 2017-01-28 846 1.0.5 add slv24_1
|
||||
-- 2008-08-24 162 1.0.4 add slv60 and 64
|
||||
-- 2008-08-22 161 1.0.3 add slvnn_m subtypes from pdp11 package
|
||||
-- 2008-03-24 129 1.0.2 add slv31
|
||||
@@ -75,5 +76,6 @@ package slvtypes is
|
||||
subtype slv16_1 is std_logic_vector(15 downto 1); -- 16 bit word, 1 lsb drop
|
||||
subtype slv18_1 is std_logic_vector(17 downto 1); -- 18 bit word, 1 lsb drop
|
||||
subtype slv22_1 is std_logic_vector(21 downto 1); -- 22 bit word, 1 lsb drop
|
||||
subtype slv24_1 is std_logic_vector(23 downto 1); -- 24 bit word, 1 lsb drop
|
||||
|
||||
end package slvtypes;
|
||||
|
||||
Reference in New Issue
Block a user