mirror of
https://github.com/wfjm/w11.git
synced 2026-02-01 06:33:07 +00:00
update tbench and tcode
- tools/bin/tmuconv: add memory system register names - tools/src - librw11/Rw11Cpu: add kCPUUBMAP - librwxxtpp/RtclRw11Cpu.cpp: use kCPUUBMAP - tools/tbench - cp/cp_all.dat: add test_cp_ubmap.tcl - cp/test_cp_cpubasics.tcl: add creset test - cp/test_cp_gr.tcl: streamline, use longer command chains - cp/test_cp_membasics.tcl: add 22bit mode tests - cp/test_cp_ubmap.tcl: added, test access via ubmap - w11a/test_w11a_dstr_word_flow.tcl: renamed from test_w11a_dstm_word_flow.tcl - w11a/test_w11a_cdma.tcl: added, test bwm/brm with active CPU - w11a/test_w11a_inst_traps.tcl: use defs_cpu.mac include - w11a/test_w11a_inst_wait.tcl: added, tests WAIT instruction - w11a/w11a_all.dat: add test_w11a_inst_wait.tcl, test_w11a_cdma.tcl - tools/tcl/rw11/defs.tcl: add A_UBMAP - tools/tcode - cpu_details.mac: add A5 - cpu_mmu.mac: add F2
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wfjm
@@ -1,10 +1,10 @@
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; $Id: cpu_details.mac 1345 2023-01-04 18:05:42Z mueller $
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; $Id: cpu_details.mac 1346 2023-01-06 12:56:08Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2023-01-04 1345 1.0 Initial version
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; 2023-01-06 1346 1.0 Initial version
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; 2022-07-18 1259 0.1 First draft
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;
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; Test CPU details
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@@ -98,6 +98,7 @@
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; part 8: traced RTI that clears tbit
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; part 9: EMT that sets tbit
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; part 10: PIRQ that sets tbit
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; A5 MBRK
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;
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; Test A1: PIRQ +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; This sub-section verifies operation of PIRQ register
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@@ -1534,6 +1535,23 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler
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;
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9999$: iot ; end of test A4.4
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;
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; Test A5: MBRK +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Test A5.1 -- MBRK direct write/read test +++++++++++++++++++++++++++
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; MBRK is a writable and readable 8 bit register an has no specific
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; function in w11.
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;
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ta0501: mov #cp.mbr,r0
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clr (r0)
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htsteq (r0)
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mov #177777,(r0) ; test word write
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hcmpeq #377,(r0)
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movb #123,(r0) ; write low byte
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hcmpeq #123,(r0)
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movb #321,1(r0) ; write high byte (no effect)
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hcmpeq #123,(r0)
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;
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9999$: iot ; end of test A5.1
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;
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; Section B: Stress and flow tests ===========================================
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; B1 address mode torture tests
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; B1.1 src-dst update hazards with (r0)+,(r0)
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@@ -2133,7 +2151,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#38. ; all tests done ?
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hcmpeq tstno,#39. ; all tests done ?
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;
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jmp loop
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;
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@@ -1,10 +1,10 @@
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; $Id: cpu_mmu.mac 1345 2023-01-04 18:05:42Z mueller $
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; $Id: cpu_mmu.mac 1346 2023-01-06 12:56:08Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2023-01-04 1345 1.0 Initial version
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; 2023-01-05 1346 1.0 Initial version
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; 2022-07-24 1262 0.1 First draft
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;
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; Test CPU MMU: all aspects of the MMU
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@@ -53,8 +53,11 @@
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kipdr0 = kipdr+ 0
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kipar0 = kipar+ 0
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kdpdr0 = kdpdr+ 0
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kdpar0 = kdpar+ 0
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kipdr1 = kipdr+ 2
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kipar1 = kipar+ 2
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kdpdr1 = kdpdr+ 2
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kdpar1 = kdpar+ 2
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kipdr5 = kipdr+12
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kipdr6 = kipdr+14
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kipar6 = kipar+14
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@@ -62,6 +65,8 @@
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kdpar6 = kdpar+14
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kipdr7 = kipdr+16
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kipar7 = kipar+16
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kdpdr7 = kdpdr+16
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kdpar7 = kdpar+16
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p0p1p2 = <1*100>+2 ; page 0, +1 click, +2
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p0p1p4 = <1*100>+4 ; page 0, +1 click, +4
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@@ -2514,8 +2519,10 @@ te0201: mov #m0.ent!m0.ena,mmr0 ; enable mmu with traps ;! MMU 18
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clr v..pir+2
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;
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; Section F: miscellaneous ===================================================
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; F1.1 test D-to-I mapping for (PC) address modes I
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; F1.2 test D-to-I mapping for (PC) address modes II
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; F1 test D-to-I mapping
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; F1.1 for (PC) address modes I
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; F1.2 for (PC) address modes II
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; F2 test LOSIZE register and access to full memory
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;
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; Test F1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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;
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@@ -2624,11 +2631,66 @@ tf0102: mov #154345,@#p6base ; inititialize target
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;
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9999$: iot ; end of test F1.2
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;
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; Summary
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; Test F2: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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;
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; Test F2.1 -- test LOSIZE register and access to full memory ++++++++
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; Read memory size from LOSIZE, write one word every 64 kB and read back.
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; Quite fast: at most 60 words (4M-256k)/64k.
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; Tests runs with kernel D space enabled (an exception!)
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;
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tf0201: mov kipdr0,kdpdr0 ; set up kernel D space 1-to-1 mapping
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mov kipar0,kdpar0
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mov kipdr1,kdpdr1
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mov kipar1,kdpar1
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mov kipdr6,kdpdr6
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mov kipar6,kdpar6
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mov kipdr7,kdpdr7
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mov kipar7,kdpar7
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mov #m3.e22!m3.dkm,mmr3 ; enable D space for kernel; 22 bit
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 22
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;
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htsteq hisize ; HISIZE must be zero
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mov losize,r0 ; last accessible click (64B)
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inc r0
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ccc
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ror r0 ; shift right 10 bits, no sign extend
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ash #-9.,r0 ; memory size in 64 kB chunks
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dec r0 ; number of chunks to test
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ble 2000$ ; quit if memory too small
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mov #2000,r1 ; step size 64kB in clicks
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mov #kdpar6,r2 ; ptr to kdpar6
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mov #p6base,r3 ; ptr to write/read test location
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; write memory
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mov r0,r4 ; initialize counter
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mov r1,r5 ; initialize current par
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100$: mov r5,(r2) ; set par
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mov r5,(r3) ; write data
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add r1,r5 ; bump pointer
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sob r4,100$
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; read memory
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mov r0,r4 ; initialize counter
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mov r1,r5 ; initialize current par
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200$: mov r5,(r2) ; set par
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hcmpeq r5,(r3) ; check data
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add r1,r5 ; bump pointer
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sob r4,200$
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;
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2000$: reset ; mmu off ;! MMU off
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clr kdpdr0
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clr kdpar0
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clr kdpdr1
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clr kdpar1
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clr kdpdr6
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clr kdpar6
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clr kdpdr7
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clr kdpar7
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;
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9999$: iot ; end of test F2.1
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;
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#32. ; all tests done ?
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hcmpeq tstno,#33. ; all tests done ?
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call chkpdr ; kernel pdr/par OK ?
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;
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jmp loop
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