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cpu_eis.mac: add MUL,DIV odd, XOR

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wfjm
2022-07-21 08:10:47 +02:00
parent c14eddd0b1
commit e1a577f26e
4 changed files with 269 additions and 8 deletions
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12
rtl/w11a/tb/tb_pdp11core_stim.dat
View File

@@ -1,4 +1,4 @@
# $Id: tb_pdp11core_stim.dat 1257 2022-07-16 21:49:08Z mueller $
# $Id: tb_pdp11core_stim.dat 1259 2022-07-18 17:39:40Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -794,6 +794,7 @@ brm 7
d=000170 -- ! mem(3174)=170
#-----------------------------------------------------------------------------
C Setup code 12 [base 3300; use 33-34] (PSW access via sex,clx,spl,mov, and clr)
# ==> now tested with cpu_basics.mac:A1.1, cpu_basics.mac:F1.*
#
wal 003300 -- code:
bwm 23
@@ -2258,6 +2259,7 @@ brm 14
#
#-----------------------------------------------------------------------------
C Setup code 24 [base 6400] (test MARK instruction)
# ==> now tested with cpu_basics.mac:A5.*
#
wal 006400 -- code (main):
bwm 13
@@ -2850,6 +2852,7 @@ brm 6
d=100100 -- ! mem(7752)
#-----------------------------------------------------------------------------
C Setup code 30 [base 10200; use 102-103] (test MUL instruction)
# ==> now tested with cpu_eis.mac:B1.1
#
wal 010200 -- code test 1 (mul even)
bwm 8
@@ -2972,6 +2975,7 @@ brm 8
C Setup code 31 [base 10400; use 104-110] (test DIV instruction, also ADC,SXT)
# Note: test 2 uses sbc too, but if div/div work correctly we have always
# C=0 for sbc, so sbc isn't tested. adc has C=0 or C=1 though.
# ==> now tested with cpu_eis.mac:B1.2
#
wal 010400 -- code test 1
bwm 8
@@ -3214,6 +3218,7 @@ rr5 d=000000 -- ! r5
rpc d=010500 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 32 [base 11100; use 111-112] (PIRQ test)
# ==> now tested with cpu_details.mac:B1.*
# The code will exercise all 7 pirq interrupt levels:
# set 1+3 -> handle 3, set 7 -> handle 7, set 6+4 -> handle 6
# -> handle 4, set 5+2 -> handle 5 -> handle 2 > handle 1
@@ -3325,6 +3330,7 @@ bwm 2
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 33 [base 11200; use 112-113] (adc(b) and sbc(b) test)
# ==> obsolete, fully tested in cpu_basics.mac:B5,B6,D5,D6
#
wal 011200 -- code test 1: (adc)
bwm 5
@@ -5147,6 +5153,8 @@ brm 110
#-----------------------------------------------------------------------------
C Setup code 43 [base 12700] (Begemot MARK instruction test)
# test data and code adapted from Mark.s11 code of Begemot p11-2.10c
# ==> now tested with cpu_basics.mac:A5.*
# ==> partialy redundant with code 24, not need to go deeper for this bastard
#
wal 012700 -- code test 1: (basics)
bwm 14
@@ -6975,6 +6983,7 @@ brm 12
d=110000 -- !
#--------
C Exec test 46.16wrc0: XOR - reg, C=0
# ==> now tested with cpu_eis.mac:E1.1
#
wal 013246 -- setup test instructions:
bwm 2
@@ -7008,6 +7017,7 @@ brm 12
d=000000 -- !
#--------
C Exec test 46.16wrc1: XOR - reg, C=1
# ==> now tested with cpu_eis.mac:E1.1
#
wal 013246 -- setup test instructions:
bwm 2

12
tools/tcode/cpu_badinst_nofpp.mac
View File

@@ -1,4 +1,4 @@
; $Id: cpu_badinst_nofpp.mac 1257 2022-07-16 21:49:08Z mueller $
; $Id: cpu_badinst_nofpp.mac 1258 2022-07-18 10:07:22Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
@@ -101,7 +101,11 @@ ta0103: mov #vh.exp,v..rit ; setup iit handler
halt
.word 007777
halt
.word 075000 ; 075000-075777
.word 075000 ; 075000-075037 {FIS in 11/40}
halt
.word 075037
halt
.word 075040 ; 075040-075777
halt
.word 075777
halt
@@ -127,7 +131,7 @@ ta0103: mov #vh.exp,v..rit ; setup iit handler
halt
;
mov #v..rit+2,v..rit ; restore iit catcher
cmp trpcnt,#27.
cmp trpcnt,#29.
beq .+4
halt
;
@@ -154,3 +158,5 @@ ta0104: mov #vh.exp,v..rit ; setup iit handler
; END OF ALL TESTS - loop closure --------------------------------------------
;
jmp loop
;
.end start

249
tools/tcode/cpu_eis.mac
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@@ -1,4 +1,4 @@
; $Id: cpu_eis.mac 1257 2022-07-16 21:49:08Z mueller $
; $Id: cpu_eis.mac 1259 2022-07-18 17:39:40Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
@@ -282,9 +282,180 @@ ta0102: mov #1000$,r5
.word 0137777,0177777, -32768., cp00v0, -16385., -1.;dd=-1073741825
;
1011$:
;
9999$: iot ; end of test A1.2
;
;
; Test A1.3 -- div odd register +++++++++++++++++++++++++++++++++++++++
; check div odd register behavior
; Note: The div instruction has, in contrast to ashc, no useful semantics when
; called with an odd register. DEC documentation doesn't specify the
; behavior. SimH assumes, that register handling is done like for ashc,
; so effective dd is 'R<<16 | R' and reminder is stored. w11 implements
; div like this. This test briefly verifies this behavior.
ta0103: mov #1000$,r4 ; setup data pointer
mov #1010$,r5 ; setup end pointer
mov #cp.psw,r3 ; setup psw pointer
clr r0 ; for tmu optics
100$: mov (r4)+,r1 ; load dd
div (r4)+,r1 ; div
cmp (r4)+,(r3) ; check psw
beq .+4
halt
cmp (r4)+,r1 ; check res (reminder)
beq .+4
halt
cmp r4,r5
blo 100$
jmp 9999$
;
; dd, dr, psw, res ;
1000$: .word 000000, 1., cp0z00, 000000 ; h: 000000
.word 000007, 16., cp0000, 000007 ; 458759/16: 28672, 7 h: 070000
.word 000007, 17., cp0000, 000016 ; 458759/17: 26985,14 h: 064551
.word 000007, 19., cp0000, 000004 ; 458759/19: 24145, 4 h: 057121
.word 000007, 15., cp0000, 000016 ; 458759/15: 30583,14 h: 073567
1010$:
;
9999$: iot ; end of test A1.3
;
; Section B: mul =============================================================
; This section verifies
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
; 0 111 000 rrr sss sss NZ0C MUL
;
; Test B1.1 -- mul even and odd ++++++++++++++++++++++++++++++++++++++
; check that mul works with even and odd destination register
;
jmp tb0101
;
; driver for mul even tests
;
tbmule: mov #cp.psw,r3 ; setup psw pointer
100$: mov (r4)+,r0 ; load f1
mul (r4)+,r0 ; mul
cmp (r4)+,(r3) ; check psw
beq .+4
halt
cmp (r4)+,r0 ; check p_high
beq .+4
halt
cmp (r4)+,r1 ; check p_low
beq .+4
halt
cmp r4,r5
blo 100$
rts pc
;
; driver for mul odd tests
;
tbmulo: mov #cp.psw,r3 ; setup psw pointer
100$: mov (r4)+,r1 ; load f1
mul (r4)+,r1 ; mul
cmp (r4)+,(r3) ; check psw
beq .+4
halt
tst (r4)+ ; skip p_high
cmp (r4)+,r1 ; check p_low
beq .+4
halt
cmp r4,r5
blo 100$
rts pc
;
tb0101: mov #1000$,r4 ; setup data pointer
mov #1010$,r5 ; setup end pointer
jsr pc,tbmule ; test even
;
mov #1000$,r4 ; setup data pointer
mov #1010$,r5 ; setup end pointer
jsr pc,tbmulo ; test odd
;
jmp 9999$
;
; fx, f2, psw, ph, pl ;
1000$: .word 0., 0., cp0z00, 0, 0 ; p = 0.
.word 0., 1., cp0z00, 0, 0 ; p = 0.
.word 0., -1., cp0z00, 0, 0 ; p = 0.
.word 1., 0., cp0z00, 0, 0 ; p = 0.
.word 1., 1., cp0000, 0, 1 ; p = 1.
.word 1., -1., cpn000, 177777, 177777 ; p = -1.
.word -1., 0., cp0z00, 0, 0 ; p = 0.
.word -1., 1., cpn000, 177777, 177777 ; p = -1.
.word -1., -1., cp0000, 0, 1 ; p = 1.
.word 181., 181., cp0000, 0, 077771 ; p = 32761.
.word 181., 182., cp000c, 0, 100256 ; p = 32942.
.word 181., -182., cpn00c, 177777, 077522 ; p = -32942.
.word 31022., 9562., cp000c, 010656, 040054 ; p = 296632364.
.word 18494.,-24041., cpn00c, 162577, 134622 ; p =-444614254.
.word -12549., 2397., cpn00c, 177065, 002057 ; p = -30079953.
.word -20493.,-23858., cp000c, 016444, 055612 ; p = 488921994.
1010$:
;
9999$: iot ; end of test B1.1
;
; Test B1.2 -- mul+div (and adc,adc,sxt) +++++++++++++++++++++++++++++
; combined div and mul test
;
tb0102: mov #1000$,r4 ; setup data pointer
mov #1010$,r5 ; setup end pointer
;
100$: mov (r4)+,r0 ; load divident high
mov (r4)+,r1 ; load divident low
div (r4)+,r0 ; divide by divisor
mov r0,r2 ; get quotient
mul -2(r4),r2 ; multiply with divisor
add r1,r3 ; add reminder on p_low
adc r2 ; propagate carry to p_high
tst r1 ; sign extend reminder
sxt r1
add r1,r2 ; and add to p_high
cmp -4(r4),r3 ; check p_low against divident low
beq .+4
halt
cmp -6(r4),r2 ; check p_high against divident high
beq .+4
halt
cmp r4,r5
blo 100$
jmp 9999$
;
; ddh ddl dr
1000$: .word 0, 0, 0
.word 0, 1, 3
.word 0, 2, 3
.word 0, 3, 3
.word 0, 4, 3
.word -1, -1, 3
.word -1, -2, 3
.word -1, -3, 3
.word -1, -4, 3
.word 0, 0, -3
.word 0, 1, -3
.word 0, 2, -3
.word 0, 3, -3
.word 0, 4, -3
.word -1, -1, -3
.word -1, -2, -3
.word -1, -3, -3
.word -1, -4, -3
.word 010656, 040054, 9562. ; dd = 296632364.
.word 010656, 040053, 9562. ; dd = 296632363.
.word 010656, 040055, 9562. ; dd = 296632365.
.word 010656, 040054, -9562. ; dd = 296632364.
.word 010656, 040053, -9562. ; dd = 296632363.
.word 010656, 040055, -9562. ; dd = 296632365.
.word 162577, 134622, 24041. ; dd = -444614254.
.word 162577, 134621, 24041. ; dd = -444614255.
.word 162577, 134623, 24041. ; dd = -444614253.
.word 162577, 134622,-24041. ; dd = -444614254.
.word 162577, 134621,-24041. ; dd = -444614255.
.word 162577, 134623,-24041. ; dd = -444614253.
1010$:
;
9999$: iot ; end of test B1.2
;
; Section C: ash =============================================================
; This section verifies
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
@@ -507,11 +678,83 @@ td0102: mov #1000$,r4 ; setup data pointer
;
9999$: iot ; end of test D1.2
;
; Section E: xor =============================================================
; This section verifies
; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
; 0 111 100 rrr ddd ddd NZ0- XOR
;
; Test E1.1 -- xor znvc=0 ++++++++++++++++++++++++++++++++++++++++++++
; check xor with all cc's cleared; memory destination
;
te0101: mov #1000$,r4 ; setup data pointer
mov #1010$,r5 ; setup end pointer
mov #cp.psw,r3 ; setup psw pointer
mov #200$,r1 ; setup dst pointer
100$: mov (r4)+,r0 ; load src
mov (r4)+,(r1) ; load dst
ccc ; nzvc=0
xor r0,(r1) ; xor
cmp (r4)+,(r3) ; check psw
beq .+4
halt
cmp (r4)+,(r1) ; check
beq .+4
halt
cmp r4,r5
blo 100$
jmp 9999$
;
200$: .word 0
;
; dst, src, psw, res
1000$: .word 000000, 000000, cp0z00, 000000
.word 000011, 000000, cp0000, 000011
.word 000011, 000110, cp0000, 000101
.word 000011, 001100, cp0000, 001111
.word 110000, 011000, cpn000, 101000
.word 110000, 110000, cp0z00, 000000
1010$:
;
9999$: iot ; end of test E1.1
;
; Test X1.2 -- xor znvc=1 ++++++++++++++++++++++++++++++++++++++++++++
; check xor with all cc's set; register destination
;
te0102: mov #1000$,r4 ; setup data pointer
mov #1010$,r5 ; setup end pointer
mov #cp.psw,r3 ; setup psw pointer
100$: mov (r4)+,r0 ; load src
mov (r4)+,r1 ; load dst
scc ; nzvc=1
xor r0,r1 ; xor
cmp (r4)+,(r3) ; check psw
beq .+4
halt
cmp (r4)+,r1 ; check
beq .+4
halt
cmp r4,r5
blo 100$
jmp 9999$
;
; dst, src, psw, res
1000$: .word 000000, 000000, cp0z0c, 000000
.word 000011, 000000, cp000c, 000011
.word 000011, 000110, cp000c, 000101
.word 000011, 001100, cp000c, 001111
.word 110000, 011000, cpn00c, 101000
.word 110000, 110000, cp0z0c, 000000
1010$:
;
9999$: iot ; end of test E1.2
;
; END OF ALL TESTS - loop closure ============================================
;
mov tstno,r0 ; hack, for easy monitoring ...
cmp tstno,#5. ; all tests done ?
cmp tstno,#10. ; all tests done ?
beq .+4
halt
;
jmp loop
;
.end start

4
tools/tcode/cpu_selftest.mac
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@@ -1,4 +1,4 @@
; $Id: cpu_selftest.mac 1254 2022-07-13 06:16:19Z mueller $
; $Id: cpu_selftest.mac 1258 2022-07-18 10:07:22Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
@@ -213,3 +213,5 @@ ta0201:
; END OF ALL TESTS - loop closure --------------------------------------------
;
jmp loop
;
.end start