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Code Issues Releases Wiki Activity

- Add Arty support (BRAM only)

Browse Source 
- Add sysmon/xadc support (for nexys4,basys3,arty designs)
- Add Vivado simulator support (DPI not yet working)
This commit is contained in:
Walter F.J. Mueller
2016-03-19 15:45:59 +00:00
parent 677773d123
commit e1479d4e5d
406 changed files with 8253 additions and 1509 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
.cvsignore
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@@ -1,6 +1,7 @@
*.dep_ghdl
*.dep_isim
*.dep_xst
*.gz
*.tar
*.tgz
*.dep_*
work-obj93.cf
*.vcd
*.ghw
@@ -14,20 +15,28 @@ xflow.his
*.pcf
*.bit
*.msk
*.svf
*.log
isim
isim.log
isim.wdb
fuse.log
*_[sft]sim.vhd
*_[sfot]sim.vhd
*_tsim.sdf
*_xst.log
*_tra.log
*_twr.log
*_map.log
*_par.log
*_tsi.log
*_pad.log
*_bgn.log
*_svn.log
*_sum.log
*_[dsft]sim.log
rlink_cext_fifo_[rt]x
rlink_cext_conf
tmu_ofile
*.dsk
*.tap
*.lst
*.cof
.Xil
project_mflow
xsim.dir
webtalk_*
*_[sfot]sim
*_[IX]Sim
*_[IX]Sim_[sfot]sim
*.dcp
*.jou
*.pb
*.prj
*.rpt
*.wdb

17
Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 682 2015-05-15 18:35:29Z mueller $
# $Id: Makefile 745 2016-03-18 22:10:34Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -6,6 +6,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2016-02-19 732 1.2.1 remove dispunit syn and sim entries
# 2015-02-01 640 1.2 add vivado targets, separate from ise targets
# 2015-01-25 638 1.1 drop as type fx2 targets
# 2014-06-14 562 1.0.8 suspend nexys4 syn targets
@@ -47,8 +48,6 @@ SYN_ise += rtl/sys_gen/tst_serloop/nexys3
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3
SYN_ise += rtl/sys_gen/w11a/nexys3
# xc2 ----------------------------------------
# Vivado based targets, by board type --------------------
# Basys3 -------------------------------------
SYN_viv += rtl/sys_gen/tst_snhumanio/basys3
@@ -62,6 +61,10 @@ SYN_viv += rtl/sys_gen/tst_serloop/nexys4
SYN_viv += rtl/sys_gen/tst_snhumanio/nexys4
SYN_viv += rtl/sys_gen/w11a/nexys4
# Arty ---------------------------------------
SYN_viv += rtl/sys_gen/tst_rlink/arty
SYN_viv += rtl/sys_gen/w11a/arty_bram
# Simulation targets -------------------------------------------------
# ISE flow -----------------------------------------------
@@ -89,17 +92,21 @@ SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_ise += rtl/sys_gen/w11a/nexys3/tb
# xc2 ----------------------------------------
# Vivado flow --------------------------------------------
# Basys3 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb
#SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb
SIM_viv += rtl/sys_gen/w11a/basys3/tb
# Nexys4 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/nexys4/tb
SIM_viv += rtl/sys_gen/tst_serloop/nexys4/tb
SIM_viv += rtl/sys_gen/w11a/nexys4/tb
# Arty ---------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/arty/tb
SIM_viv += rtl/sys_gen/w11a/arty_bram/tb
#
.PHONY : default
.PHONY : all all_ise all_viv

46
doc/ECO-027-trap_mmu.txt Normal file
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@@ -0,0 +1,46 @@
$Id: ECO-027-trap_mmu.txt 708 2015-08-03 06:41:43Z mueller $
Scope:
Introduced in release w11a_V0.71
Affects: all w11a systems
Symptom summary:
A mmu trap could be lost or vectored through 014 (bpt) rather 250 (mmu).
Background:
The PDP-11/70 and 11/45 MMU offers a 'mmu trap' feature, which can cause
a trap when a memory location is read or written. This can be enabled with
special ACF values in the page descriptor registers for each segment end
globally enabled with an enable bit in SSR0.
Since only 11/70 and 11/45 offer this (and J11 does not) this feature is
in general not used by operations systems.
Summary of issues:
When an instruction does more than one memory access and the mmu trap
condition occurs not on the last access
- an mmu trap could be missed
- an mmu trap might be vectored through 014 (the bpt vector)
The later happens for all read-modify-write accesses.
Analysis:
The VM_STAT.trap_mmu flag was copied into the R_STATUS.trap_mmu state bit
in do_memcheck, which is called for each memory wait. In case of a
read-modify-write the initial read will signal trap_mmu, while the
rmw completion will not (the mmu doesn't check on rmw completions).
This leads to
- lost mmu traps (e.g. when mmu trap comes on 1st of 2 access)
- mmu traps vectored through 014 (the bpt vector)
The later happens due to the logic of state s_opg_gen_rmw_w:
- do_memcheck can clear R_STATUS.trap_mmu
- do_fork_next still branches to s_trap_disp because R_STATUS.trap_mmu='1'
- s_trap_disp sees R_STATUS.trap_mmu='0' and miscalculates the vector
Fixes:
pdp11_sequencer was modified to ensure that R_STATUS.trap_mmu is only set
in do_memcheck. Same for trap_ysv (which had the same potential bug)
Provisos:
The issue was found by systematic testing of mmu fault and trap behavior.
Because known OS don't use mmu traps the issue should not have any impact
on practical usage with OS like rsx or 211bsd.

104
doc/README.txt
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@@ -1,4 +1,4 @@
$Id: README.txt 722 2015-12-30 19:45:46Z mueller $
$Id: README.txt 746 2016-03-19 13:08:36Z mueller $
Release notes for w11a
@@ -22,6 +22,108 @@ Release notes for w11a
2. Change Log ----------------------------------------------------------------
- trunk (2016-03-19: svn rev 35(oc) 746(wfjm); untagged w11a_V0.72) +++++++++
- Preface
- The new low-cost Digilent Arty board is a very attractive platform.
The DDR3 memory will take some time to integrate, in this release thus
only designs using the BRAMs.
- added support for the Vivado simulator. Simple test benches work fine.
Rlink based test benches don't work due to a bug in Vivado 2015.4.
- A rather esoteric CPU bug was fixed in release V0.71 but forgotten to
mention in the README. See ECO-027-trap_mmu.txt for details.
- Summary
- added Arty support. The w11a design uses BRAMs as memory, like the
Basys3 version. This gives 176 KByte memory, not enough for 2.11BSD,
but for many other less demanding OS available for a PDP11.
- added support for SYSMON/XADC (see README_xadc.txt)
- Vivado flow is now default for test benches of components and all Artix
based systems. If applicable an ISE flow is available under Makefile.ise
(resolves known issues V0.64-4 and V0.64-5).
- re-factored tbcore_rlink to support DPI and VHPI
- Vivado supports with DPI (from SystemVerilog) a mechanism to call
external C code. The rlink test bench code so far relies on VHPI, which
is supported by ghdl, but not by ISE ISim or Vivado xsim. The code was
restructured and can use now DPI or VHPI to support both ghdl and
Vivado. Unfortunately has Vivado 2015.4 a bug, DPI doesn't work in a
mixed vhdl-verilog language environment (see Known issues), so the
code base is there, but utilization will habe to wait.
- Vivado synthesis by default keeps hierarchy. This leads to doubly defined
modules if a component is used in both test bench and unit under test.
To avoid this copies of s7_cmt_sfs and some serport_* modules were
created and are now used in the test benches.
- New features
- new directory trees for
- rtl/bplib/arty - board support files for arty
- rtl/bplib/sysmon - driver + rbus iface for SYSMON/XADC
- rtl/vlib/rlink/tbcore - new location for rlink tb iface code
- tools/tcl/rbsysmon - sysmon/xadc support
- new modules
- rtl/bplib/bpgen
- rgbdrv_* - driver + rbus iface for 3 color RGBLED
- rtl/vlib/rlink/tbcore
- rlink_cext_iface_dpi.sv - DPI based cext iface
- rlink_cext_iface_vhpi.vhd - VHPI based cext iface
- rlink_cext_dpi.c - dpi to vhpi adapter
- rtl/vlib/serport/tb
- serport_uart_*_tb - added copies for tb usage
- rtl/vlib/xlib/tb
- s7_cmt_sfs_tb - added copy for tb usage
-
- new files
- doc/man/man1
- tbrun_tbw.1 - man file for tbrun_tbw
- tbrun_tbwrri.1 - man file for tbrun_tbwrri
- new systems
- rtl/sys_gen/tst_rlink - rlink tester
- arty/sys_tst_rlink_arty - for Arty
- rtl/sys_gen/w11a - w11a
- arty_bram/sys_w11a_br_arty - for Arty (BRAM only, 176 MByte)
- Changes
- */.cvsignore - all ignore files re-organized
- */tb/Makefile - Vivado now default, keep Makefile.ise
- rtl/bplib/*/tb/tb_*.vhd - use s7_cmt_sfs_tb and serport_master_tb
- rtl/vlib/comlib
- comlib.vhd - add work-around for vivado 2015.4 issue
- rtl/vlib/rbus
- rb_sres_or_mon - supports 6 inputs now
- rtl/vlib/serport
- serport_master - moved to tb, _tb appended to name
- rtl/vlib/rlink/tbcore
- tbcore_rlink - re-structured to use rlink_cext_iface
- rtl/sys_gen/...
- sys_tst_rlink_b3 - hardwire XON=1, support XADC
- sys_tst_rlink_n4 - support XADC and RGBLEDs
- sys_w11a_b3 - hardwire XON=1, support XADC; 72 MHz now
- sys_w11a_n4 - support XADC
- tools/bin
- tbrun_tbw - add vivado xsim and Makefile.ise support
- tbrun_tbwrri - use --sxon and --hxon instead of --xon
- tbw - add XSim support
- ti_w11 - add arty support, add -fx
- vbomconv - add [ise,viv]; add @uut tag handling;
add preliminary --(vsyn|vsim)_export;
add vivado xsim support;
- xtwi,xtwv - add BARE_PATH to provide clean environment
- Bug fixes
- tools/tcl/rutil
- regdsc.tcl - regdsc: fix variable name in error msg
- Known issues
- all issues: see README_known_issues.txt
- resolved issues:
- V0.64-4: support added for Vivado xsim. See however issue V0.72-1+2.
- V0.64-5: w11a_tb_guide.txt covers xsim tests too.
- new issues:
- V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied
vhdl-verilog language environment. This prevents currently to
build a xsim simulation model for rlink based test benches.
- V0.72-2: xsim simulations with timing annotation not yet available.
- trunk (2015-12-30: svn rev 34(oc) 722(wfjm); untagged w11a_V0.71) +++++++++
- Preface
- the w11a so far lacked any 'hardware debugger' support, which made the

25
doc/README_buildsystem_Vivado.txt
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@@ -1,4 +1,4 @@
# $Id: README_buildsystem_Vivado.txt 651 2015-02-26 21:32:15Z mueller $
# $Id: README_buildsystem_Vivado.txt 745 2016-03-18 22:10:34Z mueller $
Guide to the Build System (Xilinx Vivado Version)
@@ -10,6 +10,7 @@ Guide to the Build System (Xilinx Vivado Version)
b. Compile UNISIM/UNIMACRO libraries for ghdl
3. Building test benches
a. With ghdl
b. With Vivado xsim
4. Building systems
5. Configuring FPGAs (via make flow)
6. Note on ISE
@@ -127,6 +128,28 @@ Guide to the Build System (Xilinx Vivado Version)
- post synthesis or optimize models currently very often fail to compile
in ghdl due to a bug in the ghdl code generator.
3b. With Vivado xsim -------------------------------------------------
To compile a Vivado xsim based test bench named <tbench> all is needed is
make <tbench>_XSim
The make file will use <tbench>.vbom, create all make dependency files,
and generate the needed Vivado xsim project files and commands.
In many cases the test benches can also be compiled against the gate
level models derived after the synthesis, optimize or routing step.
make <tbench>_XSim_ssim # for post-synthesis
make <tbench>_XSim_osim # for post-optimize
make <tbench>_XSim_tsim # for post-routing
Notes:
- xsim currently (as of Vivado 2015.4) crashes when DPI is used in a mixed
vhdl verilog context.
Since DPI is used in the rlink simulation all system test benches with
an rlink interface, thus most, will only run with ghdl and not with XSim.
4. Building systems -------------------------------------------------------
To generate a bit file for a system named <sys> all is needed is

10
doc/README_known_issues.txt
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@@ -1,8 +1,13 @@
$Id: README_known_issues.txt 693 2015-06-21 14:02:46Z mueller $
$Id: README_known_issues.txt 746 2016-03-19 13:08:36Z mueller $
Known issues for this release.
The case id indicates the release when the issue was first recognized.
- V0.72-2: xsim simulations with timing annotation not yet available.
- V0.72-1: Vivado 2015.4 xelab crashes when DPI is used in a mxied vhdl-verilog
language environment. This prevents currently to build a xsim simulation
model for rlink based test benches.
- V0.66-1: the TM11 controller transfers data byte wise (all disk do it 16bit
word wise) and allows for odd byte length transfers. Odd length transfers
are currently not supported and rejected as invalid command. Odd byte
@@ -24,9 +29,6 @@ The case id indicates the release when the issue was first recognized.
flow control issue (likely since V0.63).
- V0.64-6: IO delays still unconstraint in vivado. All critical IOs use
explicitly IOB flops, thus timing well defined.
- V0.64-5: w11a_tb_guide.txt covers only ISE based tests (see also V0.64-4).
- V0.64-4: No support for the Vivado simulator (xsim) yet. With ghdl only
functional simulations, post synthesis (_ssim) fails to compile.
- V0.64-3: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud is
not supported according to FTDI, but works. 12 MBaud in an upcoming release.
- V0.64-2: rlink throughput on basys3/nexys4 limited by serial port stack

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doc/README_xadc.txt Normal file
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@@ -0,0 +1,49 @@
# $Id: README_xadc.txt 746 2016-03-19 13:08:36Z mueller $
The Artix-7 based designs contain now a module which makes the data of the
FPGA system monitor, called XADC in 7Series and SYSMON otherwise, available
on the rbus and therefore from ti_rri.
To set this up in ti_rri or ti_w11 use
package require rbsysmon
rbsysmon::setup_xadc_arty; # for arty
rbsysmon::setup_xadc_base; # for b3,n4
Two procedures allow to read and nicely print the XADC data
rbsysmon::print
--> gives on an Arty for example
Value cur val min val max val low lim high lim alarm
temp 34.3 d 30.8 36.0 60.0 85.0
Vccint 0.948 V 0.944 0.953 0.920 0.980
Vccaux 1.799 V 1.787 1.802 1.710 1.890
Vccbram 0.948 V 0.944 0.954 0.920 0.980
V 5V0 4.978 V
V VU 0.088 V
A 5V0 0.173 A
A 0V95 0.087 A
rbsysmon::print_raw
--> produces a full list of all defined registers, like
name description : hex other
sm.temp cur temp : 9a50 30.6 deg
sm.vint cur Vccint : 50ce 0.947 V
sm.vaux cur Vccaux : 9962 1.797 V
sm.vrefp cur Vrefp : 0000 0.000 V
....
sm.flag flag reg : 0000 0000000000000000
sm.conf0 conf 0 : 9000 1001000000000000
sm.conf1 conf 1 : 2ef0 0010111011110000
sm.conf2 conf 2 : 0400 0000010000000000
....
For simulation proper setup files are included and activated by tbw to that
one sees in simulation nominal readings for the power monitor values. To
test this do for example
cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb
make
ti_rri --fifo=,xon --run='tbw tb_tst_rlink_arty'
.. commands above ...

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@@ -0,0 +1,92 @@
.\" -*- nroff -*-
.\" $Id: tbrun_tbw.1 745 2016-03-18 22:10:34Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN_TBW 1 2016-03-18 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun_tbw \- \fBtbw\fP based test bench starter
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY tbrun_tbw
.OP OPTIONS
.I TBENCH
.OP STIMFILE
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBtbrun_tbw\fP is a convenience script for starting \fBtbw\fP(1) based
test benches. It will
.RS 2
.PD 0
.IP "-" 2
issue a \fBmake\fP(1) command to (re)-build \fITBENCH\fP.
.IP "-"
build a \fBtbw\fP(1) command, using \fISTIMFILE\fP if specified.
.IP "-"
create a shell pipe to which runs tbw and handles the output with
.IP " -" 4
\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics
created by \fBghdl\fP(1) and it's IEEE libs
.IP " -"
\fBtee\fP(1) to save the output to a log file. The log file
name is build as "<TBENCH>_<lsuf>.log"
.IP " -"
\fBegrep\fP(1) to filter out only essential lines to stdout
.PD
.RE
.PP
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Note: \fBtbrun_tbw\fP is implemented as shell script. If options have an
argument it is separated white space and not by '='! So write '--ghw\ xxx'
and not '--ghw=xxx' !
.
.\" -- --dry -------------------------------------
.IP \fB\-\-dry\fP
dry run, prints the commands but doesn't execute
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log'
.
.\" -- --stack -----------------------------------
.IP \fB\-\-stack\ \fInnn\fR
use \fInnn\fP as \fBghdl\fP(1) stack size
.
.\" -- --ghw fname -------------------------------
.IP \fB\-\-ghw\ \fIfname\fR
write a ghw file with name '\fIfname\fP.ghw'
.
.\" -- --tbw opts --------------------------------
.IP \fB\-\-tbw\ \fIopts\fR
append \fIopts\fP to the \fBtbw\fP(1) command
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBtbrun_tbw tb_serport_uart_rx" 4
Simplest default case, will execute
.EX
make tb_serport_uart_rx
time tbw tb_serport_uart_rx 2>&1 |\\
ghdl_assert_filter |\\
tee tb_serport_uart_rx_dsim.log |\\
egrep "(-[EFW]:|ERROR|FAIL|PASS|DONE)"
.EE
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbw (1),
.BR ghdl_assert_filter (1),
.BR ghdl (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: tbrun_tbwrri.1 745 2016-03-18 22:10:34Z mueller $
.\"
.\" Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBRUN_TBWRRI 1 2016-03-18 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbrun_tbw \- \fBti_rri\fP plus \fBtbw\fP based test bench starter
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY tbrun_tbwrri
.OP OPTIONS
.I TBENCH
.OP COMMANDS
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBtbrun_tbwrri\fP is a convenience script for starting \fBti_rri\fP(1) plus
\fBtbw\fP(1) based test benches. It will
.RS 2
.PD 0
.IP "-" 2
issue a \fBmake\fP(1) command to (re)-build \fITBENCH\fP.
.IP "-"
build a \fBtbw\fP(1) command to start \fITBENCH\fP.
.IP "-"
build a \fBti_rri\fP(1) command which starts \fBtbw\fP via \fB\-\-run\fP
.IP "-"
create a ti_rri command list with
.IP " -" 4
setup commands resulting from \fB\-\-cuff\fP, \fB\-\-fusp\fP, ...
.IP " -"
all optional \fICOMMANDS\fP
.IP "-" 2
create shell pipes to filter the output with
.IP " -" 4
\fBghdl_assert_filter\fP(1) to suppress irrelevant diagnostics
created by \fBghdl\fP(1) and it's IEEE libs
.IP " -"
\fBtee\fP(1) to save the output to a log file. The log file
name is build as "<TBENCH>_<lsuf>.log"
.IP " -"
\fBegrep\fP(1) to filter out only essential lines to stdout
.PD
.RE
.PP
.
.\" ------------------------------------------------------------------
.SH OPTIONS
Note: \fBtbrun_tbwrri\fP is implemented as shell script. If options have an
argument it is separated white space and not by '='! So write '--ghw\ xxx'
and not '--ghw=xxx' !
.
.\" -- --dry -------------------------------------
.IP \fB\-\-dry\fP
dry run, prints the commands but doesn't execute
.
.\" -- --lsuf ------------------------------------
.IP \fB\-\-lsuf\ \fIsuff\fR
use '_\fIsuff\fR.log' as suffix for log file. Default is '_dsim.log'
.
.\" -- --stack -----------------------------------
.IP \fB\-\-stack\ \fInnn\fR
use \fInnn\fP as \fBghdl\fP(1) stack size
.
.\" -- --ghw fname -------------------------------
.IP \fB\-\-ghw\ \fIfname\fR
write a ghw file with name '\fIfname\fP.ghw'
.
.\" -- --tbw opts --------------------------------
.IP \fB\-\-tbw\ \fIopts\fR
append \fIopts\fP to the \fBtbw\fP command
.
.\" -- --rri opts --------------------------------
.IP \fB\-\-rri\ \fIopts\fR
append \fIopts\fP to the \fBti_rri\fP command
.
.\" -- --pack plist ------------------------------
.IP \fB\-\-pack\ \fIplist\fR
add a '\-\-pack=\fIplist\fR' option to \fBti_rri\fP command
.
.\" -- --cuff ------------------------------------
.IP \fB\-\-cuff\fR
use Cypress FX2 instead of serport, will generate appropriate 'rlc oob' commands.
For nexys2 and nexys3 designs.
.
.\" -- --fusp ------------------------------------
.IP \fB\-\-fusp\fR
use 2nd serport, will generate appropriate 'rlc oob' commands.
For s3board, nexys2, and nexys3 designs.
.
.\" -- --sxon ------------------------------------
.IP \fB\-\-sxon\fR
switched\ XON: enable XON flow control with SWI(1), will generate appropriate
'rlc oob' commands and ti_rri \-\-fifo options.
For nexys4 designs.
.
.\" -- --hxon ------------------------------------
.IP \fB\-\-hxon\fR
hardwired\ XON: will generate appropriate \fBti_rri\fP \fB\-\-fifo\fP options.
For basys3 and arty designs.
.
.\" -- --pcom ------------------------------------
.IP \fB\-\-pcom\fR
enables that test bench comments are passed to stdout.
.
.\" -- --help ------------------------------------
.IP \fB\-\-help\fR
print help message and quit.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR tbw (1),
.BR ti_rri (1),
.BR ghdl_assert_filter (1),
.BR ghdl (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: tbw.1 620 2014-12-25 10:48:35Z mueller $
.\" $Id: tbw.1 727 2016-02-07 13:58:47Z mueller $
.\"
.\" Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBW 1 2011-11-06 "Retro Project" "Retro Project Manual"
.TH TBW 1 2016-02-06 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbw \- wrapper script to start ghdl based VHDL test benches
@@ -71,7 +71,8 @@ defined via the \fItbw.dat\fP file, for details see section FILES.
The options \fB\-run\fP, \fB\-fifo\fP and \fB\-verbose\fP are processed
by tbw itself. If more than one is given they must be in this order.
.IP \fB\-run\fR
Used for _ISim tb's, runs the tb with a 'run all' command.
Used for _ISim or _XSim tb's, ensures that simulation runs till end. Will
issue a 'run all' command for ISim and a '-R' option for XSim.
.IP \fB\-fifo\fR
Forces usage of rlink_cext fifo, will ignore tbw.dat
.IP \fB\-verbose\fR

20
doc/man/man1/ti_rri.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: ti_rri.1 666 2015-04-12 21:17:54Z mueller $
.\" $Id: ti_rri.1 742 2016-03-13 14:40:19Z mueller $
.\"
.\" Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TI_RRI 1 2015-04-12 "Retro Project" "Retro Project Manual"
.TH TI_RRI 1 2016-03-13 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
ti_rri \- \fBRlink\fP Backend Server
@@ -87,7 +87,12 @@ software flow control (xon/xoff)
defer link initialization (debug or test benches)
.PD
.RE
Note: in general the default pipe names are used, thus \fIname\fP is almost
never specified. If only options are given an empty \fIname\fP field must be
specified like in \fB\-\-fifo=,xon\fP.
.RE
.
.\" -- --term ------------------------------------
.IP \fB\-\-term\fR[=\fIname\fR[,\fIbaud\fR[,\fIopts\fR]]]
@@ -207,10 +212,15 @@ with eval.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBti_rri --fifo --run='tbw tb_tst_rlink_n3'" 4
Starts the \fBghdl\fP(1) test bench 'tb_tst_rlink_n3' located in CWD via
.IP "\fBti_rri --fifo --run='tbw tb_tst_rlink_n4'" 4
Starts the \fBghdl\fP(1) test bench 'tb_tst_rlink_n4' located in CWD via
\fBtbw\fP(1). It is assumed that the local \fItbw.dat\fP file configures
fifo communication for the test bench.
.
.IP "\fBti_rri --fifo=,xon --run='tbw tb_tst_rlink_arty'" 4
Like above, starts arty rather n4 test bench. The rlink is operated with
software flow control. Note the comma in front of \fIxon\fP, required to
ensure that default pipe name is used !
.\" ------------------------------------------------------------------
.SH "SEE ALSO"

24
doc/man/man1/ti_w11.1
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: ti_w11.1 712 2015-11-01 22:53:45Z mueller $
.\" $Id: ti_w11.1 745 2016-03-18 22:10:34Z mueller $
.\"
.\" Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -51,15 +51,19 @@ use /dev/ttyUSB* (* is device number \fIN\fP)
.SS "setup options for ghdl simulation runs"
.PD 0
.IP \fB-b3\fP
start \fItb_w11a_b3\fP simulation (w11a on Basys3, default \fB-f1x\fP)
start \fItb_w11a_b3\fP simulation (Basys3, default \fB-fx\fP)
.IP \fB-n4\fP
start \fItb_w11a_n4\fP simulation (w11a on Nexys4)
start \fItb_w11a_n4\fP simulation (Nexys4)
.IP \fB-bn4\fP
start \fItb_w11a_br_n4\fP simulation (Nexys4, BRAM only)
.IP \fB-bar\fP
start \fItb_w11a_br_arty\fP simulation (Arty, BRAM only, default \fB-fx\fP)
.IP \fB-n3\fP
start \fItb_w11a_n3\fP simulation (w11a on Nexys3, default \fB-fc\fP)
start \fItb_w11a_n3\fP simulation (Nexys3, default \fB-fc\fP)
.IP \fB-n2\fP
start \fItb_w11a_n2\fP simulation (w11a on Nexys2, default \fB-fc\fP)
start \fItb_w11a_n2\fP simulation (Nexys2, default \fB-fc\fP)
.IP \fB-s3\fP
start \fItb_w11a_s3\fP simulation (w11a on S3board, default \fB-f2\fP)
start \fItb_w11a_s3\fP simulation (S3board, default \fB-f2\fP)
.PD
.IP \fB-f\fIm\fR
select communication mode for simulation. The \fB-f\fIm\fR can be used after
@@ -69,14 +73,16 @@ for mode \fIm\fP are
.PD 0
.IP \fBc\fP 4
use Cypress FX2 data path (cuff, only for -n2 and -n3)
.IP \fBx\fP 4
use 1st serport with hardwired xon (for -b3 and -arty)
.IP \fB1\fP 4
use 1st serport
.IP \fB1x\fP 4
use 1st serport with xon
use 1st serport with switched xon
.IP \fB2\fP 4
use 2nd serport (fusp, only for -s3,-n2,-n3)
.IP \fB2x\fP 4
use 2nd serport with xon
use 2nd serport with switched xon
.PD
.RE
.IP \fB-tmu\fP
@@ -91,6 +97,8 @@ activate ghw wave file writing
load and execute \fIfile\fP. If the file type is '.mac' the file will
be on the fly compiled with \fBasm-11\fP(1), for all other file types
it is assumed that they are in \fBlda\fP(5) format.
.IP \fB-dry\fR
dry run, prints the commands but doesn't execute
.
.\" ------------------------------------------------------------------
.SH EXAMPLES

122
doc/man/man1/vbomconv.1
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@@ -1,38 +1,18 @@
.\" -*- nroff -*-
.\" $Id: vbomconv.1 646 2015-02-15 12:04:55Z mueller $
.\" $Id: vbomconv.1 746 2016-03-19 13:08:36Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\"
.\" ------------------------------------------------------------------
.
.TH VBOMCONV 1 2015-02-15 "Retro Project" "Retro Project Manual"
.TH VBOMCONV 1 2016-03-19 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbomconv \- generate files and actions from vbom manifest files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY vbomconv
.B \-\-help
.
.SY vbomconv
.OP \-\-trace
.B \-\-dep_ghdl
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-dep_xst
|
.B \-\-dep_isim
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-dep_vsyn
.I vbom
.
.\" --- ghdl
.SY vbomconv
.OP \-\-trace
.B \-\-ghdl_i_cmd
@@ -60,9 +40,25 @@ vbomconv \- generate files and actions from vbom manifest files
.OP \-\-trace
.BI \-\-ghdl_export "\fR=\fPpath"
.I vbom
.\" --- vivado
.SY vbomconv
.OP \-\-trace
.B \-\-vsyn_prj
|
.B \-\-vsim_prj
.I vbom
.
.SY vbomconv
.OP \-\-trace
.BI \-\-vsyn_export "\fR=\fPpath"
|
.BI \-\-vsim_export "\fR=\fPpath"
.I vbom
.\" --- ise
.SY vbomconv
.OP \-\-trace
.B \-\-xst_prj
|
.B \-\-isim_prj
@@ -74,14 +70,30 @@ vbomconv \- generate files and actions from vbom manifest files
|
.BI \-\-isim_export "\fR=\fPpath"
.I vbom
.\" --- dep_
.SY vbomconv
.OP \-\-trace
.B \-\-dep_ghdl
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-vsyn_prj
.B \-\-dep_xst
|
.B \-\-dep_isim
.I vbom
.
.SY vbomconv
.OP \-\-trace
.B \-\-dep_vsyn
|
.B \-\-dep_vsim
.I vbom
.\" --- general
.SY vbomconv
.OP \-\-trace
.B \-\-get_top
.I vbom
.
@@ -89,6 +101,8 @@ vbomconv \- generate files and actions from vbom manifest files
.OP \-\-trace
.B \-\-flist
.I vbom
.SY vbomconv
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
@@ -112,18 +126,21 @@ The \fBvbomconv\fP tool does this traversal of \fBvbom\fP
files and generates, depending on command line options, the files and/or
commands needed to run a synthesis tool or to build a simulation model.
Currently supported is synthesis with Xilinx ISE \fBxst\fP Xilinx Vivado
and simulation with \fBghdl\fP(1) or Xilinx ISE \fBISim\fP.
and simulation with \fBghdl\fP(1), Xilinx ISE \fBISim\fP or
Xilinx Vivado \fBxsim\fP.
\fBvbomconv\fP therefore currently generates
.PD 0
.IP "\fB- ghdl\fP" 8
commands for analysis, inspection and make step
.IP "\fB- xst\fP" 8
project files
.IP "\fB- ISim\fP" 8
project files
.IP "\fB- vsyn\fP" 8
project setups for Vivado synthesis
.IP "\fB- vsim\fP" 8
project setups for Vivado simulation
.IP "\fB- xst\fP" 8
project files for ISE synthesis
.IP "\fB- ISim\fP" 8
project files for ISE simulation
.IP "\fB- make\fP" 8
dependency files
.PD
@@ -191,7 +208,7 @@ The first definition seen in the \fIvbom\fP
traversal is taken, all others are ignored. The filename in the usage clause
is the default used in case the logical name wasn't defined.
Last but not least are 3 directives defined in the \fBvbom\fP
Last but not least are 5 directives defined in the \fBvbom\fP
file format:
.
.IP "\fB@top\fP:\fIname\fP"
@@ -203,8 +220,19 @@ allows to specify additional system libraries. Currently used to indicate
that the \fIunisim\fP, \fIunimacro\fP or \fIsimprim\fP libraries are
needed by \fBghdl\fP.
.
.IP "\fB@uut\fP:\fIfile\fP"
signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is
the 'unit under test'. This allows to split the sources into a simulation
only test bench part and a synthesizable 'unit under test' part. \fIfile\fP
is typically a \fIvbom\fP in case of a functional simulation or the file
name of a generated post synthesis model.
.
.IP "\fB@xdc\fP:\fIfile\fP"
specifies that \fIfile\fP is a constraint file for Vivado synthesis and should
be included in the constraints fileset.
.
.IP "\fB@ucf_cpp\fP:\fIfile\fP"
indicates that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1)
specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1)
from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files.
.PP
The full description of the file format and examples are given in a
@@ -258,6 +286,8 @@ one not requiring a \fIvbom\fP file.
.B \-\-dep_isim
.TQ
.B \-\-dep_vsyn
.TQ
.B \-\-dep_vsim
These four actions write to \fIstdout\fP dependency rules for inclusion in
\fIMakefile\fPs.
Together with an appropruate pattern rule they allow to automatitize
@@ -314,6 +344,14 @@ and produces the following types of dependencies
\fI<stem>\fP_rou.dcp : \fB*\fP.vhd \fB*\fP.xdc
\fI<stem>\fP.dep_vsyn : \fB*\fP.vbom
.EE
\fB\-\-dep_vsim\fP creates the dependencies for Vivado \fBxim\fP
based simulation models and produces the following types of dependencies
.EX
\fI<stem>\fP_XSim : \fI<stem>\fP.dep_vsim
\fI<stem>\fP_XSim : \fB*\fP.vhd
\fI<stem>\fP.dep_vsim : \fB*\fP.vbom
.EE
.
.\" ----------------------------------------------
.TP
@@ -359,19 +397,30 @@ the EXAMPLES section for practical usage in a make flow.
.\" ----------------------------------------------
.TP
.B \-\-vsym_prj
This action write to \fIstdout\fP a Tcl script suitable as project definition
This action writes to \fIstdout\fP a Tcl script suitable as project definition
for Vivado synthesis. This script is source'ed or eval'ed and defines the
source fileset and the constraints fileset. The vhdl source files are in
proper compilation order.
.
.\" ----------------------------------------------
.TP
.BI \-\-xst_export \fR=\fPpath
.TQ
.B \-\-vsim_prj
This action writes to \fIstdout\fP a shell script which will generated the
Vivado simulation snapshot and a short forwarder script for starting the
simulation.
.
.\" ----------------------------------------------
.TP
.BI \-\-ghdl_export \fR=\fPpath
.TQ
.BI \-\-vsyn_export \fR=\fPpath
.TQ
.BI \-\-vsim_export \fR=\fPpath
.TQ
.BI \-\-xst_export \fR=\fPpath
.TQ
.BI \-\-isim_export \fR=\fPpath
These three actions create a flat copy of all source files needed for a
These actions create a flat copy of all source files needed for a
\fBxst\fP synthesis or a \fBghdl\fP or \fBISim\fP
simulation model in the directory \fIpath\fP.
The sub directory structure is lost, all files will be in directory
@@ -508,6 +557,7 @@ output like in
.BR rm_dep (1),
.BR ghdl (1),
.BR xtwi (1),
.BR xtwv (1),
.BR cpp (1),
.br
.BR xise_ghdl_simprim (1),

26
doc/man/man1/xtwi.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: xtwi.1 651 2015-02-26 21:32:15Z mueller $
.\" $Id: xtwi.1 746 2016-03-19 13:08:36Z mueller $
.\"
.\" Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XTWI 1 2013-11-10 "Retro Project" "Retro Project Manual"
.TH XTWI 1 2016-03-19 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xtwi \- Xilinx Tool Wrapper script for ISE
@@ -31,6 +31,9 @@ by the ISE installation procedure.
and execs the \fICOMMAND\fP. This way \fICOMMAND\fP is executed in the
ISE environment, while the login shell stays clean.
\fBxtwi\fP can also setup a clean environment when BARE_PATH and
BARE_LD_LIBRARY_PATH are defined.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
@@ -38,6 +41,23 @@ ISE environment, while the login shell stays clean.
.B XTWI_PATH
Install path of ISE, without the /ISE_DS/ appended by ISE installation
.
.TP
.B BARE_PATH
Optional. If defined \fBxtwi\fP will set
.EX
export PATH=$BARE_PATH:$RETROBASE/tools/bin
.EE
LD_LIBRARY_PATH will be unset unless BARE_LD_LIBRARY_PATH is
defined too.
.
.TP
.B BARE_LD_LIBRARY_PATH
Optional. If defined \fBxtwi\fP will set
.EX
export LD_LIBRARY_PATH=$BARE_LD_LIBRARY_PATH
.EE
Used only when BARE_PATH is defined.
.
.\" ------------------------------------------------------------------
.SH FILES
.TP 4

26
doc/man/man1/xtwv.1
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: xtwv.1 651 2015-02-26 21:32:15Z mueller $
.\" $Id: xtwv.1 746 2016-03-19 13:08:36Z mueller $
.\"
.\" Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XTWV 1 2014-04-21 "Retro Project" "Retro Project Manual"
.TH XTWV 1 2016-03-19 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xtwv \- Xilinx Tool Wrapper script for Vivado
@@ -30,6 +30,9 @@ of the Vivado version to be used.
and execs the \fICOMMAND\fP. This way \fICOMMAND\fP is executed in the
Vivado environment, while the login shell stays clean.
\fBxtwi\fP can also setup a clean environment when BARE_PATH and
BARE_LD_LIBRARY_PATH are defined.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
@@ -37,6 +40,23 @@ Vivado environment, while the login shell stays clean.
.B BXTWV_PATH
Install path of Vivado
.
.TP
.B BARE_PATH
Optional. If defined \fBxtwi\fP will set
.EX
export PATH=$BARE_PATH:$RETROBASE/tools/bin
.EE
LD_LIBRARY_PATH will be unset unless BARE_LD_LIBRARY_PATH is
defined too.
.
.TP
.B BARE_LD_LIBRARY_PATH
Optional. If defined \fBxtwi\fP will set
.EX
export LD_LIBRARY_PATH=$BARE_LD_LIBRARY_PATH
.EE
Used only when BARE_PATH is defined.
.
.\" ------------------------------------------------------------------
.SH FILES
.TP 4

39
doc/man/man5/vbom.5
View File

@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: vbom.5 646 2015-02-15 12:04:55Z mueller $
.\" $Id: vbom.5 746 2016-03-19 13:08:36Z mueller $
.\"
.\" Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH VBOM 2015-02-15 "Retro Project" "Retro Project Manual"
.TH VBOM 2016-03-19 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
vbom \- vhdl manifest file format - 'vhdl bill of material'
@@ -44,6 +44,14 @@ refers to a source file. Usually used for libraries refered to in 'use'
clauses, and as last file, the source file of the entity which is
described by this \fBvbom\fP file.
.
.TP
.B "\fB.v\fP"
.TQ
.B "\fB.sv\fP"
refers to a verilog or system-verilog source file. Accepted by the vivado
xsim simulator. Typically used for DPI wrappers or simprim based models
in vivado.
.
.IP "\fB.c\fP"
refers to the C source which implements a \fIvhdl\fP function or procedure
via the \fIvhpi\fP mechanism. Supported only in conjunction with \fBghdl\fP.
@@ -74,14 +82,18 @@ Currently supported \fItag\fP names are
.PD 0
.IP "\fBghdl\fP" 6
included in conjunction with ghdl simulation
.IP "\fBxst\fP" 6
included in conjunction with ISE xst synthesis
.IP "\fBisim\fP" 6
included in conjunction with ISE ISim simulation
.IP "\fBviv\fP" 6
included in conjunction with Vivado targets
.IP "\fBvsyn\fP" 6
included in conjunction with Vivado synthesis
.IP "\fBvsim\fP" 6
included in conjunction with Vivado simulation
.IP "\fBise\fP" 6
included in conjunction with ISE targets
.IP "\fBxst\fP" 6
included in conjunction with ISE xst synthesis
.IP "\fBisim\fP" 6
included in conjunction with ISE ISim simulation
.IP "\fBsim\fP" 6
included in conjunction with simulation (ghdl,isim,vsim)
.PD
@@ -122,13 +134,20 @@ Specifies an additional system library. Allowed values for \fIname\fP are
Currently used to generate the appropriate -L options for \fBghdl\fP commands,
e.g. generated by the \fBvbomconv\fP action \fB\-\-ghdl_m\fP.
.
.IP "\fB@ucf_cpp\fP:\fIfile\fP"
Specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1)
from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files.
.IP "\fB@uut\fP:\fIfile\fP"
Signals that the \fIvbom\fP descibes a test bench and that \fIfile\fP is
the 'unit under test'. This allows to split the sources into a simulation
only test bench part and a synthesizable 'unit under test' part. \fIfile\fP
is typically a \fIvbom\fP in case of a functional simulation or the file
name of a generated post synthesis model.
.
.IP "\fB@xdc\fP:\fIfile\fP"
Specifies that \fIfile\fP is a constraint file for Vivado synthesis and should
be included in the constraints fileset.
.
.IP "\fB@ucf_cpp\fP:\fIfile\fP"
Specifies that a \fIfile\fP.ucf file is to be generated by \fBcpp\fP(1)
from a \fIfile\fP.ucf_cpp source file. This allows to modularize ISE ucf files.
.RE
.
.\" ------------------------------------------------------------------

44
doc/w11a_os_guide.txt
View File

@@ -1,4 +1,4 @@
# $Id: w11a_os_guide.txt 680 2015-05-14 13:29:46Z mueller $
# $Id: w11a_os_guide.txt 745 2016-03-18 22:10:34Z mueller $
Guide to run operating system images on w11a systems
@@ -20,7 +20,7 @@ Guide to run operating system images on w11a systems
- Serial port
- via an integrated USB-UART bridge
- on basys3 and nexys4 with a FT2232HQ, allows up to 12M Baud
- on arty, basys3, and nexys4 with a FT2232HQ, allows up to 12M Baud
- on nexys3 with a FT232R, allows up to 2M Baud
- via RS232 port, as on s3board and nexys2
- using a serial port (/dev/ttySx) is limited to 115 kBaud on most PCs.
@@ -45,18 +45,24 @@ Guide to run operating system images on w11a systems
Recommended setup for best performance (boards ordered by vintage):
Board Channel/Interface nom. speed peak transfer rate
Board Channel/Interface nom. speed peak transfer rate
basys3 USB-UART bridge 10M Baud 910 kB/sec
nexys4 USB-UART bridge 10M Baud 910 kb/sec
nexys3 Cypress FX2 USB USB2.0 speed 30000 kB/sec
nexys2 Cypress FX2 USB USB2.0 speed 30000 kB/sec
s3board RS232+USB-RS232 cable 460k Baud 41 kB/sec
arty USB-UART bridge 10M Baud 910 kB/sec
basys3 USB-UART bridge 10M Baud 910 kB/sec
nexys4 USB-UART bridge 10M Baud 910 kb/sec
nexys3 Cypress FX2 USB USB2.0 speed 30000 kB/sec
nexys2 Cypress FX2 USB USB2.0 speed 30000 kB/sec
s3board RS232+USB-RS232 cable 460k Baud 41 kB/sec
2. FPGA Board setup -------------------------------------------------------
Recommended setups
- Arty
- connect USB cable to micro-USB connector labeled 'J10'
- to configure via vivado hardware server
make <sys>.vconfig
- Basys3
- connect USB cable to micro-USB connector labeled 'PROG'
- to configure via vivado hardware server
@@ -99,16 +105,24 @@ Guide to run operating system images on w11a systems
are in the indicated positions (SWI=...). The concrete boot script
name <boot-script> is given in the following sections
- for b3 over serial
SWI = 00000000 00101010
- for arty over serial
SWI = 0110 (gives console light emulation...)
ti_w11 -tu<dn>,10M,break,xon @<oskit-name>_boot.tcl
NOTE: the arty w11a has currently only 176 kB memory (all from BRAMS!)
unix-v5 works fine. XXDP, RT11 and RSX-11M should work.
211bsd will not boot, either most RSX-11M+ systems.
- for b3 over serial
SWI = 00000000 00101000 (gives console light display on LEDS)
ti_w11 -tu<dn>,12M,break,xon @<oskit-name>_boot.tcl
NOTE: the basys3 w11a has only 176 kB memory (all from BRAMS!)
unix-v5 works fine. XXDP, RT11 and RSX-11M should work.
211bsd will not boot, either most RSX-11M+ systems.
- for n4 over serial
SWI = 00000000 00101000
SWI = 00000000 00101000 (gives console light display on LEDS)
ti_w11 -tu<dn>,10M,break,cts @<oskit-name>_boot.tcl
- for n2,n3 over fx2
@@ -122,10 +136,10 @@ Guide to run operating system images on w11a systems
Notes:
- on <dn>, the serial device number
- check with 'ls /dev/ttyUSB*' to see what is available
- <dn> is typically '1' if only a single basys3 or nexys4 is connected
Initially two ttyUSB devices show up, the lower is for FPGA config
and will disappear when Vivado hardware server is used once. The
upper provides the data connection.
- <dn> is typically '1' if a single FT2232HQ based boardis connected,
like a arty, basys3, or nexys4. Initially two ttyUSB devices show up,
the lower is for FPGA config and will disappear when Vivado hardware
server is used once. The upper provides the data connection.
- <dn> is typically '0' if only a single USB-RS232 cable is connected
- on LED display

239
doc/w11a_tb_guide.txt
View File

@@ -1,7 +1,10 @@
# $Id: w11a_tb_guide.txt 722 2015-12-30 19:45:46Z mueller $
# $Id: w11a_tb_guide.txt 745 2016-03-18 22:10:34Z mueller $
Note: Only ISE based test benches are currently documented !
The Vivado test environemnt is still in it's infancy !
Note: - Ghdl is used to all functional simulations
- Optionally Vivado xsim can be used (with some limitations)
- For post synthesis or post implementation simulations either
Ghdl or Vivado xsim (with some limitations) can be used.
- ISE isim is also available, but considered legacy support
Guide to running w11a test benches
@@ -45,15 +48,26 @@ Guide to running w11a test benches
- Most tests can be run against
- the functional model
- gate level models at three stages
- gate level models at three stages (vivado flow)
- the post synthesis model (from *_syn.dcp)
- the post optimization model (from *_opt.dcp)
- the post routing model (from *_rou.dcp)
This is simply done using
make <testbench>_ssim for post-synthesis
make <testbench>_osim for post-optimization
make <testbench>_tsim for post-routing
- gate level models at three stages (ISE flow)
- the post-xst model (produced by netgen from ngc xst output)
- the post-map model (produced by netgen from ncd ngdbuild output)
- the post-par model (produced by netgen from ncd par output)
This is simply done using
make <testbench>_ssim for post-xst
make <testbench>_fsim for post-map
make <testbench>_tsim for post-par
all the rest is handled by the build environment.
This is simply done using
make <testbench>_ssim for post-xst
make <testbench>_fsim for post-map
make <testbench>_tsim for post-par
All the rest is handled by the build environment.
An example of a post-synthesis model is given for the w11a core test.
- for convenience a wrapper script 'tbrun_tbw' is used to generate the
@@ -71,68 +85,69 @@ Guide to running w11a test benches
cd $RETROBASE/rtl/vlib/serport/tb
tbrun_tbw tb_serport_uart_rx
-> 1269955.0 ns 63488: DONE
-> real 0m01.178s user 0m01.172s sys 0m00.020s
-> real 0m0.444s user 0m0.453s sys 0m0.007s
- serport receiver/transmitter test
tbrun_tbw tb_serport_uart_rxtx
-> 52335.0 ns 2607: DONE
-> real 0m00.094s user 0m00.092s sys 0m00.008s
-> real 0m0.074s user 0m0.077s sys 0m0.010s
- serport autobauder test
tbrun_tbw tb_serport_autobaud
-> 367475.0 ns 18364: DONE
-> real 0m00.610s user 0m00.612s sys 0m00.004s
-> real 0m0.247s user 0m0.258s sys 0m0.007s
- 9 bit comma,data to Byte stream converter test
cd $RETROBASE/rtl/vlib/comlib/tb
tbrun_tbw tb_cdata2byte
-> 7261.0 ns 354: DONE
-> real 0m0.385s user 0m0.041s sys 0m0.006s
-> 7261.0 ns 354: DONE
-> real 0m0.042s user 0m0.042s sys 0m0.019s
- rlink core test
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw tb_rlink_direct
-> 78975.0 ns 3939: DONE
-> real 0m00.508s user 0m00.262s sys 0m00.028s
-> real 0m0.225s user 0m0.226s sys 0m0.025s
- rlink core test via serial port interface
cd $RETROBASE/rtl/vlib/rlink/tb
tbrun_tbw --lsuf stim2_dsim tb_rlink_sp1c tb_rlink_sp1c_stim.dat
-> 27595.0 ns 1370: DONE
-> real 0m0.250s user 0m0.108s sys 0m0.011s
-> real 0m0.098s user 0m0.111s sys 0m0.007s
tbrun_tbw --lsuf stim1_dsim tb_rlink_sp1c tb_rlink_stim.dat
-> 420295.0 ns 21005: DONE
-> real 0m02.271s user 0m01.360s sys 0m00.040s
-> real 0m0.942s user 0m0.947s sys 0m0.012s
- w11a core test (using behavioural model)
cd $RETROBASE/rtl/w11a/tb
tbrun_tbw tb_pdp11core
-> 1220255.0 ns 61073: DONE
-> real 0m10.736s user 0m10.713s sys 0m00.060s
-> 225355.0 ns 61258: DONE
-> real 0m6.280s user 0m6.284s sys 0m0.018s
- w11a core test (using post-synthesis model)
- w11a core test (using Vivado post-synthesis model)
tbrun_tbw tb_pdp11core_ssim
-> 1220255.0 ns 61073: DONE
-> real 1m09.738s user 1m09.588s sys 0m00.096s
-> 225355.0 ns 61258: DONE
-> real 2m4.138s user 2m4.063s sys 0m0.050s
- s3board sram controller test
cd $RETROBASE/rtl/bplib/s3board/tb
tbrun_tbw tb_s3_sram_memctl
-> 5015.0 ns 241: DONE
-> real 0m00.113s user 0m00.068s sys 0m00.016s
-> real 0m0.107s user 0m0.055s sys 0m0.020s
- nexys2/nexys3 cram controller test
cd $RETROBASE/rtl/bplib/nxcramlib/tb
tbrun_tbw tb_nx_cram_memctl_as
-> 24272.5 ns 1204: DONE
-> real 0m00.343s user 0m00.248s sys 0m00.100s
-> real 0m0.189s user 0m0.149s sys 0m0.055s
3. System tests benches ---------------------------------------------------
@@ -162,62 +177,112 @@ Guide to running w11a test benches
cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
tbrun_tbw tb_tst_serloop_s3
-> 301353.3 ns 18068: DONE
-> real 0m1.422s user 0m1.372s sys 0m0.024s
-> real 0m0.765s user 0m0.781s sys 0m0.013s
- sys_tst_serloop_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
tbrun_tbw tb_tst_serloop1_n2
-> 361560.0 ns 18068: DONE
-> real 0m1.341s user 0m1.340s sys 0m0.016s
-> real 0m0.994s user 0m0.991s sys 0m0.022s
tbrun_tbw tb_tst_serloop2_n2
-> 304353.3 ns 18248: DONE
-> real 0m1.933s user 0m1.924s sys 0m0.024s
-> real 0m1.543s user 0m1.561s sys 0m0.007s
- sys_tst_serloop_n3 test bench
cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
tbrun_tbw tb_tst_serloop1_n3
-> 361560.0 ns 18068: DONE
-> real 0m1.371s user 0m1.372s sys 0m0.016s
-> real 0m0.740s user 0m0.755s sys 0m0.012s
4b. rlink tester -----------------------------------------------------
The sys_tst_rlink design is a test target for validating the rlink
and rbus functionality at all levels.
The sys_tst_rlink design is a test target for validating the rlink and
rbus functionality at all levels.
- sys_tst_rlink_s3 test bench
- Artix based systems
cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
tbrun_tbwrri --pack tst_rlink tb_tst_rlink_s3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1377680.0 ns 68874: DONE
-> real 0m6.876s user 0m6.790s sys 0m0.060s
- sys_tst_rlink_arty test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_arty \
"tst_rlink::setup" "tst_rlink::test_all"
-> 764400.0 ns 76419: DONE
-> real 0m9.323s user 0m9.233s sys 0m0.080s
- sys_tst_rlink_n2 test bench
- sys_tst_rlink_b3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/basys3/tb
tbrun_tbwrri --hxon --pack tst_rlink tb_tst_rlink_b3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 763900.0 ns 76369: DONE
-> real 0m6.804s user 0m6.696s sys 0m0.085s
- sys_tst_rlink_n4 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys4/tb
tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n4 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 758010.0 ns 75780: DONE
-> real 0m10.198s user 0m10.081s sys 0m0.104s
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n2 \
- Spartan based systems
- sys_tst_rlink_n3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 763770.0 ns 76356: DONE
-> real 0m5.955s user 0m5.834s sys 0m0.094s
- sys_tst_rlink_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1526860.0 ns 76332: DONE
-> real 0m8.607s user 0m8.448s sys 0m0.150s
- sys_tst_rlink_s3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
tbrun_tbwrri --fusp --pack tst_rlink tb_tst_rlink_s3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1526540.0 ns 76317: DONE
-> real 0m5.650s user 0m5.571s sys 0m0.052s
4c. rlink tester, Cypress FX2 based version --------------------------
The sys_tst_rlink_cuff design is a test target for validating the rlink and
rbus functionality at all levels over the Cypress FX2 USB interface which
is provided by the Nexys2 abd Nexys3 boards.
- sys_tst_rlink_cuff_ic_n3 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n3 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 1378200.0 ns 68899: DONE
-> real 0m10.320s user 0m10.110s sys 0m0.204s
-> 440440.0 ns 44023: DONE
-> real 0m4.062s user 0m3.922s sys 0m0.111s
- sys_tst_rlink_n3 test bench
- sys_tst_rlink_cuff_ic_n2 test bench
cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
tbrun_tbwrri --pack tst_rlink tb_tst_rlink_n3 \
cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
tbrun_tbwrri --cuff --pack tst_rlink tb_tst_rlink_cuff_ic_n2 \
"tst_rlink::setup" "tst_rlink::test_all"
-> 689210.0 ns 68900: DONE
-> real 0m7.098s user 0m6.874s sys 0m0.191s
-> 466940.0 ns 23336: DONE
-> real 0m2.831s user 0m2.696s sys 0m0.101s
4c. w11a systems -----------------------------------------------------
4d. w11a systems -----------------------------------------------------
The stimulus file used in the w11a core test can be executed in the
full system context (both s3board and nexys2 versions) with the
following commands. Note that the cycle number printed in the DONE
line can now vary slightly because the response time of the rlink
backend process and thus scheduling of backend vs. ghdl process
The stimulus file used in the w11a core test can be executed in the full
system context with the following commands. Note that the cycle number
printed in the DONE line can now vary slightly because the response time of
the rlink backend process and thus scheduling of backend vs. ghdl process
can affect the result.
For convenience a wrapper script 'tbrun_tbwrri' is used to generate the
@@ -225,32 +290,43 @@ Guide to running w11a test benches
checks with 'make' whether the test bench is up-to-date or must be
(re)-compiled.
- sys_w11a_s3 test bench
- Artix based systems
cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
tbrun_tbwrri --pack rw11 tb_w11a_s3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 9864500.0 ns 493215: DONE
-> real 0m59.728s user 0m58.586s sys 0m0.576s
cd $RETROBASE/rtl/sys_gen/w11a/nexys4/tb
tbrun_tbwrri --pack rw11 tb_w11a_n4 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 6681310.0 ns 534488: DONE
-> real 1m26.253s user 1m26.139s sys 0m0.430s
- sys_w11a_n2 test bench
- Spartan based systems
- sys_w11a_n3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 3614866.2 ns 231338: DONE
-> real 0m47.290s user 0m46.975s sys 0m0.537s
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --pack rw11 --cuff tb_w11a_n2 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 3809180.0 ns 190448: DONE
-> real 0m55.733s user 0m55.504s sys 0m0.592s
- sys_w11a_n3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
tbrun_tbwrri --pack rw11 --cuff tb_w11a_n3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 279834.9 ns 236133: DONE
-> real 0m59.998s user 0m59.676s sys 0m0.618s
- sys_w11a_n2 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --cuff --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 4007500.0 ns 200364: DONE
-> real 0m43.803s user 0m43.698s sys 0m0.400s
- sys_w11a_s3 test bench
cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
tbrun_tbwrri --fusp --pack rw11 tb_w11a_s3 \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
-> 10526060.0 ns 526293: DONE
-> real 1m13.659s user 1m13.467s sys 0m0.431s
A new, modular w11a test bench is under construction. So far it is very
incomplete. This very preliminary version can be executed with
@@ -258,14 +334,13 @@ Guide to running w11a test benches
- sys_w11a_n2 test bench
cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \
tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
-> 3204500.0 ns 160214: DONE
-> real 0m44.753s user 0m45.361s sys 0m0.616s
-> 3280220.0 ns 164000: DONE
-> real 0m30.190s user 0m30.843s sys 0m0.577s
tbrun_tbwrri --lsuf tbench_dsim --pack rw11 --cuff tb_w11a_n2 \
tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11 tb_w11a_n2 \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"
-> 1369960.0 ns 68487: DONE
-> real 0m21.399s user 0m21.480s sys 0m0.254s
-> 1387300.0 ns 69354: DONE
-> real 0m14.298s user 0m14.314s sys 0m0.240s

14
rtl/bplib/arty/arty_pclk.xdc Normal file
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@@ -0,0 +1,14 @@
# -*- tcl -*-
# $Id: arty_pclk.xdc 726 2016-01-31 23:02:31Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Primary clocks for Digilent Arty
#
# Revision History:
# Date Rev Version Comment
# 2016-01-31 726 1.0 Initial version
#
create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100]

100
rtl/bplib/arty/arty_pins.xdc Normal file
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@@ -0,0 +1,100 @@
# -*- tcl -*-
# $Id: arty_pins.xdc 740 2016-03-06 20:56:56Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Pin locks for Digilent Arty core functionality
# - USB UART
# - human I/O (switches, buttons, leds)
#
# Revision History:
# Date Rev Version Comment
# 2016-03-06 740 1.1 add A_VPWRP/N to baseline config
# 2016-01-31 726 1.0 Initial version
#
# config setup --------------------------------------------------------------
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
# clocks -- in bank 35 ------------------------------------------------------
set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}]
#
# USB UART Interface -- in bank 16 ------------------------------------------
set_property PACKAGE_PIN a9 [get_ports {I_RXD}]
set_property PACKAGE_PIN d10 [get_ports {O_TXD}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD}]
set_property DRIVE 12 [get_ports {O_TXD}]
set_property SLEW SLOW [get_ports {O_TXD}]
#
# switches -- in bank 16 ----------------------------------------------------
set_property PACKAGE_PIN a8 [get_ports {I_SWI[0]}]
set_property PACKAGE_PIN c11 [get_ports {I_SWI[1]}]
set_property PACKAGE_PIN c10 [get_ports {I_SWI[2]}]
set_property PACKAGE_PIN a10 [get_ports {I_SWI[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}]
#
# buttons -- in bank 16 -----------------------------------------------------
set_property PACKAGE_PIN d9 [get_ports {I_BTN[0]}]
set_property PACKAGE_PIN c9 [get_ports {I_BTN[1]}]
set_property PACKAGE_PIN b9 [get_ports {I_BTN[2]}]
set_property PACKAGE_PIN b8 [get_ports {I_BTN[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}]
#
# LEDs -- in bank 14+35 -----------------------------------------------------
set_property PACKAGE_PIN h5 [get_ports {O_LED[0]}]
set_property PACKAGE_PIN j5 [get_ports {O_LED[1]}]
set_property PACKAGE_PIN t9 [get_ports {O_LED[2]}]
set_property PACKAGE_PIN t10 [get_ports {O_LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}]
set_property DRIVE 12 [get_ports {O_LED[*]}]
set_property SLEW SLOW [get_ports {O_LED[*]}]
#
# RGB-LEDs -- in bank 35 ----------------------------------------------------
# Note: [0] red [1] green [2] blue
set_property PACKAGE_PIN g6 [get_ports {O_RGBLED0[0]}]
set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[1]}]
set_property PACKAGE_PIN e1 [get_ports {O_RGBLED0[2]}]
set_property PACKAGE_PIN g3 [get_ports {O_RGBLED1[0]}]
set_property PACKAGE_PIN j4 [get_ports {O_RGBLED1[1]}]
set_property PACKAGE_PIN g4 [get_ports {O_RGBLED1[2]}]
set_property PACKAGE_PIN j3 [get_ports {O_RGBLED2[0]}]
set_property PACKAGE_PIN j2 [get_ports {O_RGBLED2[1]}]
set_property PACKAGE_PIN h4 [get_ports {O_RGBLED2[2]}]
set_property PACKAGE_PIN k1 [get_ports {O_RGBLED3[0]}]
set_property PACKAGE_PIN h6 [get_ports {O_RGBLED3[1]}]
set_property PACKAGE_PIN k2 [get_ports {O_RGBLED3[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED2[*] O_RGBLED3[*]}]
set_property DRIVE 12 [get_ports {O_RGBLED2[*] O_RGBLED3[*]}]
set_property SLEW SLOW [get_ports {O_RGBLED2[*] O_RGBLED3[*]}]
#
# power measurements -- in bank 15 ------------------------------------------
set_property PACKAGE_PIN c12 [get_ports {A_VPWRP[0]}]; # ad1p -> vaux(1)
set_property PACKAGE_PIN b12 [get_ports {A_VPWRN[0]}]; # ad1n (VU volt)
set_property PACKAGE_PIN b16 [get_ports {A_VPWRP[1]}]; # ad2p -> vaux(2)
set_property PACKAGE_PIN b17 [get_ports {A_VPWRN[1]}]; # ad2n (5V0 volt)
set_property PACKAGE_PIN f13 [get_ports {A_VPWRP[2]}]; # ad9p -> vaux(9)
set_property PACKAGE_PIN f14 [get_ports {A_VPWRN[2]}]; # ad9n (5V0 curr)
set_property PACKAGE_PIN a15 [get_ports {A_VPWRP[3]}]; # ad10p -> vaux(10)
set_property PACKAGE_PIN a16 [get_ports {A_VPWRN[3]}]; # ad10n (0V95 curr)
set_property IOSTANDARD LVCMOS33 [get_ports {A_VPWRP[*] A_VPWRN[*]}]

4
rtl/bplib/arty/arty_setup.tcl Normal file
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@@ -0,0 +1,4 @@
# $Id: arty_setup.tcl 726 2016-01-31 23:02:31Z mueller $
#
set rvtb_part "xc7a35ticsg324-1l"
set rvtb_board "arty"

51
rtl/bplib/arty/artylib.vhd Normal file
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@@ -0,0 +1,51 @@
-- $Id: artylib.vhd 740 2016-03-06 20:56:56Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: artylib
-- Description: Digilent Arty components
--
-- Dependencies: -
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-01-31 726 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package artylib is
component arty_aif is -- ARTY, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4 -- arty pwrmon (pos)
);
end component;
end package artylib;

1
rtl/bplib/arty/tb/.cvsignore Normal file
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@@ -0,0 +1 @@
tb_arty_dummy

30
rtl/bplib/arty/tb/Makefile Normal file
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@@ -0,0 +1,30 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-01-31 726 1.0 Initial version
#
EXE_all = tb_arty_dummy
#
include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk
#
.PHONY : all all_ssim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
#
clean : viv_clean ghdl_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
endif
#

5
rtl/bplib/arty/tb/arty_dummy.vbom Normal file
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@@ -0,0 +1,5 @@
# libs
../../../vlib/slvtypes.vhd
# components
# design
arty_dummy.vhd

65
rtl/bplib/arty/tb/arty_dummy.vhd Normal file
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@@ -0,0 +1,65 @@
-- $Id: arty_dummy.vhd 740 2016-03-06 20:56:56Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: arty_dummy - syn
-- Description: arty minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_arty
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-01-31 726 1.0 Initial version (cloned from basys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity arty_dummy is -- ARTY dummy (base; loopback)
-- implements arty_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- arty switches
I_BTN : in slv4; -- arty buttons
O_LED : out slv4; -- arty leds
O_RGBLED0 : out slv3; -- arty rgb-led 0
O_RGBLED1 : out slv3; -- arty rgb-led 1
O_RGBLED2 : out slv3; -- arty rgb-led 2
O_RGBLED3 : out slv3; -- arty rgb-led 3
A_VPWRN : in slv4; -- arty pwrmon (neg)
A_VPWRP : in slv4 -- arty pwrmon (pos)
);
end arty_dummy;
architecture syn of arty_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED0
O_RGBLED1 <= (others=>'0');
O_RGBLED2 <= (others=>'0');
O_RGBLED3 <= (others=>'0');
end syn;

23
rtl/bplib/arty/tb/tb_arty.vbom Normal file
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@@ -0,0 +1,23 @@
# Not meant for direct top level usage. Used with
# tb_arty_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/xlib/xlib.vhd
../artylib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_arty_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${arty_aif := arty_dummy.vbom}
# design
tb_arty.vhd
@top:tb_arty

186
rtl/bplib/arty/tb/tb_arty.vhd Normal file
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@@ -0,0 +1,186 @@
-- $Id: tb_arty.vhd 740 2016-03-06 20:56:56Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_arty - sim
-- Description: Test bench for arty (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/tb/s7_cmt_sfs_tb
-- tb_basys3_core
-- serport/tb/serport_master_tb
-- arty_aif [UUT]
--
-- To test: generic, any arty_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-06 740 1.1 add A_VPWRN/P to baseline config
-- 2016-02-20 734 1.0.2 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.0.1 direct instantiation of tbcore_rlink
-- 2016-01-31 726 1.0 Initial version (derived from tb_basys3)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.artylib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_arty is
end tb_arty;
architecture sim of tb_arty is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLK_STOP : slbit := '0';
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv4 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv4 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_RGBLED2 : slv3 := (others=>'0');
signal O_RGBLED3 : slv3 := (others=>'0');
constant clock_period : time := 10 ns;
constant clock_offset : time := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC,
CLK_STOP => CLK_STOP
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
ARTYCORE : entity work.tb_arty_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
);
UUT : arty_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_RGBLED2 => O_RGBLED2,
O_RGBLED3 => O_RGBLED3,
A_VPWRN => (others=>'0'),
A_VPWRP => (others=>'0')
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => '0', -- FIXME: or 1 ???
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => open,
TXCTS_N => '0'
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;

6
rtl/bplib/arty/tb/tb_arty_core.vbom Normal file
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@@ -0,0 +1,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simbus.vhd
# components
# design
tb_arty_core.vhd

70
rtl/bplib/arty/tb/tb_arty_core.vhd Normal file
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@@ -0,0 +1,70 @@
-- $Id: tb_arty_core.vhd 726 2016-01-31 23:02:31Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_arty_core - sim
-- Description: Test bench for arty - core device handling
--
-- Dependencies: -
--
-- To test: generic, any arty target
--
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-01-31 726 1.0 Initial version (derived from tb_basys3_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_arty_core is
port (
I_SWI : out slv4; -- arty switches
I_BTN : out slv4 -- arty buttons
);
end tb_arty_core;
architecture sim of tb_arty_core is
signal R_SWI : slv4 := (others=>'0');
signal R_BTN : slv4 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;

4
rtl/bplib/basys3/basys3_pclk.xdc
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@@ -1,10 +1,10 @@
# -*- tcl -*-
# $Id: basys3_pclk.xdc 639 2015-01-30 18:12:19Z mueller $
# $Id: basys3_pclk.xdc 726 2016-01-31 23:02:31Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Primary clocks for Basys3
# Primary clocks for Digilent Basys3
#
# Revision History:
# Date Rev Version Comment

4
rtl/bplib/basys3/basys3_pins.xdc
View File

@@ -1,10 +1,10 @@
# -*- tcl -*-
# $Id: basys3_pins.xdc 640 2015-02-01 09:56:53Z mueller $
# $Id: basys3_pins.xdc 726 2016-01-31 23:02:31Z mueller $
#
# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Pin locks for Basys 3 core functionality
# Pin locks for Digilent Basys 3 core functionality
# - USB UART
# - human I/O (switches, buttons, leds, display)
#

4
rtl/bplib/basys3/basys3lib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: basys3lib.vhd 635 2015-01-16 17:37:08Z mueller $
-- $Id: basys3lib.vhd 726 2016-01-31 23:02:31Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -12,7 +12,7 @@
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: basys3ib
-- Package Name: basys3lib
-- Description: Basys 3 components
--
-- Dependencies: -

10
rtl/bplib/basys3/tb/tb_basys3.vbom
View File

@@ -5,8 +5,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../basys3lib.vhd
../../../vlib/simlib/simlib.vhd
@@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_basys3_core.vbom
../../../vlib/serport/serport_master.vbom
${basys3_aif := basys3_dummy.vbom}
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${basys3_aif := basys3_dummy.vbom}
# design
tb_basys3.vhd
@top:tb_basys3

27
rtl/bplib/basys3/tb/tb_basys3.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_basys3.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_basys3.vhd 734 2016-02-20 22:43:20Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -17,19 +17,22 @@
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- rlink/tbcore/tbcore_rlink
-- xlib/tb/s7_cmt_sfs_tb
-- tb_basys3_core
-- serport/serport_master
-- serport/tb/serport_master_tb
-- basys3_aif [UUT]
--
-- To test: generic, any basys3_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2014.4; ghdl 0.31
-- Tool versions: viv 2014.4-2015.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 734 1.1.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.1.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.1.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.1 use serport_master instead of serport_uart_rxtx
-- 2015-02-18 648 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
@@ -42,8 +45,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.basys3lib.all;
use work.simlib.all;
@@ -97,7 +98,7 @@ begin
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
CLKGEN_COM : entity work.s7_cmt_sfs_tb
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
@@ -105,7 +106,7 @@ begin
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
@@ -114,7 +115,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
@@ -125,7 +126,7 @@ begin
TX_ENA => RXVAL
);
N4CORE : entity work.tb_basys3_core
B3CORE : entity work.tb_basys3_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN
@@ -143,7 +144,7 @@ begin
O_SEG_N => O_SEG_N
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

3
rtl/bplib/basys3/tb/tb_basys3_core.vbom
View File

@@ -1,9 +1,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
# design
tb_basys3_core.vhd

3
rtl/bplib/basys3/tb/tb_basys3_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_basys3_core.vhd 648 2015-02-20 20:16:21Z mueller $
-- $Id: tb_basys3_core.vhd 724 2016-01-03 22:53:53Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -33,7 +33,6 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_basys3_core is

6
rtl/bplib/bpgen/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -14,7 +14,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -24,7 +24,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

63
rtl/bplib/bpgen/bpgenlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: bpgenlib.vhd 637 2015-01-25 18:36:40Z mueller $
-- $Id: bpgenlib.vhd 737 2016-02-28 09:07:18Z mueller $
--
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Generic Board/Part components
--
-- Dependencies: -
-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31
-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-27 737 1.2 add rgbdrv entity
-- 2015-01-24 637 1.1.2 add generics to sn_humanio and sn_7segctl
-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob
-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib
@@ -180,4 +181,60 @@ component sn_humanio_demu is -- human i/o handling: swi,btn,led only
);
end component;
component rgbdrv_master is -- rgbled driver: master
generic (
DWIDTH : positive := 8); -- dimmer width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
RGBCNTL : out slv3; -- rgb control
DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control
);
end component;
component rgbdrv_analog is -- rgbled driver: analog channel
generic (
DWIDTH : positive := 8); -- dimmer width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
DIMR : in slv(DWIDTH-1 downto 0); -- dim red
DIMG : in slv(DWIDTH-1 downto 0); -- dim green
DIMB : in slv(DWIDTH-1 downto 0); -- dim blue
O_RGBLED : out slv3 -- pad-o: rgb led
);
end component;
component rgbdrv_binary is -- rgbled driver: binary channel
generic (
DWIDTH : positive := 8); -- dimmer width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
DIM : in slv(DWIDTH-1 downto 0); -- dim
ENARGB : in slv3; -- enable [0] red [1] green [2] blue
O_RGBLED : out slv3 -- pad-o: rgb led
);
end component;
component rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
DATR : in slv4; -- red data
DATG : in slv4; -- green data
DATB : in slv4; -- blue data
O_RGBLED0 : out slv3; -- pad-o: rgb led 0
O_RGBLED1 : out slv3; -- pad-o: rgb led 1
O_RGBLED2 : out slv3; -- pad-o: rgb led 2
O_RGBLED3 : out slv3 -- pad-o: rgb led 3
);
end component;
end package bpgenlib;

22
rtl/bplib/bpgen/bpgenrbuslib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: bpgenrbuslib.vhd 637 2015-01-25 18:36:40Z mueller $
-- $Id: bpgenrbuslib.vhd 734 2016-02-20 22:43:20Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Generic Board/Part components using rbus
--
-- Dependencies: -
-- Tool versions: ise 12.1-14.7; viv 2014.4; ghdl 0.26-0.31
-- Tool versions: ise 12.1-14.7; viv 2014.4-2015.4; ghdl 0.26-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 734 1.3 add rgbdrv_analog_rbus
-- 2015-01-25 637 1.2 add generics to sn_humanio_rbus
-- 2014-08-15 583 1.1 rb_mreq addr now 16 bit
-- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib)
@@ -103,4 +104,19 @@ component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
);
end component;
component rgbdrv_analog_rbus is -- rgb analog from rbus
generic (
DWIDTH : positive := 8; -- dimmer width
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
O_RGBLED : out slv3 -- pad-o: rgb led
);
end component;
end package bpgenrbuslib;

7
rtl/bplib/bpgen/rgbdrv_3x4mux.vbom Normal file
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@@ -0,0 +1,7 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
# components
../../vlib/xlib/iob_reg_o_gen.vbom
# design
rgbdrv_3x4mux.vhd

120
rtl/bplib/bpgen/rgbdrv_3x4mux.vhd Normal file
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@@ -0,0 +1,120 @@
-- $Id: rgbdrv_3x4mux.vhd 737 2016-02-28 09:07:18Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_3x4mux - syn
-- Description: rgbled driver: mux three 4bit inputs
--
-- Dependencies: xlib/iob_reg_o_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-27 737 1.0 Initial version (re-write, new logic)
-- 2016-02-20 734 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity rgbdrv_3x4mux is -- rgbled driver: mux three 4bit inputs
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
DATR : in slv4; -- red data
DATG : in slv4; -- green data
DATB : in slv4; -- blue data
O_RGBLED0 : out slv3; -- pad-o: rgb led 0
O_RGBLED1 : out slv3; -- pad-o: rgb led 1
O_RGBLED2 : out slv3; -- pad-o: rgb led 2
O_RGBLED3 : out slv3 -- pad-o: rgb led 3
);
end rgbdrv_3x4mux;
architecture syn of rgbdrv_3x4mux is
signal R_LED : slv4 := "0001";
signal R_COL : slv3 := "001";
signal R_DIM : slbit := '1';
signal RGB0 : slv3 := (others=>'0');
signal RGB1 : slv3 := (others=>'0');
signal RGB2 : slv3 := (others=>'0');
signal RGB3 : slv3 := (others=>'0');
begin
IOB_RGB0: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB0, PAD => O_RGBLED0);
IOB_RGB1: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB1, PAD => O_RGBLED1);
IOB_RGB2: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB2, PAD => O_RGBLED2);
IOB_RGB3: iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => RGB3, PAD => O_RGBLED3);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_LED <= "0001";
R_COL <= "001";
R_DIM <= '1';
else
if CE_USEC = '1' then
R_DIM <= not R_DIM;
if R_DIM = '1' then
R_COL <= R_COL(1) & R_COL(0) & R_COL(2);
if R_COL(2) = '1' then
R_LED <= R_LED(2) & R_LED(1) & R_LED(0) & R_LED(3);
end if;
end if;
end if;
end if;
end if;
end process proc_regs;
proc_mux: process (R_DIM, R_COL, R_LED, DATR, DATG, DATB)
begin
RGB0(0) <= (not R_DIM) and R_COL(0) and R_LED(0) and DATR(0);
RGB0(1) <= (not R_DIM) and R_COL(1) and R_LED(0) and DATG(0);
RGB0(2) <= (not R_DIM) and R_COL(2) and R_LED(0) and DATB(0);
RGB1(0) <= (not R_DIM) and R_COL(0) and R_LED(1) and DATR(1);
RGB1(1) <= (not R_DIM) and R_COL(1) and R_LED(1) and DATG(1);
RGB1(2) <= (not R_DIM) and R_COL(2) and R_LED(1) and DATB(1);
RGB2(0) <= (not R_DIM) and R_COL(0) and R_LED(2) and DATR(2);
RGB2(1) <= (not R_DIM) and R_COL(1) and R_LED(2) and DATG(2);
RGB2(2) <= (not R_DIM) and R_COL(2) and R_LED(2) and DATB(2);
RGB3(0) <= (not R_DIM) and R_COL(0) and R_LED(3) and DATR(3);
RGB3(1) <= (not R_DIM) and R_COL(1) and R_LED(3) and DATG(3);
RGB3(2) <= (not R_DIM) and R_COL(2) and R_LED(3) and DATB(3);
end process proc_mux;
end syn;

7
rtl/bplib/bpgen/rgbdrv_analog.vbom Normal file
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@@ -0,0 +1,7 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/xlib/xlib.vhd
# components
../../vlib/xlib/iob_reg_o_gen.vbom
# design
rgbdrv_analog.vhd

98
rtl/bplib/bpgen/rgbdrv_analog.vhd Normal file
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@@ -0,0 +1,98 @@
-- $Id: rgbdrv_analog.vhd 734 2016-02-20 22:43:20Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_analog - syn
-- Description: rgbled driver: analog channel
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 734 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity rgbdrv_analog is -- rgbled driver: analog channel
generic (
DWIDTH : positive := 8); -- dimmer width
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
DIMR : in slv(DWIDTH-1 downto 0); -- dim red
DIMG : in slv(DWIDTH-1 downto 0); -- dim green
DIMB : in slv(DWIDTH-1 downto 0); -- dim blue
O_RGBLED : out slv3 -- pad-o: rgb led
);
end rgbdrv_analog;
architecture syn of rgbdrv_analog is
signal R_RGB : slv3 := (others=>'0'); -- state registers
signal N_RGB : slv3 := (others=>'0'); -- next value state regs
begin
IOB_RGB : iob_reg_o_gen
generic map (DWIDTH => 3)
port map (CLK => CLK, CE => '1', DO => R_RGB, PAD => O_RGBLED);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_RGB <= (others=>'0');
else
R_RGB <= N_RGB;
end if;
end if;
end process proc_regs;
proc_next: process (R_RGB, RGBCNTL, DIMCNTL, DIMR, DIMG, DIMB)
variable irgb : slv3 := (others=>'0');
begin
irgb := (others=>'0');
if unsigned(DIMCNTL) < unsigned(DIMR) then
irgb(0) := RGBCNTL(0);
end if;
if unsigned(DIMCNTL) < unsigned(DIMG) then
irgb(1) := RGBCNTL(1);
end if;
if unsigned(DIMCNTL) < unsigned(DIMB) then
irgb(2) := RGBCNTL(2);
end if;
N_RGB <= irgb;
end process proc_next;
end syn;

8
rtl/bplib/bpgen/rgbdrv_analog_rbus.vbom Normal file
View File

@@ -0,0 +1,8 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
bpgenlib.vbom
# components
rgbdrv_analog.vbom
# design
rgbdrv_analog_rbus.vhd

193
rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd Normal file
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@@ -0,0 +1,193 @@
-- $Id: rgbdrv_analog_rbus.vhd 734 2016-02-20 22:43:20Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_analog_rbus - syn
-- Description: rgb analog from rbus
--
-- Dependencies: bpgen/rgbdrv_analog
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2015.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 724 1.0 Initial version
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
-- 00 red r/w/- red channel
-- 01 green r/w/- green channel
-- 10 blue r/w/- blue channel
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.bpgenlib.all;
-- ----------------------------------------------------------------------------
entity rgbdrv_analog_rbus is -- rgb analog from rbus
generic (
DWIDTH : positive := 8; -- dimmer width
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
RGBCNTL : in slv3; -- rgb control
DIMCNTL : in slv(DWIDTH-1 downto 0);-- dim control
O_RGBLED : out slv3 -- pad-o: rgb led
);
end rgbdrv_analog_rbus;
architecture syn of rgbdrv_analog_rbus is
type regs_type is record
rbsel : slbit; -- rbus select
dimr : slv(DWIDTH-1 downto 0); -- dim red
dimg : slv(DWIDTH-1 downto 0); -- dim green
dimb : slv(DWIDTH-1 downto 0); -- dim blue
end record regs_type;
constant dimzero : slv(DWIDTH-1 downto 0) := (others=>'0');
constant regs_init : regs_type := (
'0', -- rbsel
dimzero, -- dimr
dimzero, -- dimg
dimzero -- dimb
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
subtype dim_rbf is integer range DWIDTH-1 downto 0;
constant rbaddr_dimr: slv2 := "00"; -- 0 r/w/-
constant rbaddr_dimg: slv2 := "01"; -- 1 r/w/-
constant rbaddr_dimb: slv2 := "10"; -- 2 r/w/-
begin
assert DWIDTH<=16
report "assert (DWIDTH<=16)"
severity failure;
RGB : rgbdrv_analog
generic map (
DWIDTH => DWIDTH)
port map (
CLK => CLK,
RESET => RESET,
RGBCNTL => RGBCNTL,
DIMCNTL => DIMCNTL,
DIMR => R_REGS.dimr,
DIMG => R_REGS.dimg,
DIMB => R_REGS.dimb,
O_RGBLED => O_RGBLED
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
end if;
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_dimr =>
irb_dout(dim_rbf) := r.dimr;
if RB_MREQ.we = '1' then
n.dimr := RB_MREQ.din(dim_rbf);
end if;
when rbaddr_dimg =>
irb_dout(dim_rbf) := r.dimg;
if RB_MREQ.we = '1' then
n.dimg := RB_MREQ.din(dim_rbf);
end if;
when rbaddr_dimb =>
irb_dout(dim_rbf) := r.dimb;
if RB_MREQ.we = '1' then
n.dimb := RB_MREQ.din(dim_rbf);
end if;
when others =>
irb_ack := '0';
end case;
end if;
N_REGS <= n;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;

5
rtl/bplib/bpgen/rgbdrv_master.vbom Normal file
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@@ -0,0 +1,5 @@
# libs
../../vlib/slvtypes.vhd
# components
# design
rgbdrv_master.vhd

103
rtl/bplib/bpgen/rgbdrv_master.vhd Normal file
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@@ -0,0 +1,103 @@
-- $Id: rgbdrv_master.vhd 734 2016-02-20 22:43:20Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rgbdrv_master - syn
-- Description: rgbled driver: master
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 734 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity rgbdrv_master is -- rgbled driver: master
generic (
DWIDTH : positive := 8); -- dimmer width (must be >= 1)
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_USEC : in slbit; -- 1 us clock enable
RGBCNTL : out slv3; -- rgb control
DIMCNTL : out slv(DWIDTH-1 downto 0) -- dim control
);
end rgbdrv_master;
architecture syn of rgbdrv_master is
type regs_type is record
rgbena : slv3; -- rgb enables
dimcnt : slv(DWIDTH-1 downto 0); -- dim counter
end record regs_type;
constant dimones : slv(DWIDTH-1 downto 0) := (others=>'1');
constant regs_init : regs_type := (
"001", -- rgbena
dimones -- dimcnt
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_USEC)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if CE_USEC = '1' then
n.dimcnt := slv(unsigned(r.dimcnt) + 1);
if r.dimcnt = dimones then
n.rgbena(2) := r.rgbena(1);
n.rgbena(1) := r.rgbena(0);
n.rgbena(0) := r.rgbena(2);
end if;
end if;
N_REGS <= n;
end process proc_next;
RGBCNTL <= R_REGS.rgbena;
DIMCNTL <= R_REGS.dimcnt;
end syn;

4
rtl/bplib/bpgen/sn_humanio.vhd
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@@ -1,4 +1,4 @@
-- $Id: sn_humanio.vhd 637 2015-01-25 18:36:40Z mueller $
-- $Id: sn_humanio.vhd 731 2016-02-14 21:07:14Z mueller $
--
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -93,7 +93,7 @@ begin
generic map (DWIDTH => 8)
port map (CLK => CLK, CE => '1', DO => N_SEG_N, PAD => O_SEG_N);
HIO : bp_swibtnled
HIO : bp_swibtnled
generic map (
SWIDTH => SWIDTH,
BWIDTH => BWIDTH,

6
rtl/bplib/fx2lib/Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -23,7 +23,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

6
rtl/bplib/fx2rlink/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -22,7 +22,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

4
rtl/bplib/issi/Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -12,7 +12,7 @@ clean : ghdl_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
#
VBOM_all = $(wildcard *.vbom)
#

6
rtl/bplib/nexys2/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys2
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -22,7 +22,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

10
rtl/bplib/nexys2/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -17,7 +17,7 @@ EXE_all += tb_nexys2_fusp_cuff_dummy
ifndef XTW_BOARD
XTW_BOARD=nexys2
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

3
rtl/bplib/nexys2/tb/tb_nexys2_core.vbom
View File

@@ -1,10 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
../../micron/mt45w8mw16b.vbom
# design
tb_nexys2_core.vhd

3
rtl/bplib/nexys2/tb/tb_nexys2_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys2_core.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nexys2_core.vhd 724 2016-01-03 22:53:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -36,7 +36,6 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_nexys2_core is

8
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vbom
View File

@@ -5,8 +5,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
@@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_master.vbom
${nexys2_fusp_aif := nexys2_fusp_dummy.vbom}
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys2_fusp_aif := nexys2_fusp_dummy.vbom}
# design
tb_nexys2_fusp.vhd
@top:tb_nexys2_fusp

16
rtl/bplib/nexys2/tb/tb_nexys2_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_nexys2_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
--
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,9 @@
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink
-- rlink/tbcore/tbcore_rlink
-- tb_nexys2_core
-- serport/serport_master
-- serport/tb/serport_master_tb
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
@@ -30,6 +30,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 3.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 3.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 3.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.2 new system clock scheme, new tbcore_rlink iface
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
@@ -49,8 +51,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
@@ -143,7 +143,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
@@ -199,7 +199,7 @@ begin
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

8
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vbom
View File

@@ -5,8 +5,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys2lib.vhd
../../../vlib/simlib/simlib.vhd
@@ -15,12 +13,12 @@ ${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
tb_nexys2_core.vbom
../../../vlib/serport/serport_master.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom}
@uut: ${nexys2_fusp_cuff_aif := nexys2_fusp_cuff_dummy.vbom}
# design
tb_nexys2_fusp_cuff.vhd
@top:tb_nexys2_fusp_cuff

16
rtl/bplib/nexys2/tb/tb_nexys2_fusp_cuff.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys2_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_nexys2_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,9 @@
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- rlink/tb/tbcore_rlink_dcm
-- rlink/tbcore/tbcore_rlink_dcm
-- tb_nexys2_core
-- serport/serport_master
-- serport/tb/serport_master_tb
-- fx2lib/tb/fx2_2fifo_core
-- nexys2_fusp_cuff_aif [UUT]
--
@@ -31,6 +31,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-01-03 469 1.1 add fx2 model and data path
-- 2013-01-01 467 1.0 Initial version (derived from tb_nexys2_fusp)
@@ -44,8 +46,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys2lib.all;
use work.simlib.all;
@@ -161,7 +161,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
@@ -223,7 +223,7 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

10
rtl/bplib/nexys3/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -11,7 +11,7 @@ EXE_all += tb_nexys3_fusp_cuff_dummy
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -23,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

3
rtl/bplib/nexys3/tb/tb_nexys3_core.vbom
View File

@@ -1,10 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
../../micron/mt45w8mw16b.vbom
# design
tb_nexys3_core.vhd

3
rtl/bplib/nexys3/tb/tb_nexys3_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_core.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_nexys3_core.vhd 724 2016-01-03 22:53:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -33,7 +33,6 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_nexys3_core is

8
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
View File

@@ -5,8 +5,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
@@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_master.vbom
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}
# design
tb_nexys3_fusp.vhd
@top:tb_nexys3_fusp

16
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys3_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_nexys3_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
--
-- Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,9 @@
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- rlink/tbcore/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_master
-- serport/tb/serport_master_tb
-- nexys3_fusp_aif [UUT]
--
-- To test: generic, any nexys3_fusp_aif target
@@ -30,6 +30,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
@@ -44,8 +46,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
@@ -143,7 +143,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
@@ -200,7 +200,7 @@ begin
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

8
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
View File

@@ -5,8 +5,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys3lib.vhd
../../../vlib/simlib/simlib.vhd
@@ -15,12 +13,12 @@ ${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_master.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom
${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom}
@uut: ${nexys3_fusp_cuff_aif := nexys3_fusp_cuff_dummy.vbom}
# design
tb_nexys3_fusp_cuff.vhd
@top:tb_nexys3_fusp_cuff

16
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys3_fusp_cuff.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_nexys3_fusp_cuff.vhd 730 2016-02-13 16:22:03Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,9 +18,9 @@
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- rlink/tbcore/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_master
-- serport/tb/serport_master_tb
-- fx2lib/tb/fx2_2fifo_core
-- nexys3_fusp_cuff_aif [UUT]
--
@@ -31,6 +31,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
@@ -45,8 +47,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys3lib.all;
use work.simlib.all;
@@ -166,7 +166,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
@@ -229,7 +229,7 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

3
rtl/bplib/nexys4/nexys4_pins.xdc
View File

@@ -1,5 +1,5 @@
# -*- tcl -*-
# $Id: nexys4_pins.xdc 643 2015-02-07 17:41:53Z mueller $
# $Id: nexys4_pins.xdc 726 2016-01-31 23:02:31Z mueller $
#
# Pin locks for Nexys 4 core functionality
# - USB UART
@@ -94,6 +94,7 @@ set_property SLEW SLOW [get_ports {O_LED[*]}]
set_property PACKAGE_PIN k5 [get_ports {O_RGBLED0[0]}]
set_property PACKAGE_PIN f13 [get_ports {O_RGBLED0[1]}]
set_property PACKAGE_PIN f6 [get_ports {O_RGBLED0[2]}]
set_property PACKAGE_PIN k6 [get_ports {O_RGBLED1[0]}]
set_property PACKAGE_PIN h6 [get_ports {O_RGBLED1[1]}]
set_property PACKAGE_PIN l16 [get_ports {O_RGBLED1[2]}]

1
rtl/bplib/nexys4/tb/.cvsignore
View File

@@ -2,4 +2,3 @@ tb_nexys4_dummy
tb_nexys4_cram_dummy
nexys4_dummy.ucf
nexys4_cram_dummy.ucf
*.dep_ucf_cpp

30
rtl/bplib/nexys4/tb/Makefile Normal file
View File

@@ -0,0 +1,30 @@
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2016-01-03 724 1.0 Initial version
#
EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy
#
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4.mk
#
.PHONY : all all_ssim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
#
clean : viv_clean ghdl_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
endif
#

11
rtl/bplib/nexys4/tb/Makefile.ise
View File

@@ -1,4 +1,5 @@
# $Id: Makefile.ise 648 2015-02-20 20:16:21Z mueller $
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -12,7 +13,7 @@ EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -24,9 +25,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

10
rtl/bplib/nexys4/tb/tb_nexys4.vbom
View File

@@ -5,8 +5,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4lib.vhd
../../../vlib/simlib/simlib.vhd
@@ -15,11 +13,11 @@ ${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_nexys4_core.vbom
../../../vlib/serport/serport_master.vbom
${nexys4_aif := nexys4_dummy.vbom}
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys4_aif := nexys4_dummy.vbom}
# design
tb_nexys4.vhd
@top:tb_nexys4

23
rtl/bplib/nexys4/tb/tb_nexys4.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys4.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_nexys4.vhd 734 2016-02-20 22:43:20Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -17,10 +17,10 @@
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- rlink/tbcore/tbcore_rlink
-- xlib/tb/s7_cmt_sfs_tb
-- tb_nexys4_core
-- serport/serport_master
-- serport/tb/serport_master_tb
-- nexys4_aif [UUT]
--
-- To test: generic, any nexys4_aif target
@@ -30,6 +30,9 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 734 1.3.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2015-02-06 643 1.2 factor out memory
-- 2015-02-01 641 1.1 separate I_BTNRST_N
@@ -45,8 +48,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
@@ -105,7 +106,7 @@ begin
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
CLKGEN_COM : entity work.s7_cmt_sfs_tb
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
@@ -113,7 +114,7 @@ begin
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
@@ -122,7 +123,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
@@ -157,7 +158,7 @@ begin
O_SEG_N => O_SEG_N
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

3
rtl/bplib/nexys4/tb/tb_nexys4_core.vbom
View File

@@ -1,9 +1,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
# design
tb_nexys4_core.vhd

3
rtl/bplib/nexys4/tb/tb_nexys4_core.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys4_core.vhd 643 2015-02-07 17:41:53Z mueller $
-- $Id: tb_nexys4_core.vhd 724 2016-01-03 22:53:53Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -35,7 +35,6 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_nexys4_core is

10
rtl/bplib/nexys4/tb/tb_nexys4_cram.vbom
View File

@@ -5,8 +5,6 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4lib.vhd
../../../vlib/simlib/simlib.vhd
@@ -15,12 +13,12 @@ ${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_nexys4_core.vbom
../../micron/mt45w8mw16b.vbom
../../../vlib/serport/serport_master.vbom
${nexys4_cram_aif := nexys4_cram_dummy.vbom}
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${nexys4_cram_aif := nexys4_cram_dummy.vbom}
# design
tb_nexys4_cram.vhd
@top:tb_nexys4_cram

23
rtl/bplib/nexys4/tb/tb_nexys4_cram.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys4_cram.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_nexys4_cram.vhd 734 2016-02-20 22:43:20Z mueller $
--
-- Copyright 2013-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -17,10 +17,10 @@
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- xlib/s7_cmt_sfs
-- rlink/tbcore/tbcore_rlink
-- xlib/tb/s7_cmt_sfs_tb
-- tb_nexys4_core
-- serport/serport_master
-- serport/tb/serport_master_tb
-- nexys4_cram_aif [UUT]
-- vlib/parts/micron/mt45w8mw16b
--
@@ -31,6 +31,9 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-20 734 1.2.3 use s7_cmt_sfs_tb to avoid xsim conflict
-- 2016-02-13 730 1.2.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.2.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.2 use serport_master instead of serport_uart_rxtx
-- 2015-02-01 641 1.1 separate I_BTNRST_N
-- 2013-09-28 535 1.0.1 use proper clock manager
@@ -45,8 +48,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.xlib.all;
use work.nexys4lib.all;
use work.simlib.all;
@@ -115,7 +116,7 @@ begin
CLK_STOP => CLK_STOP
);
CLKGEN_COM : s7_cmt_sfs
CLKGEN_COM : entity work.s7_cmt_sfs_tb
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
@@ -123,7 +124,7 @@ begin
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
@@ -132,7 +133,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
CLK_STOP => CLK_STOP,
@@ -192,7 +193,7 @@ begin
DATA => IO_MEM_DATA
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

6
rtl/bplib/nxcramlib/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -12,7 +12,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -22,7 +22,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

3
rtl/bplib/nxcramlib/tb/.cvsignore
View File

@@ -1,5 +1,2 @@
tb_nx_cram_memctl_as
tb_nx_cram_memctl_as_[sft]sim
tb_nx_cram_memctl_as_ISim
tb_nx_cram_memctl_as_ISim_[sft]sim
tb_nx_cram_memctl_stim

10
rtl/bplib/nxcramlib/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -11,7 +11,7 @@ EXE_all = tb_nx_cram_memctl_as
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -23,9 +23,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

2
rtl/bplib/nxcramlib/tb/tb_nx_cram_memctl.vbom
View File

@@ -9,7 +9,7 @@
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../micron/mt45w8mw16b.vbom
${uut := tbd_nx_cram_memctl_as.vbom}
@uut: ${uut := tbd_nx_cram_memctl_as.vbom}
# design
tb_nx_cram_memctl.vhd
@top:tb_nx_cram_memctl

6
rtl/bplib/s3board/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=s3board
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -23,7 +23,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

9
rtl/bplib/s3board/tb/.cvsignore
View File

@@ -1,13 +1,4 @@
tb_s3board_dummy
tb_s3board_dummy_[sft]sim
tb_s3board_dummy_ISim
tb_s3board_dummy_ISim_[sft]sim
tb_s3board_fusp_dummy
rlink_cext_fifo_rx
rlink_cext_fifo_tx
rlink_cext_conf
tb_s3_sram_memctl
tb_s3_sram_memctl_[sft]sim
tb_s3_sram_memctl_stim
tb_s3_sram_memctl_ISim
tb_s3_sram_memctl_ISim_[sft]sim

10
rtl/bplib/s3board/tb/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -17,7 +17,7 @@ EXE_all += tb_s3_sram_memctl
ifndef XTW_BOARD
XTW_BOARD=s3board
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
@@ -29,9 +29,9 @@ clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include $(RETROBASE)/rtl/make_ise/generic_ghdl.mk
include $(RETROBASE)/rtl/make_ise/generic_isim.mk
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#

3
rtl/bplib/s3board/tb/tb_s3board_core.vbom
View File

@@ -1,10 +1,7 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/serport/serport_uart_rx.vbom
../../../vlib/serport/serport_uart_tx.vbom
../../issi/is61lv25616al.vbom
# design
tb_s3board_core.vhd

5
rtl/bplib/s3board/tb/tb_s3board_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_s3board_core.vhd 649 2015-02-21 21:10:16Z mueller $
-- $Id: tb_s3board_core.vhd 724 2016-01-03 22:53:53Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -35,7 +35,6 @@ use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.simbus.all;
entity tb_s3board_core is

8
rtl/bplib/s3board/tb/tb_s3board_fusp.vbom
View File

@@ -5,18 +5,16 @@
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/rlink/tb/rlinktblib.vhd
../../../vlib/serport/serportlib.vbom
../s3boardlib.vbom
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
tb_s3board_core.vbom
../../../vlib/serport/serport_master.vbom
${s3board_fusp_aif := s3board_fusp_dummy.vbom}
../../../vlib/serport/tb/serport_master_tb.vbom
@uut: ${s3board_fusp_aif := s3board_fusp_dummy.vbom}
# design
tb_s3board_fusp.vhd
@top:tb_s3board_fusp

16
rtl/bplib/s3board/tb/tb_s3board_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_s3board_fusp.vhd 666 2015-04-12 21:17:54Z mueller $
-- $Id: tb_s3board_fusp.vhd 730 2016-02-13 16:22:03Z mueller $
--
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -17,10 +17,10 @@
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tb/tbcore_rlink
-- rlink/tbcore/tbcore_rlink
-- tb_s3board_core
-- s3board_fusp_aif [UUT]
-- serport/serport_master
-- serport/tb/serport_master_tb
--
-- To test: generic, any s3board_fusp_aif target
--
@@ -28,6 +28,8 @@
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2016-02-13 730 1.3.2 direct instantiation of tbcore_rlink
-- 2016-01-03 724 1.3.1 use serport/tb/serport_master_tb
-- 2015-04-12 666 1.3 use serport_master instead of serport_uart_rxtx
-- 2011-12-23 444 3.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-19 427 3.0.1 now numeric_std clean
@@ -47,8 +49,6 @@ use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serportlib.all;
use work.s3boardlib.all;
use work.simlib.all;
use work.simbus.all;
@@ -122,7 +122,7 @@ begin
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
TBCORE : tbcore_rlink
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLK,
CLK_STOP => CLK_STOP,
@@ -169,7 +169,7 @@ begin
O_FUSP_TXD => O_FUSP_TXD
);
SERMSTR : serport_master
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (

6
rtl/bplib/sysmon/sysmon_rbus_core.vbom Normal file
View File

@@ -0,0 +1,6 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
# components
# design
sysmon_rbus_core.vhd

372
rtl/bplib/sysmon/sysmon_rbus_core.vhd Normal file
View File

@@ -0,0 +1,372 @@
-- $Id: sysmon_rbus_core.vhd 741 2016-03-12 23:49:03Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sysmon_rbus_core - syn
-- Description: SYSMON interface to rbus (generic)
--
-- Dependencies: -
--
-- Test bench: -
--
-- Target Devices: generic (all with SYSMON or XADC)
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
-- - in general 1-to-1 mapping to sysmon/xadc address space
-- --> see function in sysmon/xadc user guide
-- - 8 addresses are implemented on the controller (base is ibase, default x"78")
-- --> see function below
--
-- Addr Bits Name r/w/f Function
-- 000 cntl -/-/f cntl
-- 15 reset -/-/f reset SYSMON
-- 001 stat r/w/- stat
-- 3 jlock r/c/- JTAGLOCKED seen
-- 2 jmod r/c/- JTAGMODIFIED seen
-- 1 jbusy r/c/- JTAGBUSY seen
-- 0 ot r/c/- OT seen
-- 010 almh r/w/- alm history
-- *:00 alm r/c/- ALM(*:0) seen
-- 011 -/-/- <unused>
-- 100 temp r/-/- current temp value
-- 101 alm r/-/- current alm value
-- *:00 alm r/-/- alm(*:0)
-- 110 -/-/- <unused>
-- 111 eos r/-/- eos counter
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmon_rbus_core is -- SYSMON interface to rbus
generic (
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SM_DEN : out slbit; -- sysmon: drp enable
SM_DWE : out slbit; -- sysmon: drp write enable
SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address
SM_DI : out slv16; -- sysmon: data input
SM_DO : in slv16; -- sysmon: data output
SM_DRDY : in slbit; -- sysmon: data ready
SM_EOS : in slbit; -- sysmon: end of scan
SM_RESET : out slbit; -- sysmon: reset
SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms
SM_OT : in slbit; -- sysmon: overtemperature
SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY
SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED
SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED
TEMP : out slv(TEWIDTH-1 downto 0) -- die temp
);
end sysmon_rbus_core;
architecture syn of sysmon_rbus_core is
type state_type is (
s_init, -- init: wait for jtaglocked down
s_idle, -- idle: dispatch
s_wait, -- wait: wait on drdy
s_twait -- twait: wait on drdy of temp read
);
type regs_type is record
rbsel : slbit; -- rbus select
state : state_type; -- state
eoscnt : slv16; -- eos counter
stat_ot : slbit; -- stat: ot
stat_jlock : slbit; -- stat: jtag locked
stat_jmod : slbit; -- stat: jtag modified
stat_jbusy : slbit; -- stat: jtag busy
almh : slv(ALWIDTH-1 downto 0); -- almh
temp : slv(TEWIDTH-1 downto 0); -- temp value
tpend : slbit; -- temp pending
end record regs_type;
constant regs_init : regs_type := (
'0', -- rbsel
s_idle, -- state
(others=>'0'), -- eoscnt
'0','0','0','0', -- stat_ot, stat_j*
slv(to_unsigned(0,ALWIDTH)), -- almh
slv(to_unsigned(0,TEWIDTH)), -- temp
'0' -- tpend
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
-- only internal regs have names, only 3 LSB in constant
constant rbaddr_cntl: slv3 := "000"; -- 0 -/-/f
constant rbaddr_stat: slv3 := "001"; -- 1 r/w/-
constant rbaddr_almh: slv3 := "010"; -- 2 r/w/-
constant rbaddr_temp: slv3 := "100"; -- 4 r/-/-
constant rbaddr_alm: slv3 := "101"; -- 5 r/-/-
constant rbaddr_eos: slv3 := "111"; -- 7 r/-/-
constant cntl_rbf_reset: integer := 15;
constant stat_rbf_jlock: integer := 3;
constant stat_rbf_jmod: integer := 2;
constant stat_rbf_jbusy: integer := 1;
constant stat_rbf_ot: integer := 0;
begin
assert DAWIDTH=7 or DAWIDTH=8
report "assert(DAWIDTH=7 or DAWIDTH=8): unsupported DAWIDTH"
severity failure;
assert ALWIDTH<=16
report "assert ALWIDTH<16: unsupported ALWIDTH"
severity failure;
assert TEWIDTH=10 or TEWIDTH=12
report "assert(TEWIDTH=10 or TEWIDTH=12): unsupported TEWIDTH"
severity failure;
assert IBASE(2 downto 0) = "000"
report "assert IBASE(2:0) = 000: invalid IBASE"
severity failure;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, SM_DO, SM_DRDY, SM_EOS, SM_ALM, SM_OT,
SM_JTAGLOCKED, SM_JTAGMODIFIED, SM_JTAGBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable irb_addr_ext : slbit := '0';
variable irb_addr_int : slbit := '0';
variable ism_den : slbit := '0';
variable ism_dwe : slbit := '0';
variable ism_daddr : slv(DAWIDTH-1 downto 0) := (others=>'0');
variable ism_reset : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
-- check for internal rbus controler register window
irb_addr_int := '0';
if RB_MREQ.addr(DAWIDTH-1 downto 3) = IBASE(DAWIDTH-1 downto 3) then
irb_addr_int := '1';
end if;
ism_den := '0';
ism_dwe := '0';
ism_daddr := RB_MREQ.addr(DAWIDTH-1 downto 0); -- default
ism_reset := '0';
-- handle EOS
if SM_EOS = '1' then
n.tpend := '1'; -- queue temp read
n.eoscnt := slv(unsigned(r.eoscnt) + 1); -- and count it
end if;
-- update stat and almh register fields
n.stat_ot := r.stat_ot or SM_OT;
n.stat_jlock := r.stat_jlock or SM_JTAGLOCKED;
n.stat_jmod := r.stat_jmod or SM_JTAGMODIFIED;
n.stat_jbusy := r.stat_jbusy or SM_JTAGBUSY;
n.almh := r.almh or SM_ALM;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' and RB_MREQ.addr(15 downto 7)=RB_ADDR(15 downto 7) then
n.rbsel := '1';
end if;
irb_ack := r.rbsel and irbena; -- ack all accesses
irb_busy := irb_ack; -- busy is default
-- internal state machine
case r.state is
when s_init => -- init: wait for jtaglocked down ----
if SM_JTAGLOCKED = '0' then
n.stat_jlock := '0'; -- clear status
n.state := s_idle; -- start working
end if;
when s_idle => -- idle: dispatch --------------------
if r.tpend = '1' then -- temp update pending ?
n.tpend := '0'; -- mark done
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := "0000000"; -- temp is reg 00h
ism_dwe := '0'; -- do read
ism_den := '1'; -- start drp cycle
n.state := s_twait;
end if;
elsif r.rbsel = '1' then -- rbus access ?
if irb_addr_int ='1' then -- internal controller regs
irb_busy := '0';
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl =>
if RB_MREQ.we = '1' then
ism_reset := RB_MREQ.din(cntl_rbf_reset);
end if;
when rbaddr_stat =>
if RB_MREQ.we = '1' then
n.stat_jlock := r.stat_jlock and
not RB_MREQ.din(stat_rbf_jlock);
n.stat_jmod := r.stat_jmod and
not RB_MREQ.din(stat_rbf_jmod);
n.stat_jbusy := r.stat_jbusy and
not RB_MREQ.din(stat_rbf_jbusy);
n.stat_ot := r.stat_ot and
not RB_MREQ.din(stat_rbf_ot);
end if;
when rbaddr_almh =>
if RB_MREQ.we = '1' then
n.almh := r.almh and not RB_MREQ.din(r.almh'range);
end if;
when rbaddr_temp =>
irb_err := RB_MREQ.we;
when rbaddr_alm =>
irb_err := RB_MREQ.we;
when rbaddr_eos =>
irb_err := RB_MREQ.we;
when others =>
irb_err := irbena;
end case;
else -- sysmon reg access
if irbena = '1' then
if SM_JTAGLOCKED = '0' then -- if not jlocked
ism_daddr := RB_MREQ.addr(ism_daddr'range);
ism_dwe := RB_MREQ.we;
ism_den := '1'; -- start drp cycle
n.state := s_wait;
else
irb_err := '1'; -- quit with error if jlocked
end if;
end if;
end if;
end if;
when s_wait => -- wait: wait on drdy ----------------
n.state := s_wait;
if SM_DRDY = '1' then
irb_busy := '0';
n.state := s_idle;
end if;
when s_twait => -- twait: wait on drdy of temp read --
n.state := s_twait;
if SM_DRDY = '1' then
n.temp := SM_DO(15 downto 16-TEWIDTH); -- take msb's
n.state := s_idle;
end if;
when others => null; -- <> ------------------------------
end case; -- case r.state
-- rbus output driver
if r.rbsel = '1' then
if irb_addr_int = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_stat =>
irb_dout(stat_rbf_jlock) := r.stat_jlock;
irb_dout(stat_rbf_jmod) := r.stat_jmod;
irb_dout(stat_rbf_jbusy) := r.stat_jbusy;
irb_dout(stat_rbf_ot) := r.stat_ot;
when rbaddr_almh =>
irb_dout(r.almh'range) := r.almh;
when rbaddr_temp =>
irb_dout(r.temp'range) := r.temp;
when rbaddr_alm =>
irb_dout(SM_ALM'range) := SM_ALM;
when rbaddr_eos =>
irb_dout := r.eoscnt;
when others =>
irb_dout := (others=>'0');
end case;
else
irb_dout := SM_DO;
end if;
end if;
N_REGS <= n;
SM_DEN <= ism_den;
SM_DWE <= ism_dwe;
SM_DADDR <= ism_daddr;
SM_DI <= RB_MREQ.din;
SM_RESET <= ism_reset;
TEMP <= r.temp;
RB_SRES <= rb_sres_init;
RB_SRES.ack <= irb_ack;
RB_SRES.busy <= irb_busy;
RB_SRES.err <= irb_err;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;

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# libs
../../vlib/slvtypes.vhd
sysmonrbuslib.vhd

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-- $Id: sysmonrbuslib.vhd 742 2016-03-13 14:40:19Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sysmonrbuslib
-- Description: generic (all with SYSMON or XADC)
--
-- Dependencies: -
-- Tool versions: viv2015.4; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-13 742 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package sysmonrbuslib is
subtype bv is bit_vector; -- vector
subtype bv16 is bit_vector(15 downto 0); -- 16 bit word
-- config reg #0 fields as bit masks (to be or'ed)
constant xadc_conf0_cavg: bv16 := x"8000"; -- 15 dis calib avr
constant xadc_conf0_avg_off: bv16 := x"0000"; -- 13:12 avr mode: off
constant xadc_conf0_avg_16: bv16 := x"1000"; -- " avr mode: 16 samples
constant xadc_conf0_avg_64: bv16 := x"2000"; -- " avr mode: 64 samples
constant xadc_conf0_avg_256: bv16 := x"3000"; -- " avr mode: 256 samples
constant xadc_conf0_mux: bv16 := x"0800"; -- 11 ena ext mux
constant xadc_conf0_bu: bv16 := x"0400"; -- 10 ena bipolar
constant xadc_conf0_ec: bv16 := x"0200"; -- 9 ena event mode
constant xadc_conf0_acq: bv16 := x"0100"; -- 8 ena inc settle
-- bit 4:0 holds channel select, not used, only for single channel mode
-- config reg #1 fields as bit masks (to be or'ed)
constant xadc_conf1_seq_default: bv16 := x"0000"; -- 15:12 seq mode: default
constant xadc_conf1_seq_spass: bv16 := x"1000"; -- " seq mode: single pass
constant xadc_conf1_seq_cont: bv16 := x"2000"; -- " seq mode: continuous
constant xadc_conf1_seq_schan: bv16 := x"3000"; -- " seq mode: single chan
constant xadc_conf1_dis_alm6: bv16 := x"0800"; -- 11 dis alm(6)
constant xadc_conf1_dis_alm5: bv16 := x"0400"; -- 10 dis alm(5)
constant xadc_conf1_dis_alm4: bv16 := x"0200"; -- 9 dis alm(4)
constant xadc_conf1_dis_alm3: bv16 := x"0100"; -- 8 dis alm(3)
constant xadc_conf1_cal3_supog: bv16 := x"0080"; -- 7 ena sup off+gain
constant xadc_conf1_cal2_supo: bv16 := x"0040"; -- 6 ena sup off
constant xadc_conf1_cal1_adcog: bv16 := x"0020"; -- 5 ena adc off+gain
constant xadc_conf1_cal0_adco: bv16 := x"0010"; -- 4 ena adc off
constant xadc_conf1_dis_alm2: bv16 := x"0008"; -- 3 dis alm(2)
constant xadc_conf1_dis_alm1: bv16 := x"0004"; -- 2 dis alm(1)
constant xadc_conf1_dis_alm0: bv16 := x"0002"; -- 1 dis alm(0)
constant xadc_conf1_dis_ot: bv16 := x"0001"; -- 0 dis ot
-- bit numbers for sequence registers (even word for build-in channels)
constant xadc_select_vccbram: integer := 14;
constant xadc_select_vrefn: integer := 13;
constant xadc_select_vrefp: integer := 12;
constant xadc_select_vpvn: integer := 11;
constant xadc_select_vccaux: integer := 10;
constant xadc_select_vccint: integer := 9;
constant xadc_select_temp: integer := 8;
constant xadc_select_vccoddr: integer := 7;
constant xadc_select_vccpaux: integer := 6;
constant xadc_select_vccpint: integer := 5;
constant xadc_select_calib: integer := 0;
-- defaults for plain build-in power monitoring
constant xadc_init_40_default: bv16 := xadc_conf0_cavg or
xadc_conf0_avg_16;
constant xadc_init_41_default: bv16 := xadc_conf1_seq_cont or
xadc_conf1_dis_alm6 or
xadc_conf1_dis_alm5 or
xadc_conf1_dis_alm4 or
xadc_conf1_cal3_supog or
xadc_conf1_cal2_supo or
xadc_conf1_cal1_adcog or
xadc_conf1_cal0_adco;
constant xadc_init_48_default: bv16 := (xadc_select_vccbram => '1',
xadc_select_vccaux => '1',
xadc_select_vccint => '1',
xadc_select_temp => '1',
xadc_select_calib => '1',
others => '0');
-- OT limit and reset are in general hardwired to 125 and 70 deg
-- the 4 lsbs of reg 53 contain the 'automatic shutdown enable'
-- must be set to "0011' to enable. done by default, seems prudent
constant xadc_init_53_default: bv16 := x"ca33"; -- OT LIMIT (125) + OT ENABLE
constant xadc_init_57_default: bv16 := x"ae40"; -- OT RESET (70)
constant xadc_init_4a_default: bv16 := (others => '0');
pure function xadc_temp2alim(temp : real) return bv16;
pure function xadc_svolt2alim (volt : real) return bv16;
component sysmon_rbus_core is -- SYSMON interface to rbus
generic (
DAWIDTH : positive := 7; -- drp address bus width
ALWIDTH : positive := 8; -- alm width
TEWIDTH : positive := 12; -- temp width
IBASE : slv8 := x"78"; -- base of controller register window
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SM_DEN : out slbit; -- sysmon: drp enable
SM_DWE : out slbit; -- sysmon: drp write enable
SM_DADDR : out slv(DAWIDTH-1 downto 0); -- sysmon: drp address
SM_DI : out slv16; -- sysmon: data input
SM_DO : in slv16; -- sysmon: data output
SM_DRDY : in slbit; -- sysmon: data ready
SM_EOS : in slbit; -- sysmon: end of scan
SM_RESET : out slbit; -- sysmon: reset
SM_ALM : in slv(ALWIDTH-1 downto 0);-- sysmon: alarms
SM_OT : in slbit; -- sysmon: overtemperature
SM_JTAGBUSY : in slbit; -- sysmon: JTAGBUSY
SM_JTAGLOCKED : in slbit; -- sysmon: JTAGLOCKED
SM_JTAGMODIFIED : in slbit; -- sysmon: JTAGMODIFIED
TEMP : out slv(TEWIDTH-1 downto 0) -- die temp
);
end component;
component sysmonx_rbus_base is -- XADC interface to rbus (basic monitor)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types)
INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12 -- xadc: die temp
);
end component;
component sysmonx_rbus_arty is -- XADC interface to rbus (arty pwrmon)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types)
INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12; -- xadc: die temp
VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon)
VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon)
);
end component;
end package sysmonrbuslib;
-- ----------------------------------------------------------------------------
package body sysmonrbuslib is
-- -------------------------------------
pure function xadc_temp2alim(temp : real) return bv16 is
variable ival : integer := 0;
begin
ival := integer(((temp + 273.14) * 16.0 * 4096.0) / 503.975);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_temp2alim;
-- -------------------------------------
pure function xadc_svolt2alim (volt : real) return bv16 is
variable ival : integer := 0;
begin
ival := integer((volt * 16.0 * 4096.0) / 3.0);
return to_bitvector(slv(to_unsigned(ival,16)));
end function xadc_svolt2alim;
end package body sysmonrbuslib;

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# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
sysmonrbuslib.vbom
@lib:unisim
# components
sysmon_rbus_core.vbom
# design
sysmonx_rbus_arty.vhd

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-- $Id: sysmonx_rbus_arty.vhd 742 2016-03-13 14:40:19Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sysmonx_rbus_arty - syn
-- Description: 7series XADC interface to rbus (arty pwrmon version)
--
-- Dependencies: sysmon_rbus_core
--
-- Test bench: -
--
-- Target Devices: 7series
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers: see sysmon_rbus_core and XADC user guide
--
-- XADC usage:
-- - build-in sensors: temp, Vccint, Vccaux, Vccbram
-- - arty power monitoring:
-- VAUX( 1) VPWR(0) <- 1/5.99 of JPR5V0 (main 5 V line)
-- VAUX( 2) VPWR(1) <- 1/16 of VU (external power jack)
-- VAUX( 9) VPWR(2) <- 250mV/A from shunt on JPR5V0 (main 5 V line)
-- VAUX(10) VPWR(3) <- 500mV/A from shunt on VCC0V95 (FPGA core)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmonx_rbus_arty is -- XADC interface to rbus (for arty)
generic (
INIT_OT_LIMIT : real := 125.0; -- INIT_53
INIT_OT_RESET : real := 70.0; -- INIT_57
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 0.98; -- INIT_51 (default for -1L types)
INIT_VCCINT_LOW : real := 0.92; -- INIT_55 (default for -1L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 0.98; -- INIT_58 (default for -1L types)
INIT_VCCBRAM_LOW : real := 0.92; -- INIT_5C (default for -1L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12; -- xadc: die temp
VPWRN : in slv4 := (others=>'0'); -- xadc: vpwr neg (4 chan pwrmon)
VPWRP : in slv4 := (others=>'0') -- xadc: vpwr pos (4 chan pwrmon)
);
end sysmonx_rbus_arty;
architecture syn of sysmonx_rbus_arty is
constant vpwrmap_0 : integer := 1; -- map vpwr(0) -> xadc vaux
constant vpwrmap_1 : integer := 2; -- map vpwr(1) -> xadc vaux
constant vpwrmap_2 : integer := 9; -- map vpwr(2) -> xadc vaux
constant vpwrmap_3 : integer := 10; -- map vpwr(3) -> xadc vaux
constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio
constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16)));
constant init_49 : bv16 := (vpwrmap_0 => '1', -- seq #1: (enable pwrmon)
vpwrmap_1 => '1',
vpwrmap_2 => '1',
vpwrmap_3 => '1',
others => '0');
signal VAUXN : slv16 := (others=>'0');
signal VAUXP : slv16 := (others=>'0');
signal SM_DEN : slbit := '0';
signal SM_DWE : slbit := '0';
signal SM_DADDR : slv7 := (others=>'0');
signal SM_DI : slv16 := (others=>'0');
signal SM_DO : slv16 := (others=>'0');
signal SM_DRDY : slbit := '0';
signal SM_EOS : slbit := '0';
signal SM_EOC : slbit := '0';
signal SM_RESET : slbit := '0';
signal SM_CHAN : slv5 := (others=>'0');
signal SM_ALM : slv8 := (others=>'0');
signal SM_OT : slbit := '0';
signal SM_JTAGLOCKED : slbit := '0';
signal SM_JTAGMODIFIED : slbit := '0';
signal SM_JTAGBUSY : slbit := '0';
begin
SM : XADC
generic map (
INIT_40 => xadc_init_40_default, -- conf #0
INIT_41 => xadc_init_41_default, -- conf #1
INIT_42 => init_42,
INIT_43 => x"0000", -- test #0 - don't use, stay 0
INIT_44 => x"0000", -- test #1 - "
INIT_45 => x"0000", -- test #2 - "
INIT_46 => x"0000", -- test #3 - "
INIT_47 => x"0000", -- test #4 - "
INIT_48 => xadc_init_48_default, -- seq #0: sel 0
INIT_49 => init_49, -- seq #1: sel 1 (enable pwrmon)
INIT_4A => xadc_init_4a_default, -- seq #2: avr 0
INIT_4B => x"0000", -- seq #3: avr 1: "
INIT_4C => x"0000", -- seq #4: mode 0: unipolar
INIT_4D => x"0000", -- seq #5: mode 1: "
INIT_4E => x"0000", -- seq #6: time 0: fast
INIT_4F => x"0000", -- seq #7: time 1: "
INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0)
INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1)
INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2)
INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT
INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0)
INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1)
INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2)
INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT
INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3)
INIT_59 => x"0000", -- alm #09: ccpint up (4)
INIT_5A => x"0000", -- alm #10: ccpaux up (5)
INIT_5B => x"0000", -- alm #11: ccdram up (6)
INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3)
INIT_5D => x"0000", -- alm #13: ccpint low (4)
INIT_5E => x"0000", -- alm #14: ccpaux low (5)
INIT_5F => x"0000", -- alm #15: ccdram low (6)
-- IS_CONVSTCLK_INVERTED => '0',
-- IS_DCLK_INVERTED => '0',
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "sysmon_stim")
port map (
DCLK => CLK,
DEN => SM_DEN,
DWE => SM_DWE,
DADDR => SM_DADDR,
DI => SM_DI,
DO => SM_DO,
DRDY => SM_DRDY,
EOC => SM_EOC, -- connected for tb usage
EOS => SM_EOS,
BUSY => open,
RESET => SM_RESET,
CHANNEL => SM_CHAN, -- connected for tb usage
MUXADDR => open,
ALM => SM_ALM,
OT => SM_OT,
CONVST => '0',
CONVSTCLK => '0',
JTAGBUSY => SM_JTAGBUSY,
JTAGLOCKED => SM_JTAGLOCKED,
JTAGMODIFIED => SM_JTAGMODIFIED,
VAUXN => VAUXN,
VAUXP => VAUXP,
VN => '0',
VP => '0'
);
VAUXN <= (vpwrmap_0 => VPWRN(0),
vpwrmap_1 => VPWRN(1),
vpwrmap_2 => VPWRN(2),
vpwrmap_3 => VPWRN(3),
others=>'0');
VAUXP <= (vpwrmap_0 => VPWRP(0),
vpwrmap_1 => VPWRP(1),
vpwrmap_2 => VPWRP(2),
vpwrmap_3 => VPWRP(3),
others=>'0');
SMRB : sysmon_rbus_core
generic map (
DAWIDTH => 7,
ALWIDTH => 8,
TEWIDTH => 12,
IBASE => x"78",
RB_ADDR => RB_ADDR)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
SM_DEN => SM_DEN,
SM_DWE => SM_DWE,
SM_DADDR => SM_DADDR,
SM_DI => SM_DI,
SM_DO => SM_DO,
SM_DRDY => SM_DRDY,
SM_EOS => SM_EOS,
SM_RESET => SM_RESET,
SM_ALM => SM_ALM,
SM_OT => SM_OT,
SM_JTAGBUSY => SM_JTAGBUSY,
SM_JTAGLOCKED => SM_JTAGLOCKED,
SM_JTAGMODIFIED => SM_JTAGMODIFIED,
TEMP => TEMP
);
ALM <= SM_ALM;
OT <= SM_OT;
end syn;

9
rtl/bplib/sysmon/sysmonx_rbus_base.vbom Normal file
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@@ -0,0 +1,9 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rbus/rblib.vhd
sysmonrbuslib.vbom
@lib:unisim
# components
sysmon_rbus_core.vbom
# design
sysmonx_rbus_base.vhd

192
rtl/bplib/sysmon/sysmonx_rbus_base.vhd Normal file
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@@ -0,0 +1,192 @@
-- $Id: sysmonx_rbus_base.vhd 742 2016-03-13 14:40:19Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sysmonx_rbus_base - syn
-- Description: 7series XADC interface to rbus (basic supply monitor version)
--
-- Dependencies: sysmon_rbus_core
--
-- Test bench: -
--
-- Target Devices: 7series
-- Tool versions: viv 2015.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-13 742 1.0 Initial version
-- 2016-03-06 738 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers: see sysmon_rbus_core and XADC user guide
--
-- XADC usage:
-- - only build-in sensors: temp, Vccint, Vccaux, Vccbram
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
use work.rblib.all;
use work.sysmonrbuslib.all;
-- ----------------------------------------------------------------------------
entity sysmonx_rbus_base is -- XADC interface to rbus (basic monitor)
generic (
INIT_TEMP_UP : real := 85.0; -- INIT_50 (default for C grade)
INIT_TEMP_LOW : real := 60.0; -- INIT_54
INIT_VCCINT_UP : real := 1.05; -- INIT_51 (default for non-L types)
INIT_VCCINT_LOW : real := 0.95; -- INIT_55 (default for non-L types)
INIT_VCCAUX_UP : real := 1.89; -- INIT_52
INIT_VCCAUX_LOW : real := 1.71; -- INIT_56
INIT_VCCBRAM_UP : real := 1.05; -- INIT_58 (default for non-L types)
INIT_VCCBRAM_LOW : real := 0.95; -- INIT_5C (default for non-L types)
CLK_MHZ : integer := 250; -- clock frequency in MHz
RB_ADDR : slv16 := slv(to_unsigned(16#0000#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
ALM : out slv8; -- xadc: alarms
OT : out slbit; -- xadc: over temp
TEMP : out slv12 -- xadc: die temp
);
end sysmonx_rbus_base;
architecture syn of sysmonx_rbus_base is
constant conf2_cd : integer := (CLK_MHZ+25)/26; -- clock division ratio
constant init_42 : bv16 := to_bitvector(slv(to_unsigned(256*conf2_cd,16)));
signal SM_DEN : slbit := '0';
signal SM_DWE : slbit := '0';
signal SM_DADDR : slv7 := (others=>'0');
signal SM_DI : slv16 := (others=>'0');
signal SM_DO : slv16 := (others=>'0');
signal SM_DRDY : slbit := '0';
signal SM_EOS : slbit := '0';
signal SM_EOC : slbit := '0';
signal SM_RESET : slbit := '0';
signal SM_CHAN : slv5 := (others=>'0');
signal SM_ALM : slv8 := (others=>'0');
signal SM_OT : slbit := '0';
signal SM_JTAGLOCKED : slbit := '0';
signal SM_JTAGMODIFIED : slbit := '0';
signal SM_JTAGBUSY : slbit := '0';
begin
SM : XADC
generic map (
INIT_40 => xadc_init_40_default, -- conf #0
INIT_41 => xadc_init_41_default, -- conf #1
INIT_42 => init_42,
INIT_43 => x"0000", -- test #0 - don't use, stay 0
INIT_44 => x"0000", -- test #1 - "
INIT_45 => x"0000", -- test #2 - "
INIT_46 => x"0000", -- test #3 - "
INIT_47 => x"0000", -- test #4 - "
INIT_48 => xadc_init_48_default, -- seq #0: sel 0
INIT_49 => x"0000", -- seq #1: sel 1: no aux
INIT_4A => xadc_init_4a_default, -- seq #2: avr 0
INIT_4B => x"0000", -- seq #3: avr 1: "
INIT_4C => x"0000", -- seq #4: mode 0: unipolar
INIT_4D => x"0000", -- seq #5: mode 1: "
INIT_4E => x"0000", -- seq #6: time 0: fast
INIT_4F => x"0000", -- seq #7: time 1: "
INIT_50 => xadc_temp2alim(INIT_TEMP_UP), -- alm #00: temp up (0)
INIT_51 => xadc_svolt2alim(INIT_VCCINT_UP), -- alm #01: ccint up (1)
INIT_52 => xadc_svolt2alim(INIT_VCCAUX_UP), -- alm #02: ccaux up (2)
INIT_53 => xadc_init_53_default, -- alm #03: OT limit OT
INIT_54 => xadc_temp2alim(INIT_TEMP_LOW), -- alm #04: temp low (0)
INIT_55 => xadc_svolt2alim(INIT_VCCINT_LOW), -- alm #05: ccint low (1)
INIT_56 => xadc_svolt2alim(INIT_VCCAUX_LOW), -- alm #06: ccaux low (2)
INIT_57 => xadc_init_57_default, -- alm #07: OT reset OT
INIT_58 => xadc_svolt2alim(INIT_VCCBRAM_UP), -- alm #08: ccbram up (3)
INIT_59 => x"0000", -- alm #09: ccpint up (4)
INIT_5A => x"0000", -- alm #10: ccpaux up (5)
INIT_5B => x"0000", -- alm #11: ccdram up (6)
INIT_5C => xadc_svolt2alim(INIT_VCCBRAM_LOW),-- alm #12: ccbram low (3)
INIT_5D => x"0000", -- alm #13: ccpint low (4)
INIT_5E => x"0000", -- alm #14: ccpaux low (5)
INIT_5F => x"0000", -- alm #15: ccdram low (6)
-- IS_CONVSTCLK_INVERTED => '0',
-- IS_DCLK_INVERTED => '0',
SIM_DEVICE => "7SERIES",
SIM_MONITOR_FILE => "sysmon_stim")
port map (
DCLK => CLK,
DEN => SM_DEN,
DWE => SM_DWE,
DADDR => SM_DADDR,
DI => SM_DI,
DO => SM_DO,
DRDY => SM_DRDY,
EOC => SM_EOC, -- connected for tb usage
EOS => SM_EOS,
BUSY => open,
RESET => SM_RESET,
CHANNEL => SM_CHAN, -- connected for tb usage
MUXADDR => open,
ALM => SM_ALM,
OT => SM_OT,
CONVST => '0',
CONVSTCLK => '0',
JTAGBUSY => SM_JTAGBUSY,
JTAGLOCKED => SM_JTAGLOCKED,
JTAGMODIFIED => SM_JTAGMODIFIED,
VAUXN => (others=>'0'),
VAUXP => (others=>'0'),
VN => '0',
VP => '0'
);
SMRB : sysmon_rbus_core
generic map (
DAWIDTH => 7,
ALWIDTH => 8,
TEWIDTH => 12,
IBASE => x"78",
RB_ADDR => RB_ADDR)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
SM_DEN => SM_DEN,
SM_DWE => SM_DWE,
SM_DADDR => SM_DADDR,
SM_DI => SM_DI,
SM_DO => SM_DO,
SM_DRDY => SM_DRDY,
SM_EOS => SM_EOS,
SM_RESET => SM_RESET,
SM_ALM => SM_ALM,
SM_OT => SM_OT,
SM_JTAGBUSY => SM_JTAGBUSY,
SM_JTAGLOCKED => SM_JTAGLOCKED,
SM_JTAGMODIFIED => SM_JTAGMODIFIED,
TEMP => TEMP
);
ALM <= SM_ALM;
OT <= SM_OT;
end syn;

2
rtl/bplib/sysmon/tb/sysmon_stim_arty.dat Normal file
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@@ -0,0 +1,2 @@
TIME TEMP VCCINT VCCAUX VCCBRAM VAUXP[1] VAUXN[1] VAUXP[2] VAUXN[2] VAUXP[9] VAUXN[9] VAUXP[10] VAUXN[10]
00000 25.0 0.95 1.80 0.95 0.840 0.000 0.000 0.000 0.062 0.000 0.050 0.000

2
rtl/bplib/sysmon/tb/sysmon_stim_n4.dat Normal file
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@@ -0,0 +1,2 @@
TIME TEMP VCCINT VCCAUX VCCBRAM
00000 25.0 1.00 1.80 1.00

6
rtl/ibus/Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 639 2015-01-30 18:12:19Z mueller $
# $Id: Makefile 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -13,7 +13,7 @@ NGC_all = $(VBOM_all:.vbom=.ngc)
ifndef XTW_BOARD
XTW_BOARD=nexys3
endif
include $(RETROBASE)/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all clean
#
@@ -23,7 +23,7 @@ clean : ise_clean
#
#----
#
include $(RETROBASE)/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)

6
rtl/make_ise/generic_ghdl.mk
View File

@@ -1,4 +1,4 @@
# $Id: generic_ghdl.mk 646 2015-02-15 12:04:55Z mueller $
# $Id: generic_ghdl.mk 733 2016-02-20 12:24:13Z mueller $
#
# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
@@ -16,7 +16,7 @@
# 2007-06-10 52 1.0 Initial version
#
GHDLIEEE = --ieee=synopsys
GHDLXLPATH = $(XTWI_PATH)/ISE_DS/ISE/ghdl
GHDLXLPATH = ${XTWI_PATH}/ISE_DS/ISE/ghdl
#
% : %.vbom
vbomconv --ghdl_i $<
@@ -35,7 +35,7 @@ GHDLXLPATH = $(XTWI_PATH)/ISE_DS/ISE/ghdl
%.dep_ghdl: %.vbom
vbomconv --dep_ghdl $< > $@
#
include $(RETROBASE)/rtl/make_ise/dontincdep.mk
include ${RETROBASE}/rtl/make_ise/dontincdep.mk
#
.PHONY: ghdl_clean ghdl_tmp_clean
#

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