mirror of
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- Add Arty support (BRAM only)
- Add sysmon/xadc support (for nexys4,basys3,arty designs) - Add Vivado simulator support (DPI not yet working)
This commit is contained in:
Walter F.J. Mueller
@@ -1,7 +1,7 @@
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#!/usr/bin/perl -w
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# $Id: vbomconv 672 2015-05-02 21:58:28Z mueller $
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# $Id: vbomconv 734 2016-02-20 22:43:20Z mueller $
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#
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# Copyright 2007-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# This program is free software; you may redistribute and/or modify it under
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# the terms of the GNU General Public License as published by the Free
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@@ -14,6 +14,9 @@
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#
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# Revision History:
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# Date Rev Version Comment
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# 2016-02-20 734 1.14 add [ise,viv]; add preliminary --(vsyn|vsim)_export;
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# 2016-02-14 731 1.13 add @uut tag handling;
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# 2016-02-07 728 1.12 add vivado xsim support; protect for empty xdc set
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# 2015-02-15 646 1.11 add vivado support: add -xlpath, use instead
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# of XTWI_PATH; drop --ise_path; add @lib:unimacro;
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# drop --viv_vhdl; add --vsyn_prj, --dep_vsyn;
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@@ -61,21 +64,27 @@ use Getopt::Long;
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my %opts = ();
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GetOptions(\%opts, "help", "trace", "xlpath=s",
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"dep_ghdl", "dep_xst", "dep_isim", "dep_vsyn",
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"xst_prj", "isim_prj",
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"vsyn_prj",
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"dep_ghdl",
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"dep_xst", "dep_isim",
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"dep_vsyn", "dep_vsim",
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"xst_prj", "isim_prj",
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"vsyn_prj", "vsim_prj",
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"ghdl_a", "ghdl_a_cmd",
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"ghdl_i", "ghdl_i_cmd",
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"ghdl_m", "ghdl_m_cmd",
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"ghdl_export=s",
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"xst_export=s",
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"isim_export=s",
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"vsyn_export=s",
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"vsim_export=s",
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"get_top",
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"flist") || exit 1;
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sub print_help;
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sub read_vbom;
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sub scan_vbom;
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sub do_synsim;
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sub scan_synsim;
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sub copy_edir;
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sub write_vbomdep;
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sub canon_fname;
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@@ -83,11 +92,15 @@ sub canon_fname;
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my @vbom_queue; # list of pending vbom's
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my @srcfile_list; # list of sources in compile order
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my @xdcfile_list; # list of xdc files
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my @srcfile_list_vhd; # all vhdl sources
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my @srcfile_list_v; # all (system) verilog sources
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my @srcfile_list_c; # all C sources
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my %vbom_files; # key=vbom; val=full file list
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my %vbom_xdc; # key=vbom; val=xdc spec list
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my %vbom_done; # key=vbom; val=done flags
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my %vbom_rank; # key=vbom; val=vbom ranks
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my %srcfile_rank; # key=source file; val=file rank
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my %srcfile_synsim; # key=source file; val=syn or sim
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my %para_tbl; # substitution table
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my @ucf_cpp_list;
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my $is_ghdl = 0; # ghdl simulation target
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@@ -96,17 +109,22 @@ my $is_isim = 0; # ISim simulation target
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my $is_vsyn = 0; # vivado synthesis target
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my $is_vsim = 0; # vivado simulation target
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my $is_sim = 0; # simulation target (generic)
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my $is_ise = 0; # ISE target
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my $is_viv = 0; # vivado target
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my $is_any = 0; # ignore tags (for --flist)
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my $nactions = 0; # number of action commands
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my $top_vbom; # top level vbom (from argv)
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my $eff_vbom; # effective vbom ([fot]sim->ssim map)
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my $stem; # stem of $top_vbom
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my $top; # top level entity name
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my $top_done = 0; # @top seen
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my $uut; # uut level name
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my $has_unisim; # @lib:unisim seen or implied
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my $has_unimacro; # @lib:unimacro seen
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my $has_simprim; # @lib:simprim seen or implied
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my $is_ssim;
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my $is_fsim;
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my $is_osim;
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my $is_tsim;
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my $do_trace = exists $opts{trace};
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my $level = 0; # vbom nesting level
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@@ -133,22 +151,27 @@ if (scalar(@ARGV) != 1) {
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foreach (keys %opts) {
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$nactions += 1 unless ($_ eq "trace" || $_ eq "xlpath");
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$is_ghdl = 1 if ($_ eq "dep_ghdl");
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$is_ghdl = 1 if ($_ =~ /^ghdl_/);
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$is_ghdl = 1 if $_ eq "dep_ghdl";
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$is_ghdl = 1 if $_ =~ /^ghdl_/;
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$is_xst = 1 if ($_ eq "dep_xst");
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$is_xst = 1 if ($_ =~ /^xst_/);
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$is_xst = 1 if $_ eq "dep_xst";
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$is_xst = 1 if $_ =~ /^xst_/;
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$is_isim = 1 if ($_ eq "dep_isim");
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$is_isim = 1 if ($_ =~ /^isim_/);
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$is_isim = 1 if $_ eq "dep_isim";
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$is_isim = 1 if $_ =~ /^isim_/;
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$is_vsyn = 1 if ($_ eq "dep_vsyn");
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$is_vsyn = 1 if ($_ =~ /^vsyn_/);
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$is_vsyn = 1 if $_ eq "dep_vsyn";
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$is_vsyn = 1 if $_ =~ /^vsyn_/;
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$is_any = 1 if ($_ eq "flist");
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$is_vsim = 1 if $_ eq "dep_vsim";
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$is_vsim = 1 if $_ =~ /^vsim_/;
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$is_any = 1 if $_ eq "flist";
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}
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$is_sim = $is_ghdl | $is_isim | $is_vsim;
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$is_ise = $is_xst | $is_isim;
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$is_viv = $is_vsyn | $is_vsim;
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print STDERR "-- [ghdl] active\n" if $do_trace && $is_ghdl;
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print STDERR "-- [xst] active\n" if $do_trace && $is_xst;
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@@ -156,6 +179,8 @@ print STDERR "-- [isim] active\n" if $do_trace && $is_isim;
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print STDERR "-- [vsyn] active\n" if $do_trace && $is_vsyn;
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print STDERR "-- [vsim] active\n" if $do_trace && $is_vsim;
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print STDERR "-- [sim] active\n" if $do_trace && $is_sim;
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print STDERR "-- [ise] active\n" if $do_trace && $is_ise;
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print STDERR "-- [viv] active\n" if $do_trace && $is_viv;
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if ($nactions > 1) {
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print STDERR "vbomconv-E: only one action qualifier allowed\n\n";
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@@ -173,24 +198,20 @@ $stem =~ s{\..*$}{};
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$top = $stem;
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$top =~ s{^.*/}{};
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# now prepare virtual _fsim and _tsim vbom's
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# now prepare virtual _fsim, _osim, and _tsim vbom's
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# they are inferred from the _ssim vbom's
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if ($top_vbom =~ m{_ssim\.vbom$}) { # detect _ssim
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$is_ssim = 1;
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}
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if ($top_vbom =~ m{_fsim\.vbom$}) { # map _fsim -> _ssim
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$is_fsim = 1;
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$top_vbom =~ s{_fsim\.vbom$}{_ssim.vbom};
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}
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if ($top_vbom =~ m{_tsim\.vbom$}) { # map _tsim -> _ssim
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$is_tsim = 1;
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$top_vbom =~ s{_tsim\.vbom$}{_ssim.vbom};
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}
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$is_ssim = 1 if $top_vbom =~ m{_ssim\.vbom$}; # detect _ssim
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$is_fsim = 1 if $top_vbom =~ m{_fsim\.vbom$}; # detect _fsim
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$is_osim = 1 if $top_vbom =~ m{_osim\.vbom$}; # detect _osim
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$is_tsim = 1 if $top_vbom =~ m{_tsim\.vbom$}; # detect _tsim
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$eff_vbom = $top_vbom;
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$eff_vbom =~ s{_[fot]sim\.vbom$}{_ssim.vbom}; # map [fot]sim -> ssim
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# traverse all vbom's start with command line argument
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push @vbom_queue, $top_vbom;
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push @vbom_queue, $eff_vbom;
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while (@vbom_queue) {
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my $cur_vbom = shift @vbom_queue;
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@@ -199,8 +220,11 @@ while (@vbom_queue) {
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# traverse internal vbom representation to build file table
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$vbom_rank{$top_vbom} = {min=>1, max=>1};
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scan_vbom($top_vbom);
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$vbom_rank{$eff_vbom} = {min=>1, max=>1};
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scan_vbom($eff_vbom);
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# separate sym (uut) and sim (tb) parts
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do_synsim($uut);
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# sort file table, build file list (decreasing rank)
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# sort first by decreasing rank and second by filename
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@@ -229,6 +253,19 @@ foreach (@vbomfile_list_min) {
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push @xdcfile_list, @{$vbom_xdc{$_}} if exists $vbom_xdc{$_};
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}
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# now split source list according to languages
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foreach (@srcfile_list) {
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if (m/\.vhd$/) {
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push @srcfile_list_vhd, $_;
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} elsif (m/\.(v|sv)$/) {
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push @srcfile_list_v, $_;
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} elsif (m/\.c$/) {
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push @srcfile_list_c, $_;
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# } else {
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# print STDERR "unknown file type $_\n";
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}
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}
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# now generate output and actions, depending on options given
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# --trace ------------------------------------------------------------
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@@ -251,12 +288,13 @@ if ($do_trace) {
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print STDERR "\n";
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print STDERR "final srcfile_rank table (sort by rank):\n";
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foreach (sort {$b->[0] <=> $a->[0] || $a->[1] cmp $b->[1]} @srcpair_list) {
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printf STDERR " %5d %s\n", $_->[0], $_->[1];
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printf STDERR " %5d %s %s\n", $_->[0], $srcfile_synsim{$_->[1]}, $_->[1];
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}
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print STDERR "\n";
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print STDERR "properties:\n";
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print STDERR " \@top: $top\n";
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print STDERR " \@uut: $uut\n" if defined $uut;
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}
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# --ghdh_a -- ghdl analysis command ----------------------------------
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@@ -363,7 +401,7 @@ if (exists $opts{ghdl_m} || exists $opts{ghdl_m_cmd} ) {
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$cmd .= " -P$xlpath/unimacro" if $has_unimacro;
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$cmd .= " -P$xlpath/simprim" if $has_simprim;
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$cmd .= " --ieee=synopsys";
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$cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_tsim;
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$cmd .= " --no-vital-checks" if $is_ssim or $is_fsim or $is_osim or $is_tsim;
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foreach (@srcfile_list) {
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next unless /\.c$/; # C source ?
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@@ -431,25 +469,115 @@ if (exists $opts{vsyn_prj}) {
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print "}\n";
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print "\n";
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print "set obj [get_filesets constrs_1]\n";
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print "add_files -norecurse -fileset \$obj \$xdc_files\n";
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# add_files does not allow adding an empty set, so protect
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if (scalar @xdcfile_list) {
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print "set obj [get_filesets constrs_1]\n";
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print "add_files -norecurse -fileset \$obj \$xdc_files\n";
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}
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print "\n";
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}
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# --vsim_prj ---------------------------------------------------------
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if (exists $opts{vsim_prj}) {
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print "#!/bin/sh\n";
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print "#\n";
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print "# generated by vbomconv -vsim_prj $top_vbom\n";
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print "#\n";
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# compile verilog before vhdl !
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# currently verilog only used for DPI interface code
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# xvhdl relies in strict compilation order, also across languages, and fails
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# when a not yet compiles module is instantiated via entiry work....
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if (scalar @srcfile_list_v) {
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print "# ---------- xvlog step\n";
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my $tfile_xvlog_prj = "tmp_${stem}_xvlog.prj";
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print "cat > $tfile_xvlog_prj <<tmp_xvlog_end_token\n";
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foreach (@srcfile_list_v) {
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my $type = (m/\.v$/) ? "verilog" : "sv ";
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print "$type work $_\n";
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}
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print "tmp_xvlog_end_token\n";
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print "#\n";
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my $opts_xvlog = "-m64 --relax";
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print "xtwv xvlog $opts_xvlog -prj $tfile_xvlog_prj 2>&1 |\\\n";
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print " tee xvlog_${stem}.log\n";
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print "rm -f $tfile_xvlog_prj\n";
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print "#\n";
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}
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if (scalar @srcfile_list_vhd) {
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print "# ---------- xvhdl step\n";
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my $tfile_xvhdl_prj = "tmp_${stem}_xvhdl.prj";
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print "cat > $tfile_xvhdl_prj <<tmp_xvhdl_end_token\n";
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foreach (@srcfile_list_vhd) {
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print "vhdl work $_\n";
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}
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print "tmp_xvhdl_end_token\n";
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print "#\n";
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my $opts_xvhdl = "-m64 --relax";
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print "xtwv xvhdl $opts_xvhdl -prj $tfile_xvhdl_prj 2>&1 |\\\n";
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print " tee xvhdl_${stem}.log\n";
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print "rm -f $tfile_xvhdl_prj\n";
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print "#\n";
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}
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if (scalar @srcfile_list_c) {
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print "# ---------- xsc step\n";
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print "xtwv xsc";
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foreach (@srcfile_list_c) {
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print " \\\n $_";
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}
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print "\n";
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print "#\n";
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}
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print "# ---------- xelab step\n";
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print "xtwv xelab --relax --debug typical --mt auto -m64 \\\n";
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print " -L work \\\n";
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if (scalar @srcfile_list_c) {
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print " --sv_lib dpi \\\n";
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}
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print " --snapshot $stem work.$top \\\n";
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print " -log xelab_${stem}.log\n";
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print "\n";
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print "# ---------- create forwarder\n";
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my $fname_forwarder = "${stem}_XSim";
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$fname_forwarder =~ s/_([sot]sim)_XSim/_XSim_$1/;
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print "if [ -x \"xsim.dir/${stem}/xsimk\" ]\n";
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print "then\n";
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print "#\n";
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print "cat > $fname_forwarder <<forwarder_end_token\n";
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print "#!/bin/sh\n";
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# Note: double escape \"\\\$\@\" needed to ensure file contains "$@"
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print "exec xtwv xsim ${stem} \"\\\$\@\"\n";
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print "forwarder_end_token\n";
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print "#\n";
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print "chmod +x $fname_forwarder\n";
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print "fi\n";
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}
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# --dep_ghdl ---------------------------------------------------------
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if (exists $opts{dep_ghdl}) {
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my $stem_fsim = $stem;
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my $stem_osim = $stem;
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my $stem_tsim = $stem;
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$stem_fsim =~ s/_ssim$/_fsim/;
|
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$stem_osim =~ s/_ssim$/_osim/;
|
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$stem_tsim =~ s/_ssim$/_tsim/;
|
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|
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print "#\n";
|
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print "$stem : $stem.dep_ghdl\n";
|
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if ($is_ssim) {
|
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print "$stem_fsim : $stem.dep_ghdl\n";
|
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print "$stem_osim : $stem.dep_ghdl\n";
|
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print "$stem_tsim : $stem.dep_ghdl\n";
|
||||
}
|
||||
print "#\n";
|
||||
@@ -473,6 +601,7 @@ if (exists $opts{dep_ghdl}) {
|
||||
|
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if ($is_ssim) {
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|
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print "#\n";
|
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foreach (@srcfile_list) {
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my $file = $_; # copy to break alias for following s///
|
||||
if (/\.c$/) {
|
||||
@@ -484,6 +613,19 @@ if (exists $opts{dep_ghdl}) {
|
||||
print "$stem_fsim : $file\n";
|
||||
}
|
||||
|
||||
print "#\n";
|
||||
foreach (@srcfile_list) {
|
||||
my $file = $_; # copy to break alias for following s///
|
||||
if (/\.c$/) {
|
||||
$file =~ s{^.*/}{}; # remove directory path
|
||||
$file =~ s/\.c$/.o/; # depend on object file for C sources
|
||||
} else {
|
||||
$file =~ s/_ssim\.vhd$/_osim.vhd/;
|
||||
}
|
||||
print "$stem_osim : $file\n";
|
||||
}
|
||||
|
||||
print "#\n";
|
||||
foreach (@srcfile_list) {
|
||||
my $file = $_; # copy to break alias for following s///
|
||||
if (/\.c$/) {
|
||||
@@ -552,12 +694,14 @@ if (exists $opts{dep_isim}) {
|
||||
|
||||
if ($is_ssim) {
|
||||
|
||||
print "#\n";
|
||||
foreach (@srcfile_list) {
|
||||
my $file = $_; # copy to break alias for following s///
|
||||
$file =~ s/_ssim\.vhd$/_fsim.vhd/;
|
||||
print "$stem_fsim_isim : $file\n";
|
||||
}
|
||||
|
||||
print "#\n";
|
||||
foreach (@srcfile_list) {
|
||||
my $file = $_; # copy to break alias for following s///
|
||||
$file =~ s/_ssim\.vhd$/_tsim.vhd/;
|
||||
@@ -592,6 +736,51 @@ if (exists $opts{dep_vsyn}) {
|
||||
write_vbomdep("$stem.dep_vsyn");
|
||||
}
|
||||
|
||||
# --dep_vsim ---------------------------------------------------------
|
||||
|
||||
if (exists $opts{dep_vsim}) {
|
||||
my $stem_vsim = $stem . "_XSim";
|
||||
|
||||
$stem_vsim =~ s/_ssim_XSim$/_XSim_ssim/ if ($is_ssim);
|
||||
|
||||
my $stem_osim_vsim = $stem_vsim;
|
||||
my $stem_tsim_vsim = $stem_vsim;
|
||||
$stem_osim_vsim =~ s/_ssim$/_osim/;
|
||||
$stem_tsim_vsim =~ s/_ssim$/_tsim/;
|
||||
|
||||
print "#\n";
|
||||
print "$stem_vsim : $stem.dep_vsim\n";
|
||||
if ($is_ssim) {
|
||||
print "$stem_osim_vsim : $stem.dep_vsim\n";
|
||||
print "$stem_tsim_vsim : $stem.dep_vsim\n";
|
||||
}
|
||||
print "#\n";
|
||||
|
||||
foreach (@srcfile_list) {
|
||||
print "$stem_vsim : $_\n";
|
||||
}
|
||||
|
||||
if ($is_ssim) {
|
||||
|
||||
print "#\n";
|
||||
foreach (@srcfile_list) {
|
||||
my $file = $_; # copy to break alias for following s///
|
||||
$file =~ s/_ssim\.vhd$/_osim.vhd/;
|
||||
print "$stem_osim_vsim : $file\n";
|
||||
}
|
||||
|
||||
print "#\n";
|
||||
foreach (@srcfile_list) {
|
||||
my $file = $_; # copy to break alias for following s///
|
||||
$file =~ s/_ssim\.vhd$/_tsim.v/;
|
||||
print "$stem_tsim_vsim : $file\n";
|
||||
}
|
||||
#
|
||||
}
|
||||
|
||||
write_vbomdep("$stem.dep_vsim");
|
||||
}
|
||||
|
||||
# --ghdl_export or xst_export or isim_export -------------------------
|
||||
|
||||
if (exists $opts{ghdl_export} or
|
||||
@@ -630,17 +819,114 @@ if (exists $opts{ghdl_export} or
|
||||
die "can't write open $edir/$stem.xcf: $!";
|
||||
close(XFILE);
|
||||
|
||||
foreach(glob("*.xcf")) { copy_edir($_, $edir); }
|
||||
foreach (glob("*.xcf")) { copy_edir($_, $edir); }
|
||||
|
||||
if (-r "$stem.ucf_cpp") {
|
||||
system "/bin/sh", "-c", "make $stem.ucf";
|
||||
}
|
||||
|
||||
foreach(glob("*.ucf")) { copy_edir($_, $edir); }
|
||||
foreach (glob("*.ucf")) { copy_edir($_, $edir); }
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
# --vsyn_export or vsim_export ---------------------------------------
|
||||
|
||||
if (exists $opts{vsyn_export} or
|
||||
exists $opts{vsim_export}) {
|
||||
my $edir;
|
||||
$edir = $opts{vsyn_export} if exists $opts{vsyn_export};
|
||||
$edir = $opts{vsim_export} if exists $opts{vsim_export};
|
||||
|
||||
if (not -d $edir) {
|
||||
print STDERR "vbomconv-I: create target directory $edir\n";
|
||||
system("mkdir -p $edir") == 0 or die "mkdir failed: $?";
|
||||
} else {
|
||||
print STDERR "vbomconv-I: target directory $edir already exists\n";
|
||||
}
|
||||
|
||||
my @filist;
|
||||
push @filist, @srcfile_list;
|
||||
push @filist, @xdcfile_list;
|
||||
my @fl_syn;
|
||||
my @fl_sim;
|
||||
my @fl_xdc;
|
||||
|
||||
foreach my $fi (@filist) {
|
||||
my $fname = $fi;
|
||||
my $fdpath = ".";
|
||||
if ($fi =~ m{(.*)/(.*)}) {
|
||||
$fname = $2;
|
||||
$fdpath = $1;
|
||||
}
|
||||
|
||||
copy_edir($fi, $edir);
|
||||
|
||||
if ($fname =~ m{\.(vhd|sv)$}) { # .vhd or .sv
|
||||
if ($srcfile_synsim{$fi} eq 'syn') {
|
||||
push @fl_syn, $fname;
|
||||
} else {
|
||||
push @fl_sim, $fname;
|
||||
}
|
||||
} elsif ($fname =~ m{\.c}) { # .c
|
||||
printf "+++2 $fi\n";
|
||||
push @fl_sim, $fname;
|
||||
} elsif ($fname =~ m{\.xdc}) { # .xdc
|
||||
push @fl_xdc, $fname;
|
||||
} else {
|
||||
print STDERR "vbomconv-W: file $fname not procesed (unknown type)\n";
|
||||
}
|
||||
}
|
||||
|
||||
open(TFILE, ">$edir/$stem.tcl") or die "can't write open $edir/$stem.tcl: $!";
|
||||
|
||||
print TFILE "#\n";
|
||||
print TFILE "# setup file lists\n";
|
||||
print TFILE "#\n";
|
||||
|
||||
print TFILE "set syn_files {\n";
|
||||
foreach (@fl_syn) {
|
||||
print TFILE " $_\n";
|
||||
}
|
||||
print TFILE "}\n";
|
||||
print TFILE "\n";
|
||||
|
||||
print TFILE "set sim_files {\n";
|
||||
foreach (@fl_sim) {
|
||||
print TFILE " $_\n";
|
||||
}
|
||||
print TFILE "}\n";
|
||||
print TFILE "\n";
|
||||
|
||||
print TFILE "set xdc_files {\n";
|
||||
foreach (@fl_xdc) {
|
||||
print TFILE " $_\n";
|
||||
}
|
||||
print TFILE "}\n";
|
||||
print TFILE "\n";
|
||||
|
||||
print TFILE 'set obj [get_filesets sources_1]' . "\n";
|
||||
print TFILE 'add_files -norecurse -fileset $obj $syn_files' . "\n";
|
||||
printf TFILE 'set_property "top" "%s" $obj' . "\n", $top;
|
||||
print TFILE "\n";
|
||||
|
||||
if (scalar @fl_sim) {
|
||||
print TFILE 'set obj [get_filesets sim_1]' . "\n";
|
||||
print TFILE 'add_files -norecurse -fileset $obj $sim_files' . "\n";
|
||||
print TFILE "\n";
|
||||
}
|
||||
|
||||
if (scalar @fl_xdc) {
|
||||
print TFILE 'set obj [get_filesets constrs_1]' . "\n";
|
||||
print TFILE 'add_files -norecurse -fileset $obj $xdc_files' . "\n";
|
||||
print TFILE "\n";
|
||||
}
|
||||
|
||||
close(TFILE);
|
||||
|
||||
|
||||
}
|
||||
|
||||
# --get_top ----------------------------------------------------------
|
||||
|
||||
if (exists $opts{get_top}) {
|
||||
@@ -756,13 +1042,15 @@ sub read_vbom {
|
||||
my $keep = $is_any;
|
||||
## print STDERR "+++1 |$qual|$name|$vbom|\n";
|
||||
foreach my $pref (split /,/,$qual) {
|
||||
if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim)$/) {
|
||||
if ($pref =~ /^(ghdl|xst|isim|vsyn|vsim|sim|ise|viv)$/) {
|
||||
$keep = 1 if ($pref eq "ghdl" && $is_ghdl);
|
||||
$keep = 1 if ($pref eq "xst" && $is_xst);
|
||||
$keep = 1 if ($pref eq "isim" && $is_isim);
|
||||
$keep = 1 if ($pref eq "vsyn" && $is_vsyn);
|
||||
$keep = 1 if ($pref eq "vsim" && $is_vsim);
|
||||
$keep = 1 if ($pref eq "sim" && $is_sim);
|
||||
$keep = 1 if ($pref eq "ise" && $is_ise);
|
||||
$keep = 1 if ($pref eq "viv" && $is_viv);
|
||||
} else {
|
||||
print STDERR "vbomconv-W: unknown tag [$pref] in $vbom_file\n";
|
||||
}
|
||||
@@ -776,6 +1064,7 @@ sub read_vbom {
|
||||
|
||||
my $tag;
|
||||
my $val = $_;
|
||||
my $uut_seen;
|
||||
|
||||
# detect tag:val lines
|
||||
if (m{^\s*(.*?)\s*:\s*(.*?)\s*$}) {
|
||||
@@ -785,14 +1074,17 @@ sub read_vbom {
|
||||
# process @top:<entity> lines
|
||||
if ($tag eq '@top') {
|
||||
$top = $val unless $top_done;
|
||||
next;
|
||||
|
||||
# process @ucf_cpp:<file> lines
|
||||
} elsif ($tag eq '@ucf_cpp') {
|
||||
push @ucf_cpp_list, $val;
|
||||
next;
|
||||
|
||||
# process @xdc:<file> lines
|
||||
} elsif ($tag eq '@xdc') {
|
||||
push @{$vbom_xdc{$vbom}}, canon_fname($vbom_path, $val);
|
||||
next;
|
||||
|
||||
# process @lib:<name> lines
|
||||
} elsif ($tag eq '@lib') {
|
||||
@@ -806,18 +1098,27 @@ sub read_vbom {
|
||||
print STDERR "vbomconv-E: invalid lib type \'$tag\' in $vbom_file\n";
|
||||
exit 1;
|
||||
}
|
||||
next;
|
||||
|
||||
# process @uut:<file> lines
|
||||
} elsif ($tag eq '@uut') {
|
||||
$uut_seen = 1;
|
||||
# Note: fall through in this case, process as normal file name
|
||||
# actual @uut tag handling later with canonized file names.
|
||||
|
||||
# catch invalid @ tags
|
||||
} else {
|
||||
print STDERR "vbomconv-E: invalid \'$tag:\' line in $vbom_file\n";
|
||||
exit 1;
|
||||
}
|
||||
next;
|
||||
|
||||
}
|
||||
|
||||
# now do _fsim, _tsim mapping
|
||||
# now do _fsim, _osim, _tsim mapping
|
||||
$val =~ s{_ssim\.vhd$}{_fsim.vhd} if $is_fsim;
|
||||
$val =~ s{_ssim\.vhd$}{_tsim.vhd} if $is_tsim;
|
||||
$val =~ s{_ssim\.vhd$}{_osim.vhd} if $is_osim;
|
||||
$val =~ s{_ssim\.vhd$}{_tsim.vhd} if $is_tsim && $is_ise; # ISE
|
||||
$val =~ s{_ssim\.vhd$}{_tsim.v} if $is_tsim && $is_viv; # Vivado
|
||||
|
||||
# process normal .vhd or .vbom file lines
|
||||
# canonize file name unless not already done by filename substitution
|
||||
@@ -828,8 +1129,17 @@ sub read_vbom {
|
||||
$fullname = canon_fname($vbom_path, $val);
|
||||
}
|
||||
|
||||
# process @uut tag here, with canonized file names
|
||||
if ($uut_seen) {
|
||||
if (defined $uut) {
|
||||
print STDERR "vbomconv-E: duplicate \@uut:, 1st '$uut' 2nd '$val'\n";
|
||||
exit 1;
|
||||
}
|
||||
$uut = $fullname;
|
||||
}
|
||||
|
||||
# determine whether additional libs needed
|
||||
if ($fullname =~ m{_ssim\.vhd$}) { # ends in _ssim.vhd
|
||||
if ($fullname =~ m{_[so]sim\.vhd$}) { # ends in _ssim.vhd or _osim.vhd
|
||||
$has_unisim = 1;
|
||||
}
|
||||
if ($fullname =~ m{_[ft]sim\.vhd$}) { # ends in _fsim.vhd or _tsim.vhd
|
||||
@@ -871,10 +1181,9 @@ sub scan_vbom {
|
||||
$vbom_rank{$vbom} = {min=>$level, max=>$level};
|
||||
}
|
||||
|
||||
foreach (@{$vbom_files{$vbom}}) {
|
||||
my $file = $_;
|
||||
foreach my $file (@{$vbom_files{$vbom}}) {
|
||||
$rank -= 1;
|
||||
if (m{\.vbom$}) {
|
||||
if ($file =~ m{\.vbom$}) {
|
||||
scan_vbom($file);
|
||||
} else {
|
||||
if (exists $srcfile_rank{$file}) {
|
||||
@@ -898,6 +1207,42 @@ sub scan_vbom {
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
|
||||
sub do_synsim {
|
||||
my ($uut) = @_;
|
||||
|
||||
# all is syn if no @uut defined; preset with sim when @uut defined
|
||||
my $def = (defined $uut) ? 'sim' : 'syn';
|
||||
foreach my $file (keys %srcfile_rank) {
|
||||
$srcfile_synsim{$file} = $def;
|
||||
}
|
||||
return unless defined $uut;
|
||||
|
||||
# if @uut seen separate them
|
||||
if (defined $uut) {
|
||||
if ($uut =~ m{\.vbom}) { # uut is vbom (functional sim)
|
||||
scan_synsim($uut);
|
||||
} else { # uut is file (post syn sim)
|
||||
$srcfile_synsim{$uut} = 'syn';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
|
||||
sub scan_synsim {
|
||||
my ($vbom) = @_;
|
||||
|
||||
foreach my $file (@{$vbom_files{$vbom}}) {
|
||||
if ($file =~ m{\.vbom$}) {
|
||||
scan_synsim($file);
|
||||
} else {
|
||||
$srcfile_synsim{$file} = 'syn';
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#-------------------------------------------------------------------------------
|
||||
|
||||
sub copy_edir {
|
||||
my ($file, $edir) = @_;
|
||||
print "cp -p $file $edir\n";
|
||||
@@ -959,6 +1304,8 @@ sub print_help {
|
||||
print " --ghdl_export=s export all ghdl source files into directory s\n";
|
||||
print " --xst_export=s export all xst source files into directory s\n";
|
||||
print " --isim_export=s export all isim source files into directory s\n";
|
||||
print " --vsyn_export=s export all vsyn source files into directory s\n";
|
||||
print " --vsim_export=s export all vsim source files into directory s\n";
|
||||
print " --get_top return top level entity name\n";
|
||||
print " --flist list all files touched by vbom for all tags\n";
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user