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cpu_eis.mac: add MUL,DIV odd, XOR
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wfjm
@@ -1,4 +1,4 @@
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; $Id: cpu_badinst_nofpp.mac 1257 2022-07-16 21:49:08Z mueller $
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; $Id: cpu_badinst_nofpp.mac 1258 2022-07-18 10:07:22Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -101,7 +101,11 @@ ta0103: mov #vh.exp,v..rit ; setup iit handler
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halt
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.word 007777
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halt
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.word 075000 ; 075000-075777
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.word 075000 ; 075000-075037 {FIS in 11/40}
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halt
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.word 075037
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halt
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.word 075040 ; 075040-075777
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halt
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.word 075777
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halt
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@@ -127,7 +131,7 @@ ta0103: mov #vh.exp,v..rit ; setup iit handler
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halt
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;
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mov #v..rit+2,v..rit ; restore iit catcher
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cmp trpcnt,#27.
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cmp trpcnt,#29.
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beq .+4
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halt
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;
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@@ -154,3 +158,5 @@ ta0104: mov #vh.exp,v..rit ; setup iit handler
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; END OF ALL TESTS - loop closure --------------------------------------------
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;
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jmp loop
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;
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.end start
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@@ -1,4 +1,4 @@
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; $Id: cpu_eis.mac 1257 2022-07-16 21:49:08Z mueller $
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; $Id: cpu_eis.mac 1259 2022-07-18 17:39:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -282,9 +282,180 @@ ta0102: mov #1000$,r5
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.word 0137777,0177777, -32768., cp00v0, -16385., -1.;dd=-1073741825
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;
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1011$:
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;
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9999$: iot ; end of test A1.2
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;
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;
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; Test A1.3 -- div odd register +++++++++++++++++++++++++++++++++++++++
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; check div odd register behavior
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; Note: The div instruction has, in contrast to ashc, no useful semantics when
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; called with an odd register. DEC documentation doesn't specify the
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; behavior. SimH assumes, that register handling is done like for ashc,
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; so effective dd is 'R<<16 | R' and reminder is stored. w11 implements
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; div like this. This test briefly verifies this behavior.
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ta0103: mov #1000$,r4 ; setup data pointer
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mov #1010$,r5 ; setup end pointer
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mov #cp.psw,r3 ; setup psw pointer
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clr r0 ; for tmu optics
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100$: mov (r4)+,r1 ; load dd
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div (r4)+,r1 ; div
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cmp (r4)+,(r3) ; check psw
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beq .+4
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halt
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cmp (r4)+,r1 ; check res (reminder)
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beq .+4
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halt
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cmp r4,r5
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blo 100$
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jmp 9999$
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;
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; dd, dr, psw, res ;
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1000$: .word 000000, 1., cp0z00, 000000 ; h: 000000
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.word 000007, 16., cp0000, 000007 ; 458759/16: 28672, 7 h: 070000
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.word 000007, 17., cp0000, 000016 ; 458759/17: 26985,14 h: 064551
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.word 000007, 19., cp0000, 000004 ; 458759/19: 24145, 4 h: 057121
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.word 000007, 15., cp0000, 000016 ; 458759/15: 30583,14 h: 073567
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1010$:
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;
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9999$: iot ; end of test A1.3
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;
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; Section B: mul =============================================================
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; This section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 111 000 rrr sss sss NZ0C MUL
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;
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; Test B1.1 -- mul even and odd ++++++++++++++++++++++++++++++++++++++
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; check that mul works with even and odd destination register
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;
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jmp tb0101
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;
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; driver for mul even tests
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;
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tbmule: mov #cp.psw,r3 ; setup psw pointer
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100$: mov (r4)+,r0 ; load f1
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mul (r4)+,r0 ; mul
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cmp (r4)+,(r3) ; check psw
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beq .+4
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halt
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cmp (r4)+,r0 ; check p_high
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beq .+4
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halt
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cmp (r4)+,r1 ; check p_low
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beq .+4
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halt
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cmp r4,r5
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blo 100$
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rts pc
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;
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; driver for mul odd tests
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;
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tbmulo: mov #cp.psw,r3 ; setup psw pointer
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100$: mov (r4)+,r1 ; load f1
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mul (r4)+,r1 ; mul
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cmp (r4)+,(r3) ; check psw
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beq .+4
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halt
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tst (r4)+ ; skip p_high
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cmp (r4)+,r1 ; check p_low
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beq .+4
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halt
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cmp r4,r5
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blo 100$
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rts pc
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;
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tb0101: mov #1000$,r4 ; setup data pointer
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mov #1010$,r5 ; setup end pointer
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jsr pc,tbmule ; test even
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;
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mov #1000$,r4 ; setup data pointer
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mov #1010$,r5 ; setup end pointer
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jsr pc,tbmulo ; test odd
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;
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jmp 9999$
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;
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; fx, f2, psw, ph, pl ;
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1000$: .word 0., 0., cp0z00, 0, 0 ; p = 0.
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.word 0., 1., cp0z00, 0, 0 ; p = 0.
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.word 0., -1., cp0z00, 0, 0 ; p = 0.
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.word 1., 0., cp0z00, 0, 0 ; p = 0.
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.word 1., 1., cp0000, 0, 1 ; p = 1.
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.word 1., -1., cpn000, 177777, 177777 ; p = -1.
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.word -1., 0., cp0z00, 0, 0 ; p = 0.
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.word -1., 1., cpn000, 177777, 177777 ; p = -1.
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.word -1., -1., cp0000, 0, 1 ; p = 1.
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.word 181., 181., cp0000, 0, 077771 ; p = 32761.
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.word 181., 182., cp000c, 0, 100256 ; p = 32942.
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.word 181., -182., cpn00c, 177777, 077522 ; p = -32942.
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.word 31022., 9562., cp000c, 010656, 040054 ; p = 296632364.
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.word 18494.,-24041., cpn00c, 162577, 134622 ; p =-444614254.
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.word -12549., 2397., cpn00c, 177065, 002057 ; p = -30079953.
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.word -20493.,-23858., cp000c, 016444, 055612 ; p = 488921994.
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1010$:
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;
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9999$: iot ; end of test B1.1
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;
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; Test B1.2 -- mul+div (and adc,adc,sxt) +++++++++++++++++++++++++++++
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; combined div and mul test
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;
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tb0102: mov #1000$,r4 ; setup data pointer
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mov #1010$,r5 ; setup end pointer
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;
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100$: mov (r4)+,r0 ; load divident high
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mov (r4)+,r1 ; load divident low
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div (r4)+,r0 ; divide by divisor
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mov r0,r2 ; get quotient
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mul -2(r4),r2 ; multiply with divisor
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add r1,r3 ; add reminder on p_low
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adc r2 ; propagate carry to p_high
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tst r1 ; sign extend reminder
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sxt r1
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add r1,r2 ; and add to p_high
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cmp -4(r4),r3 ; check p_low against divident low
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beq .+4
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halt
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cmp -6(r4),r2 ; check p_high against divident high
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beq .+4
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halt
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cmp r4,r5
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blo 100$
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jmp 9999$
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;
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; ddh ddl dr
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1000$: .word 0, 0, 0
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.word 0, 1, 3
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.word 0, 2, 3
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.word 0, 3, 3
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.word 0, 4, 3
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.word -1, -1, 3
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.word -1, -2, 3
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.word -1, -3, 3
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.word -1, -4, 3
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.word 0, 0, -3
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.word 0, 1, -3
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.word 0, 2, -3
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.word 0, 3, -3
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.word 0, 4, -3
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.word -1, -1, -3
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.word -1, -2, -3
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.word -1, -3, -3
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.word -1, -4, -3
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.word 010656, 040054, 9562. ; dd = 296632364.
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.word 010656, 040053, 9562. ; dd = 296632363.
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.word 010656, 040055, 9562. ; dd = 296632365.
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.word 010656, 040054, -9562. ; dd = 296632364.
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.word 010656, 040053, -9562. ; dd = 296632363.
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.word 010656, 040055, -9562. ; dd = 296632365.
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.word 162577, 134622, 24041. ; dd = -444614254.
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.word 162577, 134621, 24041. ; dd = -444614255.
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.word 162577, 134623, 24041. ; dd = -444614253.
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.word 162577, 134622,-24041. ; dd = -444614254.
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.word 162577, 134621,-24041. ; dd = -444614255.
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.word 162577, 134623,-24041. ; dd = -444614253.
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1010$:
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;
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9999$: iot ; end of test B1.2
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;
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; Section C: ash =============================================================
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; This section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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@@ -507,11 +678,83 @@ td0102: mov #1000$,r4 ; setup data pointer
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;
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9999$: iot ; end of test D1.2
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;
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; Section E: xor =============================================================
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; This section verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 111 100 rrr ddd ddd NZ0- XOR
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;
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; Test E1.1 -- xor znvc=0 ++++++++++++++++++++++++++++++++++++++++++++
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; check xor with all cc's cleared; memory destination
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;
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te0101: mov #1000$,r4 ; setup data pointer
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mov #1010$,r5 ; setup end pointer
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mov #cp.psw,r3 ; setup psw pointer
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mov #200$,r1 ; setup dst pointer
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100$: mov (r4)+,r0 ; load src
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mov (r4)+,(r1) ; load dst
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ccc ; nzvc=0
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xor r0,(r1) ; xor
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cmp (r4)+,(r3) ; check psw
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beq .+4
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halt
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cmp (r4)+,(r1) ; check
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beq .+4
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halt
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cmp r4,r5
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blo 100$
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jmp 9999$
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;
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200$: .word 0
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;
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; dst, src, psw, res
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1000$: .word 000000, 000000, cp0z00, 000000
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.word 000011, 000000, cp0000, 000011
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.word 000011, 000110, cp0000, 000101
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.word 000011, 001100, cp0000, 001111
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.word 110000, 011000, cpn000, 101000
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.word 110000, 110000, cp0z00, 000000
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1010$:
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;
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9999$: iot ; end of test E1.1
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;
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; Test X1.2 -- xor znvc=1 ++++++++++++++++++++++++++++++++++++++++++++
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; check xor with all cc's set; register destination
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;
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te0102: mov #1000$,r4 ; setup data pointer
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mov #1010$,r5 ; setup end pointer
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mov #cp.psw,r3 ; setup psw pointer
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100$: mov (r4)+,r0 ; load src
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mov (r4)+,r1 ; load dst
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scc ; nzvc=1
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xor r0,r1 ; xor
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cmp (r4)+,(r3) ; check psw
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beq .+4
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halt
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cmp (r4)+,r1 ; check
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beq .+4
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halt
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cmp r4,r5
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blo 100$
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jmp 9999$
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;
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; dst, src, psw, res
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1000$: .word 000000, 000000, cp0z0c, 000000
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.word 000011, 000000, cp000c, 000011
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.word 000011, 000110, cp000c, 000101
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.word 000011, 001100, cp000c, 001111
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.word 110000, 011000, cpn00c, 101000
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.word 110000, 110000, cp0z0c, 000000
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1010$:
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;
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9999$: iot ; end of test E1.2
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;
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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cmp tstno,#5. ; all tests done ?
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cmp tstno,#10. ; all tests done ?
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beq .+4
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halt
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;
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jmp loop
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;
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.end start
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@@ -1,4 +1,4 @@
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; $Id: cpu_selftest.mac 1254 2022-07-13 06:16:19Z mueller $
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; $Id: cpu_selftest.mac 1258 2022-07-18 10:07:22Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -213,3 +213,5 @@ ta0201:
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; END OF ALL TESTS - loop closure --------------------------------------------
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;
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jmp loop
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;
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.end start
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