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add pdp11_dmpcnt: performance counters
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wfjm
parent
970be66d07
commit
f838fc3b4d
10
rtl/w11a/pdp11_dmpcnt.vbom
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10
rtl/w11a/pdp11_dmpcnt.vbom
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# libs
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../vlib/slvtypes.vhd
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../vlib/memlib/memlib.vhd
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../vlib/rbus/rblib.vhd
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# components
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[sim]../vlib/memlib/ram_1swar_gen.vbom
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[xst]../vlib/memlib/ram_1swar_gen_unisim.vbom
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[vsyn]../vlib/memlib/ram_1swar_gen.vbom
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# design
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pdp11_dmpcnt.vhd
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382
rtl/w11a/pdp11_dmpcnt.vhd
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382
rtl/w11a/pdp11_dmpcnt.vhd
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-- $Id: pdp11_dmpcnt.vhd 1051 2018-09-29 15:29:11Z mueller $
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--
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-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: pdp11_dmpcnt - syn
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-- Description: pdp11: debug&moni: performance counters
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--
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-- Dependencies: -
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-- Test bench: -
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--
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-- Target Devices: generic
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-- Tool versions: ise 14.7; viv 2017.2-2018.2; ghdl 0.34
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2018-09-23 1050 14.7 131013 xc6slx16-2 250 337 20 121 s 6.5
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--
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-- Revision History: -
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-- Date Rev Version Comment
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-- 2018-09-29 1051 1.0 Initial version
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-- 2018-09-23 1050 0.1 First draft
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------------------------------------------------------------------------------
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--
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-- rbus registers:
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--
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-- Addr Bits Name r/w/f Function
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-- 00 cntl -/w/f Control register
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-- 15 ainc -/w/- enable address autoinc
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-- 13:09 caddr -/w/- counter address
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-- 07:00 vers r/-/- counter layout version
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-- 02:00 func 0/-/f change run status if != noop
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-- 0xx noop
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-- 100 sto stop
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-- 101 sta start
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-- 110 clr clear
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-- 111 loa load caddr
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-- 01 stat r/-/- Status register
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-- 15 ainc r/-/- enable address autoinc
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-- 13:09 caddr r/-/- counter address
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-- 08 waddr r/-/- word address
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-- 00 run r/-/- running
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-- 10 data r/-/- Data register
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.rblib.all;
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-- ----------------------------------------------------------------------------
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entity pdp11_dmpcnt_precnt is -- pre-counter
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port (
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CLK : in slbit; -- clock
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CLR : in slbit; -- clear
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ENA : in slbit; -- count
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DOUT : out slv5 -- data
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);
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end pdp11_dmpcnt_precnt;
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architecture syn of pdp11_dmpcnt_precnt is
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signal R_CNT : slv5 := (others=>'0');
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begin
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proc_cnt: process (CLK)
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begin
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if rising_edge(CLK) then
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if CLR = '1' then
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R_CNT <= (others=>'0');
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else
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if ENA = '1' then
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R_CNT <= slv(unsigned(R_CNT) + 1);
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end if;
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end if;
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end if;
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end process proc_cnt;
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DOUT <= R_CNT;
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end syn;
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-- ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.slvtypes.all;
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use work.memlib.all;
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use work.rblib.all;
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entity pdp11_dmpcnt is -- debug&moni: performance counters
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generic (
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RB_ADDR : slv16 := slv(to_unsigned(16#0060#,16)); -- rbus address
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VERS : slv8 := slv(to_unsigned(1, 8)); -- counter layout version
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CENA : slv32 := (others=>'1')); -- counter enables
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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RB_MREQ : in rb_mreq_type; -- rbus: request
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RB_SRES : out rb_sres_type; -- rbus: response
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PERFSIG : in slv32 -- signals to count
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);
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end pdp11_dmpcnt;
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architecture syn of pdp11_dmpcnt is
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constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
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constant rbaddr_stat : slv2 := "01"; -- stat address offset
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constant rbaddr_data : slv2 := "10"; -- data address offset
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constant cntl_rbf_ainc : integer := 15;
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subtype cntl_rbf_caddr is integer range 13 downto 9;
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subtype cntl_rbf_vers is integer range 7 downto 0;
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subtype cntl_rbf_func is integer range 2 downto 0;
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constant stat_rbf_ainc : integer := 15;
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subtype stat_rbf_caddr is integer range 13 downto 9;
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constant stat_rbf_waddr : integer := 8;
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constant stat_rbf_run : integer := 0;
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constant func_sto : slv3 := "100"; -- func: stop
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constant func_sta : slv3 := "101"; -- func: start
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constant func_clr : slv3 := "110"; -- func: clear
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constant func_loa : slv3 := "111"; -- func: load
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type regs_type is record
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rbsel : slbit; -- rbus select
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run : slbit; -- run flag
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saddr : slv5; -- scan address
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raddr : slv5; -- read address (counter)
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waddr : slbit; -- read address (word)
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ainc : slbit; -- enable ddress autoinc
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zbusy : slbit; -- clear in progress
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dval : slbit; -- data valid
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dout : slv32; -- read data (valid if dval=1)
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psig : slv32; -- signals, floped
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end record regs_type;
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constant regs_init : regs_type := (
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'0','0', -- rbsel,run
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(others=>'0'), -- saddr
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(others=>'0'), -- raddr
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'0','0','0','0', -- waddr,ainc,zbusy,dval
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(others=>'0'), -- dout
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(others=>'0') -- psig
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);
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signal R_REGS : regs_type := regs_init;
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signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
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type pre_do_type is array (31 downto 0) of slv5;
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signal PRE_CLR : slv32 := (others=>'0');
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signal PRE_DO : pre_do_type := (others=> (others => '0'));
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signal MEM_DI : slv32 := (others=>'0');
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signal MEM_DO : slv32 := (others=>'0');
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begin
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MEM : ram_1swar_gen
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generic map (
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AWIDTH => 5,
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DWIDTH => 32)
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port map (
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CLK => CLK,
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WE => '1',
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ADDR => R_REGS.saddr,
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DI => MEM_DI,
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DO => MEM_DO
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);
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PRE: for i in 31 downto 0 generate
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ENA: if CENA(i)='1' generate
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CNT : entity work.pdp11_dmpcnt_precnt
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port map (
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CLK => CLK,
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CLR => PRE_CLR(i),
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ENA => R_REGS.psig(i),
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DOUT => PRE_DO(i)
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);
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end generate ENA;
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end generate PRE;
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proc_cnt: process (R_REGS, PRE_DO, MEM_DO)
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variable iclr : slv32 := (others=>'0');
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variable ipdo : slv32 := (others=>'0');
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variable icnt : slv32 := (others=>'0');
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variable imdi : slv32 := (others=>'0');
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constant ipdo_pad : slv(31 downto 5) := (others=>'0');
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constant icnt_pad : slv(31 downto 1) := (others=>'0');
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begin
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iclr := (others=>'0');
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iclr(to_integer(unsigned(R_REGS.saddr))) := '1';
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ipdo := ipdo_pad & PRE_DO(to_integer(unsigned(R_REGS.saddr)));
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icnt := icnt_pad & R_REGS.psig(to_integer(unsigned(R_REGS.saddr)));
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PRE_CLR <= iclr;
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if R_REGS.zbusy = '0' then
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imdi := slv(unsigned(MEM_DO) + unsigned(ipdo) + unsigned(icnt));
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else
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imdi := (others=>'0');
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end if;
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MEM_DI <= imdi;
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end process proc_cnt;
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proc_regs: process (CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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R_REGS <= regs_init;
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else
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R_REGS <= N_REGS;
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end if;
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end if;
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end process proc_regs;
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proc_next: process (R_REGS, RB_MREQ, PERFSIG, MEM_DO)
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variable r : regs_type := regs_init;
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variable n : regs_type := regs_init;
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variable irb_ack : slbit := '0';
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variable irb_busy : slbit := '0';
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variable irb_err : slbit := '0';
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variable irb_dout : slv16 := (others=>'0');
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variable irbena : slbit := '0';
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begin
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r := R_REGS;
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n := R_REGS;
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irb_ack := '0';
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irb_busy := '0';
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irb_err := '0';
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irb_dout := (others=>'0');
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irbena := RB_MREQ.re or RB_MREQ.we;
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-- rbus address decoder
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n.rbsel := '0';
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if RB_MREQ.aval='1' then
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if RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
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n.rbsel := '1';
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end if;
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end if;
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if r.run = '1' then -- if running
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n.psig := PERFSIG; -- capture performance signals
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else
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n.psig := (others=>'0'); -- otherwise ignore them
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end if;
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n.saddr := slv(unsigned(r.saddr) + 1); -- scan counter (always running)
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-- capture data in dout buffer if scan=read address and looking at lsb and
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-- if either data not valid or no rbus cycle active. this ensures that
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-- dval waits end, and also that data isn't changing during rbus active.
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if r.saddr = r.raddr and r.waddr = '0' and
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(r.dval='0' or r.rbsel='0') then
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n.dout := MEM_DO; -- capture data
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n.dval := '1';
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end if;
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-- rbus transactions
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if r.rbsel = '1' then
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irb_ack := irbena; -- ack all accesses
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case RB_MREQ.addr(1 downto 0) is
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when rbaddr_cntl => -- cntl ------------------
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if RB_MREQ.we = '1' then
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case RB_MREQ.din(cntl_rbf_func) is
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when func_sto => -- func: stop ------------
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n.run := '0';
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when func_sta => -- func: start -----------
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n.run := '1';
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when func_clr => -- func: clear -----------
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n.run := '0';
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if r.zbusy = '0' then
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n.zbusy := '1';
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n.saddr := (others=>'0');
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n.raddr := (others=>'0');
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n.waddr := '0';
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n.ainc := '0';
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irb_busy := '1';
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else
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if r.saddr = "11111" then
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n.zbusy := '0';
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n.dval := '0';
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else
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irb_busy := '1';
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end if;
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end if;
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when func_loa => -- func: load ------------
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n.ainc := RB_MREQ.din(cntl_rbf_ainc);
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n.raddr := RB_MREQ.din(cntl_rbf_caddr);
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n.waddr := '0';
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n.dval := '0';
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when others => null; -- <> --------------------
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end case;
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end if;
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when rbaddr_stat => -- stat ------------------
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irb_err := RB_MREQ.we;
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when rbaddr_data => -- data ------------------
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-- write to data is an error
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if RB_MREQ.we='1' then
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irb_err := '1'; -- error
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end if;
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if RB_MREQ.re = '1' then
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if r.dval = '0' then
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irb_busy := '1';
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else
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n.waddr := not r.waddr;
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if r.ainc='1' and r.waddr = '1' then -- autoinc and wrap ?
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n.raddr := slv(unsigned(r.raddr) + 1);
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n.dval := '0';
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end if;
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end if;
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end if;
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when others => irb_err := '1'; -- <> --------------------
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end case;
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end if;
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-- rbus output driver
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if r.rbsel = '1' then
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case RB_MREQ.addr(1 downto 0) is
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when rbaddr_cntl => null; -- cntl ------------------
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irb_dout(cntl_rbf_vers) := VERS;
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when rbaddr_stat => -- stat ------------------
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irb_dout(stat_rbf_ainc) := r.ainc;
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irb_dout(stat_rbf_caddr) := r.raddr;
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irb_dout(stat_rbf_waddr) := r.waddr;
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irb_dout(stat_rbf_run) := r.run;
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when rbaddr_data => -- data ------------------
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if r.waddr = '0' then
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irb_dout := r.dout(15 downto 0);
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else
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irb_dout := r.dout(31 downto 16);
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end if;
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when others => null;
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end case;
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end if;
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N_REGS <= n;
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RB_SRES.ack <= irb_ack;
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RB_SRES.err <= irb_err;
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RB_SRES.busy <= irb_busy;
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RB_SRES.dout <= irb_dout;
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end process proc_next;
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end syn;
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