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19 Commits 1 Branch 40 Tags
b06cbef00a5b26138965ac9d4e4627d4f08ff90f
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7 Commits

Author SHA1 Message Date
Walter F.J. Mueller
99de9893cb - interim release w11a_V0.562 (untagged) 
- C++ and Tcl based backend server: many support classes for interfacing to 
  w11 system designs, and the associated Tcl bindings.
- add 'asm-11', a simple, Macro-11 syntax subset combatible, assembler. 
- use now doxygen 1.8.3.1, generate c++,tcl, and vhdl source docs
 2013-04-13 17:13:15 +00:00
Walter F.J. Mueller
3f455d5236 - interim release w11a_V0.532 (untagged) 
- re-organize modules 'human I/O' interface on Digilent boards
- add test designs for 'human I/O' interface for atlys,nexys2, and s3board
- small updates in crc8 and dcm areas
- with one exception all vhdl sources use now numeric_std
 2011-11-20 12:31:43 +00:00
Walter F.J. Mueller
e15295649e - interim release w11a_V0.531 (untagged) 
- many small changes to prepare upcoming support for Spartan-6 and
  usage of Cypress FX2 USB interface on nexys2/3 and atlys boards
 2011-09-12 20:52:31 +00:00
Walter F.J. Mueller
c3d40ba4b9 - interim release w11a_V0.52 (untagged) 
- migrate to rbus protocol verion 3
  - reorganize rbus and rlink modules, many renames
 2011-01-02 13:39:34 +00:00
Walter F.J. Mueller
16ce5b2091 - interim release w11a_V0.51 (untagged) 
- migrate to ibus protocol verion 2
  - nexys2 systems now with DCM derived system clock supported
  - sys_w11a_n2 now runs with 58 MHz clksys
 2010-11-27 23:17:50 +00:00
Walter F.J. Mueller
6a9b05b201 additional documentation 2010-07-22 19:46:37 +00:00
Walter F.J. Mueller
3335c61549 initial source upload (no docs yet) 2010-07-09 18:14:38 +00:00