5 Commits

Author	SHA1	Message	Date
Walter F.J. Mueller	cbd8ce3468	- interim release w11a_V0.56 (untagged) ... - re-organized handling of board and derived clocks in test benches - added message filter definitions for some designs (.mfset files) - added Cypress EZ-USB FX2 controller (USB interface) - added firmware for EZ-USB FX2 supporting jtag access and data transfer - FPGA configure over USB now supported directly in make build flow - added test systems for USB testing and rlink over USB verification - no functional change of w11a CPU core or any pre-existing test systems - Note: Carefully read the disclaimer about usage of USB VID/PID numbers in the file README_USB-VID-PID.txt. You'll be responsible for any misuse of the defaults provided with the project sources !!	2013-01-02 21:06:53 +00:00
Walter F.J. Mueller	3f455d5236	- interim release w11a_V0.532 (untagged) ... - re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std	2011-11-20 12:31:43 +00:00
Walter F.J. Mueller	c3d40ba4b9	- interim release w11a_V0.52 (untagged) ... - migrate to rbus protocol verion 3 - reorganize rbus and rlink modules, many renames	2011-01-02 13:39:34 +00:00
Walter F.J. Mueller	16ce5b2091	- interim release w11a_V0.51 (untagged) ... - migrate to ibus protocol verion 2 - nexys2 systems now with DCM derived system clock supported - sys_w11a_n2 now runs with 58 MHz clksys	2010-11-27 23:17:50 +00:00
Walter F.J. Mueller	3335c61549	initial source upload (no docs yet)	2010-07-09 18:14:38 +00:00