5 Commits

Author	SHA1	Message	Date
wfjm	8d323848b3	Some minor updates ... - top-level Makefile: drop w11a/arty_bram - sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6)) - RtclGet.ipp: use const& for oper() of string& and Rtime& - *.Doxyfile: bump version to 0.77 - comment and docu updates	2019-02-24 12:50:38 +01:00
wfjm	cb7b906089	Add memory tester for Arty and MIG ... - sys_tst_sram_arty: add system and tb - sramif_mig_arty: add SRAM to DDR via MIG adapter for arty - cdc_pulse: add clock domain crossing for a slowly changing value - cdc_vector_s0: add ENA port (now used in cdc_pulse) - tst_mig/util.tcl: test_rwait: add optional lena argument - viv_tools_build.tcl: downgrade SSN critical warnings to warnings	2019-01-03 09:15:07 +01:00
wfjm	14362b2a56	Add basic DDR memory support ... - arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model	2018-12-31 10:00:14 +01:00
wfjm	05c7d937c7	Add Digilent Cmod A7 (35 die size) support ... - general board support - c7_sram_memctl: SRAM memory controller (incl tb) - is61wv5128bll: simple memory model (incl tb) - sn_humanio_emu_rbus: human IO emulator - 92-retro-usb-persistent.rules: add more board rules - associated changes - sn_humanio_rbus: add stat_rbf_emu (=0); single cycle btn pulses - rgbdrv_analog(_rbus): add ACTLOW generic to invert output polarity - ti_rri: adopt Digilent autodetect for CmodA7 - add systems - tst_rlink: rlink tested - tst_sram: SRAM tester - w11a: w11a system with 672 kB memory (512 SRAM + 160 BRAM)	2017-06-28 22:29:09 +02:00
Walter F.J. Mueller	51cb648e54	docu tune-ups; some more README.md	2016-12-23 15:51:48 +01:00