wfjm.w11/doc/w11a_known_differences.md

Summary of known differences and limitations for w11a CPU and systems

This file lists the differences and limitations of the w11 CPU and systems. The issues of the w11 CPU and systems are listed in a separate document README_known_issues.md.

Known differences between w11a and KB11-C (11/70)

• instruction behavior
  • Instruction fetch after SPL
  • CLR and SXT do a write
  • State of N and Z and registers after a DIV abort with V=1
• instruction abort handling
  • PC is incremented before an instruction fetch abort
• vector flow abort handling
  • SP decremented only once after 1st vector push abort
• stack limit and stack error behavior
  • Stack limit checks done independent of register set
  • No unconditional instruction fetch after stack error abort
• memory management behavior
  • MMR0 instruction complete implementation differences
  • MMU traps not suppressed when MMU register accessed
  • MMU aborts have priority over NXM aborts
  • MMR0 abort flags are set when stack limit abort done
• not implemented 11/70 features
  • 18-bit UNIBUS address space not mapped
  • MMU maintenance mode not implemented
  • no cache parity and minimal subset of memory system controls
• other differences
  • Usage of 11/70 SYSID register

All points relate to very 11/70 specific behavior, no operating system depends on them, therefore they are considered acceptable implementation differences.

For a comprehensive list of differences between all PDP-11 models consult the PDP-11 Family Differences Table in

• PDP-11 Architecture Handbook (1983) Appendix B p303
• PDP-11 MICRO/PDP-11 Handbook 1983-84 Appendix G p387
• and also PDP-11 family differences appendix

Also helpful are the differences sections in the manuals of for processors

• T-11 User's Guide 1982 Appendix B p221
• J-11 Programmer's Reference Rev 2.04 1982 Section 11.0 p37 (focus on registers and instructions)
• KD11-E (11/34) Central Processor Manual Table 2-8 p41

Known limitations

• some programs use timing loops based on the execution speed of the original processors. This can lead to spurious timeouts, especially in old test programs.
  A 'CPU throttle mechanism' will be added in a future version to circumvent this for some old test codes.
• the emulated I/O can lead to apparently slow device reaction times, especially when the server runs as a normal user process. This can lead to a timeout, again mostly in test programs.
  A 'watch dog' mechanism will be added in a future version which suspends the CPU when the server doesn't respond fast enough.

Known differences between Simh, E11, a real 11/70, and w11a

The Simh and E11 simulators do not model some 11/70 details that have no effect on normal operation for performance reasons. Test codes, like xxdp diagostic programs or the tcodes of the w11 verification suite are sometimes sensitive to those details, so the most relevant ones are listed under

• Known differences between SimH, 11/70, and w11a
• Known differences between E11, 11/70, and w11a