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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
This directory sub-tree contains a wide range of support modules and is organized in
| Directory | Content |
|---|---|
| cdclib | modules for clock domain crossing |
| comlib | modules for communication |
| genlib | grab bag of other modules |
| memlib | wrappers for distributed and block RAM; fifos |
| rbus | modules for rbus fabric; some basic rbus devices |
| rlink | rlink interface |
| serport | serial port interface |
| simlib | helper modules for test benches |
| xlib | warppers for some Xilinx components |