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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
278 lines
12 KiB
VHDL
278 lines
12 KiB
VHDL
-- $Id: memlib.vhd 1109 2019-02-09 13:36:41Z mueller $
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--
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-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Package Name: memlib
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-- Description: Basic memory components: single/dual port synchronous and
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-- asynchronus rams; Fifo's.
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--
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-- Dependencies: -
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-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
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-- Revision History:
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-- Date Rev Version Comment
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-- 2019-02-03 1109 1.1.1 add fifo_simple_dram
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-- 2016-03-25 751 1.1 add fifo_2c_dram2
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-- 2008-03-08 123 1.0.3 add ram_2swsr_xfirst_gen_unisim
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-- 2008-03-02 122 1.0.2 change generic default for BRAM models
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-- 2007-12-27 106 1.0.1 add fifo_2c_dram
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-- 2007-06-03 45 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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package memlib is
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component ram_1swar_gen is -- RAM, 1 sync w asyn r port
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generic (
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AWIDTH : positive := 4; -- address port width
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DWIDTH : positive := 16); -- data port width
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port (
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CLK : in slbit; -- clock
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WE : in slbit; -- write enable
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ADDR : in slv(AWIDTH-1 downto 0); -- address port
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DI : in slv(DWIDTH-1 downto 0); -- data in port
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DO : out slv(DWIDTH-1 downto 0) -- data out port
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);
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end component;
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component ram_1swar_1ar_gen is -- RAM, 1 sync w asyn r + 1 asyn r port
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generic (
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AWIDTH : positive := 4; -- address port width
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DWIDTH : positive := 16); -- data port width
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port (
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CLK : in slbit; -- clock
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WE : in slbit; -- write enable (port A)
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DI : in slv(DWIDTH-1 downto 0); -- data in (port A)
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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end component;
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component ram_1swsr_wfirst_gen is -- RAM, 1 sync r/w ports, write first
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generic (
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AWIDTH : positive := 10; -- address port width
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DWIDTH : positive := 16); -- data port width
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port(
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CLK : in slbit; -- clock
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EN : in slbit; -- enable
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WE : in slbit; -- write enable
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ADDR : in slv(AWIDTH-1 downto 0); -- address port
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DI : in slv(DWIDTH-1 downto 0); -- data in port
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DO : out slv(DWIDTH-1 downto 0) -- data out port
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);
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end component;
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component ram_1swsr_rfirst_gen is -- RAM, 1 sync r/w ports, read first
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generic (
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AWIDTH : positive := 11; -- address port width
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DWIDTH : positive := 9); -- data port width
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port(
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CLK : in slbit; -- clock
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EN : in slbit; -- enable
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WE : in slbit; -- write enable
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ADDR : in slv(AWIDTH-1 downto 0); -- address port
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DI : in slv(DWIDTH-1 downto 0); -- data in port
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DO : out slv(DWIDTH-1 downto 0) -- data out port
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);
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end component;
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component ram_2swsr_wfirst_gen is -- RAM, 2 sync r/w ports, write first
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generic (
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AWIDTH : positive := 11; -- address port width
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DWIDTH : positive := 9); -- data port width
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port(
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CLKA : in slbit; -- clock port A
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CLKB : in slbit; -- clock port B
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ENA : in slbit; -- enable port A
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ENB : in slbit; -- enable port B
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WEA : in slbit; -- write enable port A
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WEB : in slbit; -- write enable port B
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DIA : in slv(DWIDTH-1 downto 0); -- data in port A
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DIB : in slv(DWIDTH-1 downto 0); -- data in port B
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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end component;
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component ram_2swsr_rfirst_gen is -- RAM, 2 sync r/w ports, read first
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generic (
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AWIDTH : positive := 11; -- address port width
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DWIDTH : positive := 9); -- data port width
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port(
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CLKA : in slbit; -- clock port A
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CLKB : in slbit; -- clock port B
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ENA : in slbit; -- enable port A
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ENB : in slbit; -- enable port B
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WEA : in slbit; -- write enable port A
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WEB : in slbit; -- write enable port B
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DIA : in slv(DWIDTH-1 downto 0); -- data in port A
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DIB : in slv(DWIDTH-1 downto 0); -- data in port B
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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end component;
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component ram_1swsr_xfirst_gen_unisim is -- RAM, 1 sync r/w port
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generic (
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AWIDTH : positive := 11; -- address port width
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DWIDTH : positive := 9; -- data port width
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WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
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port(
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CLK : in slbit; -- clock
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EN : in slbit; -- enable
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WE : in slbit; -- write enable
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ADDR : in slv(AWIDTH-1 downto 0); -- address
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DI : in slv(DWIDTH-1 downto 0); -- data in
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DO : out slv(DWIDTH-1 downto 0) -- data out
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);
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end component;
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component ram_2swsr_xfirst_gen_unisim is -- RAM, 2 sync r/w ports
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generic (
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AWIDTH : positive := 11; -- address port width
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DWIDTH : positive := 9; -- data port width
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WRITE_MODE : string := "READ_FIRST"); -- write mode: (READ|WRITE)_FIRST
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port(
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CLKA : in slbit; -- clock port A
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CLKB : in slbit; -- clock port B
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ENA : in slbit; -- enable port A
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ENB : in slbit; -- enable port B
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WEA : in slbit; -- write enable port A
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WEB : in slbit; -- write enable port B
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ADDRA : in slv(AWIDTH-1 downto 0); -- address port A
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ADDRB : in slv(AWIDTH-1 downto 0); -- address port B
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DIA : in slv(DWIDTH-1 downto 0); -- data in port A
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DIB : in slv(DWIDTH-1 downto 0); -- data in port B
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DOA : out slv(DWIDTH-1 downto 0); -- data out port A
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DOB : out slv(DWIDTH-1 downto 0) -- data out port B
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);
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end component;
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component fifo_simple_dram is -- fifo, CE/WE interface, dram based
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generic (
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AWIDTH : positive := 6; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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CE : in slbit; -- clock enable
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WE : in slbit; -- write enable
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DI : in slv(DWIDTH-1 downto 0); -- input data
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DO : out slv(DWIDTH-1 downto 0); -- output data
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EMPTY : out slbit; -- fifo empty status
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FULL : out slbit; -- fifo full status
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SIZE : out slv(AWIDTH-1 downto 0) -- number of used slots
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);
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end component;
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component fifo_1c_dram_raw is -- fifo, 1 clock, dram based, raw
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generic (
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AWIDTH : positive := 4; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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WE : in slbit; -- write enable
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RE : in slbit; -- read enable
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DI : in slv(DWIDTH-1 downto 0); -- input data
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DO : out slv(DWIDTH-1 downto 0); -- output data
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SIZE : out slv(AWIDTH-1 downto 0); -- number of used slots
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EMPTY : out slbit; -- empty flag
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FULL : out slbit -- full flag
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);
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end component;
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component fifo_1c_dram is -- fifo, 1 clock, dram based
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generic (
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AWIDTH : positive := 4; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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DI : in slv(DWIDTH-1 downto 0); -- input data
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ENA : in slbit; -- write enable
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BUSY : out slbit; -- write port hold
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DO : out slv(DWIDTH-1 downto 0); -- output data
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VAL : out slbit; -- read valid
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HOLD : in slbit; -- read hold
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SIZE : out slv(AWIDTH downto 0) -- number of used slots
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);
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end component;
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component fifo_1c_bubble is -- fifo, 1 clock, bubble regs
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generic (
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NSTAGE : positive := 4; -- number of stages
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DWIDTH : positive := 16); -- data width
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port (
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CLK : in slbit; -- clock
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RESET : in slbit; -- reset
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DI : in slv(DWIDTH-1 downto 0); -- input data
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ENA : in slbit; -- write enable
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BUSY : out slbit; -- write port hold
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DO : out slv(DWIDTH-1 downto 0); -- output data
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VAL : out slbit; -- read valid
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HOLD : in slbit -- read hold
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);
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end component;
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component fifo_2c_dram is -- fifo, 2 clock, dram based
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generic (
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AWIDTH : positive := 4; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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port (
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CLKW : in slbit; -- clock (write side)
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CLKR : in slbit; -- clock (read side)
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RESETW : in slbit; -- W|reset from write side
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RESETR : in slbit; -- R|reset from read side
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DI : in slv(DWIDTH-1 downto 0); -- W|input data
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ENA : in slbit; -- W|write enable
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BUSY : out slbit; -- W|write port hold
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DO : out slv(DWIDTH-1 downto 0); -- R|output data
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VAL : out slbit; -- R|read valid
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HOLD : in slbit; -- R|read hold
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SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
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SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
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);
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end component;
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component fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2)
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generic (
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AWIDTH : positive := 4; -- address width (sets size)
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DWIDTH : positive := 16); -- data width
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port (
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CLKW : in slbit; -- clock (write side)
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CLKR : in slbit; -- clock (read side)
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RESETW : in slbit; -- W|reset from write side
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RESETR : in slbit; -- R|reset from read side
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DI : in slv(DWIDTH-1 downto 0); -- W|input data
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ENA : in slbit; -- W|write enable
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BUSY : out slbit; -- W|write port hold
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DO : out slv(DWIDTH-1 downto 0); -- R|output data
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VAL : out slbit; -- R|read valid
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HOLD : in slbit; -- R|read hold
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SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
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SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
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);
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end component;
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end package memlib;
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