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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
10 lines
186 B
Plaintext
10 lines
186 B
Plaintext
# libs
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../../slvtypes.vhd
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../../simlib/simlib.vhd
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# components
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../../simlib/simclkv.vbom
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../../simlib/simclkcnt.vbom
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${uut := tbd_fifo_2c_dram2.vbom} -UUT
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# design
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tb_fifo_2c_dram2.vhd
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