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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
7 lines
122 B
Plaintext
7 lines
122 B
Plaintext
# configure for _*sim case
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# configure
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uut = tbd_fifo_2c_dram_ssim.vhd
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# design
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tb_fifo_2c_dram.vbom
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@top:tb_fifo_2c_dram
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