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0c395856d7
- add fifo_simple_dram: simple fifo with CE/WE interface, dram based - add test benches for fifo_simple_dram, fifo_2c_dram, and fifo_2c_dram2 - add simclkv: test bench clock generator with variable period
85 lines
2.9 KiB
VHDL
85 lines
2.9 KiB
VHDL
-- $Id: tbd_fifo_2c_dram.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tbd_fifo_2c_dram - syn
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-- Description: Wrapper for fifo_2c_dram to avoid records & generics. It
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-- has a port interface which will not be modified by xst
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-- synthesis (no records, no generic port).
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--
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-- Dependencies: fifo_2c_dram
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--
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-- To test: fifo_2c_dram
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--
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-- Target Devices: generic
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--
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-- Synthesized (xst):
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-- Date Rev ise Target flop lutl lutm slic t peri
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-- 2010-04-24 281 11.4 L68 xc3s1000-4 36 43 32 52 s 8.34
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--
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-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 11.4; ghdl 0.18-0.26
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-- Revision History:
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-- Date Rev Version Comment
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-- 2007-12-28 106 1.0 Initial version
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.slvtypes.all;
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use work.memlib.all;
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entity tbd_fifo_2c_dram is -- fifo, 2 clock, dram based [tb design]
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-- generic: AWIDTH=4; DWIDTH=16
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port (
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CLKW : in slbit; -- clock (write side)
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CLKR : in slbit; -- clock (read side)
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RESETW : in slbit; -- reset (synchronous with CLKW)
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RESETR : in slbit; -- reset (synchronous with CLKR)
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DI : in slv16; -- input data
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ENA : in slbit; -- write enable
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BUSY : out slbit; -- write port hold
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DO : out slv16; -- output data
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VAL : out slbit; -- read valid
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HOLD : in slbit; -- read hold
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SIZEW : out slv4; -- number slots to write (synch w/ CLKW)
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SIZER : out slv4 -- number slots to read (synch w/ CLKR)
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);
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end tbd_fifo_2c_dram;
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architecture syn of tbd_fifo_2c_dram is
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begin
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FIFO : fifo_2c_dram
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generic map (
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AWIDTH => 4,
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DWIDTH => 16)
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port map (
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CLKW => CLKW,
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CLKR => CLKR,
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RESETW => RESETW,
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RESETR => RESETR,
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DI => DI,
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ENA => ENA,
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BUSY => BUSY,
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DO => DO,
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VAL => VAL,
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HOLD => HOLD,
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SIZEW => SIZEW,
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SIZER => SIZER
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);
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end syn;
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