mirror of
https://github.com/wfjm/w11.git
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14362b2a56
- arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model
This directory sub-tree contains a wide range of support modules and is organized in
| Directory | Content |
|---|---|
| cdclib | modules for clock domain crossing |
| comlib | modules for communication |
| genlib | grab bag of other modules |
| memlib | wrappers for distributed and block RAM; fifos |
| rbus | modules for rbus fabric; some basic rbus devices |
| rlink | rlink interface |
| serport | serial port interface |
| simlib | helper modules for test benches |
| xlib | warppers for some Xilinx components |